Initial commit
This commit is contained in:
domenico
@@ -0,0 +1,42 @@
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From 2d3da16317086ba6048c601ee88cdc96f19fd741 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Fri, 7 Feb 2020 12:40:26 -0800
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Subject: [PATCH 01/12] net: thunderx: use proper interface type for RGMII
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The configuration of the OCTEONTX XCV_DLL_CTL register via
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xcv_init_hw() is such that the RGMII RX delay is bypassed
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leaving the RGMII TX delay enabled in the MAC:
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/* Configure DLL - enable or bypass
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* TX no bypass, RX bypass
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*/
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cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL);
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cfg &= ~0xFF03;
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cfg |= CLKRX_BYP;
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writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL);
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This would coorespond to a interface type of PHY_INTERFACE_MODE_RGMII_RXID
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and not PHY_INTERFACE_MODE_RGMII.
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Fixing this allows RGMII PHY drivers to do the right thing (enable
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RX delay in the PHY) instead of erroneously enabling both delays in the
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PHY.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c
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+++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c
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@@ -1048,7 +1048,7 @@ static int phy_interface_mode(u8 lmac_ty
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if (lmac_type == BGX_MODE_QSGMII)
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return PHY_INTERFACE_MODE_QSGMII;
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if (lmac_type == BGX_MODE_RGMII)
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- return PHY_INTERFACE_MODE_RGMII;
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+ return PHY_INTERFACE_MODE_RGMII_RXID;
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return PHY_INTERFACE_MODE_SGMII;
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}
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@@ -0,0 +1,41 @@
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From e8287ec10f21877eb0ac4c1fb4e89e42d8bc10da Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Wed, 11 Mar 2020 08:19:45 -0700
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Subject: [PATCH 2/7] gpio: thunderx: fix irq_request_resources
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If there are no parent resources do not call irq_chip_request_resources_parent
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at all as this will return an error.
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This resolves a regression where devices using a thunderx gpio as an interrupt
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would fail probing.
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Fixes: 0d04d0c ("gpio: thunderx: Use the default parent apis for {request,release}_resources")
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/gpio/gpio-thunderx.c | 9 ++++++---
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1 file changed, 6 insertions(+), 3 deletions(-)
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--- a/drivers/gpio/gpio-thunderx.c
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+++ b/drivers/gpio/gpio-thunderx.c
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@@ -363,15 +363,18 @@ static int thunderx_gpio_irq_request_res
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{
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struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
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struct thunderx_gpio *txgpio = txline->txgpio;
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+ struct irq_data *parent_data = data->parent_data;
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int r;
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r = gpiochip_lock_as_irq(&txgpio->chip, txline->line);
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if (r)
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return r;
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- r = irq_chip_request_resources_parent(data);
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- if (r)
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- gpiochip_unlock_as_irq(&txgpio->chip, txline->line);
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+ if (parent_data && parent_data->chip->irq_request_resources) {
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+ r = irq_chip_request_resources_parent(data);
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+ if (r)
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+ gpiochip_unlock_as_irq(&txgpio->chip, txline->line);
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+ }
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return r;
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}
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@@ -0,0 +1,57 @@
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From 097cc81ee5c15913ad330baffff2e3dea09bdad0 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Thu, 30 Aug 2018 15:16:08 -0700
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Subject: [PATCH] can: mcp251x: convert driver to half-duplex SPI
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Some SPI host controllers such as the Cavium Thunder TX do not support
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full-duplex SPI. Using half-duplex transfers allows the driver to work
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with those host controllers.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/net/can/spi/mcp251x.c | 15 ++++++++-------
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1 file changed, 8 insertions(+), 7 deletions(-)
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--- a/drivers/net/can/spi/mcp251x.c
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+++ b/drivers/net/can/spi/mcp251x.c
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@@ -291,23 +291,23 @@ static u8 mcp251x_read_reg(struct spi_de
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priv->spi_tx_buf[0] = INSTRUCTION_READ;
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priv->spi_tx_buf[1] = reg;
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- mcp251x_spi_trans(spi, 3);
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- val = priv->spi_rx_buf[2];
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+ spi_write_then_read(spi, priv->spi_tx_buf, 2, &val, 1);
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return val;
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}
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static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2)
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{
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+ u8 val[4] = {0};
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struct mcp251x_priv *priv = spi_get_drvdata(spi);
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priv->spi_tx_buf[0] = INSTRUCTION_READ;
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priv->spi_tx_buf[1] = reg;
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- mcp251x_spi_trans(spi, 4);
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+ spi_write_then_read(spi, priv->spi_tx_buf, 2, val, 2);
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- *v1 = priv->spi_rx_buf[2];
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- *v2 = priv->spi_rx_buf[3];
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+ *v1 = val[0];
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+ *v2 = val[1];
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}
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static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val)
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@@ -398,8 +398,9 @@ static void mcp251x_hw_rx_frame(struct s
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buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
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} else {
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priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
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- mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
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- memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
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+ spi_write_then_read(spi, priv->spi_tx_buf, 1, priv->spi_rx_buf,
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+ SPI_TRANSFER_BUF_LEN);
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+ memcpy(buf + 1, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN - 1);
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}
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}
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@@ -0,0 +1,59 @@
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From d0ff7a1bcfe886cab1a237895b08ac51ecfe10e7 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Wed, 10 Apr 2019 08:00:47 -0700
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Subject: [PATCH 04/12] PCI: add quirk for Gateworks PLX PEX860x switch with
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GPIO PERST#
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Gateworks boards use PLX PEX860x switches where downstream ports
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have their PERST# driven from the PEX GPIO.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/pci/quirks.c | 32 ++++++++++++++++++++++++++++++++
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1 file changed, 32 insertions(+)
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--- a/drivers/pci/quirks.c
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+++ b/drivers/pci/quirks.c
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@@ -25,6 +25,7 @@
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#include <linux/ktime.h>
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#include <linux/mm.h>
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#include <linux/nvme.h>
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+#include <linux/of.h>
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#include <linux/platform_data/x86/apple.h>
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#include <linux/pm_runtime.h>
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#include <linux/suspend.h>
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@@ -5783,3 +5784,34 @@ static void apex_pci_fixup_class(struct
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}
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DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
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PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
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+
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+#ifdef CONFIG_PCI_HOST_THUNDER_PEM
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+/*
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+ * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
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+ * as they are used for slots1-7 PERST#
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+ */
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+static void newport_pciesw_early_fixup(struct pci_dev *dev)
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+{
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+ u32 dw;
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+
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+ if (!of_machine_is_compatible("gw,newport"))
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+ return;
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+
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+ if (dev->devfn != 0)
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+ return;
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+
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+ dev_info(&dev->dev, "de-asserting PERST#\n");
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+ pci_read_config_dword(dev, 0x62c, &dw);
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+ dw |= 0xaaa8; /* GPIO1-7 outputs */
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+ pci_write_config_dword(dev, 0x62c, dw);
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+
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+ pci_read_config_dword(dev, 0x644, &dw);
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+ dw |= 0xfe; /* GPIO1-7 output high */
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+ pci_write_config_dword(dev, 0x644, dw);
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+
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+ msleep(100);
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+}
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, newport_pciesw_early_fixup);
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, newport_pciesw_early_fixup);
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, newport_pciesw_early_fixup);
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+#endif /* CONFIG_PCI_HOST_THUNDER_PEM */
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