Initial commit

target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef RTL838X_IOREMAP_H_
+#define RTL838X_IOREMAP_H_
+
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
+{
+	return phys_addr;
+}
+
+static inline int is_rtl838x_internal_registers(phys_addr_t offset)
+{
+	/* IO-Block */
+	if (offset >= 0xb8000000 && offset < 0xb9000000)
+		return 1;
+	/* Switch block */
+	if (offset >= 0xbb000000 && offset < 0xbc000000)
+		return 1;
+	return 0;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+					 unsigned long flags)
+{
+	if (is_rtl838x_internal_registers(offset))
+		return (void __iomem *)offset;
+	return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+	return is_rtl838x_internal_registers((unsigned long)addr);
+}
+
+#endif

target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h

@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#ifndef _RTL83XX_IRQ_H_
+#define _RTL83XX_IRQ_H_
+
+#define NR_IRQS 32
+#include_next <irq.h>
+
+/* Global Interrupt Mask Register */
+#define RTL83XX_ICTL_GIMR	0x00
+/* Global Interrupt Status Register */
+#define RTL83XX_ICTL_GISR	0x04
+
+#define RTL83XX_IRQ_CPU_BASE	0
+#define RTL83XX_IRQ_CPU_NUM	8
+#define RTL83XX_IRQ_ICTL_BASE	(RTL83XX_IRQ_CPU_BASE + RTL83XX_IRQ_CPU_NUM)
+#define RTL83XX_IRQ_ICTL_NUM	32
+
+/* Cascaded interrupts */
+#define RTL83XX_ICTL1_IRQ	(RTL83XX_IRQ_CPU_BASE + 2)
+#define RTL83XX_ICTL2_IRQ	(RTL83XX_IRQ_CPU_BASE + 3)
+#define RTL83XX_ICTL3_IRQ	(RTL83XX_IRQ_CPU_BASE + 4)
+#define RTL83XX_ICTL4_IRQ	(RTL83XX_IRQ_CPU_BASE + 5)
+#define RTL83XX_ICTL5_IRQ	(RTL83XX_IRQ_CPU_BASE + 6)
+
+/* Interrupt routing register */
+#define RTL83XX_IRR0		0x08
+#define RTL83XX_IRR1		0x0c
+#define RTL83XX_IRR2		0x10
+#define RTL83XX_IRR3		0x14
+
+/* Cascade map */
+#define UART0_CASCADE		2
+#define UART1_CASCADE		1
+#define TC0_CASCADE		5
+#define TC1_CASCADE		1
+#define TC2_CASCADE		1
+#define TC3_CASCADE		1
+#define TC4_CASCADE		1
+#define OCPTO_CASCADE		1
+#define HLXTO_CASCADE		1
+#define SLXTO_CASCADE		1
+#define NIC_CASCADE		4
+#define GPIO_ABCD_CASCADE	4
+#define GPIO_EFGH_CASCADE	4
+#define RTC_CASCADE		4
+#define	SWCORE_CASCADE		3
+#define WDT_IP1_CASCADE		4
+#define WDT_IP2_CASCADE		5
+#define USB_H2_CASCADE		1
+
+/* Pack cascade map into interrupt routing registers */
+#define RTL83XX_IRR0_SETTING (\
+	(UART0_CASCADE		<< 28) | \
+	(UART1_CASCADE		<< 24) | \
+	(TC0_CASCADE		<< 20) | \
+	(TC1_CASCADE		<< 16) | \
+	(OCPTO_CASCADE		<< 12) | \
+	(HLXTO_CASCADE		<< 8)  | \
+	(SLXTO_CASCADE		<< 4)  | \
+	(NIC_CASCADE		<< 0))
+#define RTL83XX_IRR1_SETTING (\
+	(GPIO_ABCD_CASCADE	<< 28) | \
+	(GPIO_EFGH_CASCADE	<< 24) | \
+	(RTC_CASCADE		<< 20) | \
+	(SWCORE_CASCADE		<< 16))
+#define RTL83XX_IRR2_SETTING	0
+#define RTL83XX_IRR3_SETTING	0
+
+/* On the RTL8390 there is no GPIO_EFGH and RTC IRQ */
+#define RTL8390_IRR1_SETTING (\
+	(GPIO_ABCD_CASCADE	<< 28) | \
+	(SWCORE_CASCADE		<< 16))
+
+/* The RTL9300 has a different external IRQ numbering scheme */
+#define RTL9300_IRR0_SETTING (\
+	(UART1_CASCADE		<< 28) | \
+	(UART0_CASCADE		<< 24) | \
+	(USB_H2_CASCADE		<< 16) | \
+	(NIC_CASCADE		<< 0))
+#define RTL9300_IRR1_SETTING (\
+	(SWCORE_CASCADE		<< 28))
+#define RTL9300_IRR2_SETTING (\
+	(GPIO_ABCD_CASCADE	<< 20) | \
+	(TC4_CASCADE		<< 12) | \
+	(TC3_CASCADE		<< 8) | \
+	(TC2_CASCADE		<< 4) | \
+	(TC1_CASCADE		<< 0))
+#define RTL9300_IRR3_SETTING (\
+	(TC0_CASCADE		<< 28) | \
+	(WDT_IP1_CASCADE	<< 20))
+
+#endif /* _RTL83XX_IRQ_H_ */

target/linux/realtek/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h

@@ -0,0 +1,418 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ * Copyright (C) 2020 B. Koblitz
+ */
+#ifndef _MACH_RTL838X_H_
+#define _MACH_RTL838X_H_
+
+#include <asm/types.h>
+/*
+ * Register access macros
+ */
+
+#define RTL838X_SW_BASE		((volatile void *) 0xBB000000)
+
+#define rtl83xx_r32(reg)	readl(reg)
+#define rtl83xx_w32(val, reg)	writel(val, reg)
+#define rtl83xx_w32_mask(clear, set, reg) rtl83xx_w32((rtl83xx_r32(reg) & ~(clear)) | (set), reg)
+
+#define rtl83xx_r8(reg)		readb(reg)
+#define rtl83xx_w8(val, reg)	writeb(val, reg)
+
+#define sw_r32(reg)		readl(RTL838X_SW_BASE + reg)
+#define sw_w32(val, reg)	writel(val, RTL838X_SW_BASE + reg)
+#define sw_w32_mask(clear, set, reg)	\
+				sw_w32((sw_r32(reg) & ~(clear)) | (set), reg)
+#define sw_r64(reg)		((((u64)readl(RTL838X_SW_BASE + reg)) << 32) | \
+				readl(RTL838X_SW_BASE + reg + 4))
+
+#define sw_w64(val, reg)	do { \
+					writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \
+					writel((u32)((val) & 0xffffffff), \
+							RTL838X_SW_BASE + reg + 4); \
+				} while (0)
+
+/*
+ * SPRAM
+ */
+#define RTL838X_ISPRAM_BASE	0x0
+#define RTL838X_DSPRAM_BASE	0x0
+
+/*
+ * IRQ Controller
+ */
+#define RTL838X_IRQ_CPU_BASE	0
+#define RTL838X_IRQ_CPU_NUM	8
+#define RTL838X_IRQ_ICTL_BASE	(RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM)
+#define RTL838X_IRQ_ICTL_NUM	32
+
+#define RTL83XX_IRQ_UART0		31
+#define RTL83XX_IRQ_UART1		30
+#define RTL83XX_IRQ_TC0			29
+#define RTL83XX_IRQ_TC1			28
+#define RTL83XX_IRQ_OCPTO		27
+#define RTL83XX_IRQ_HLXTO		26
+#define RTL83XX_IRQ_SLXTO		25
+#define RTL83XX_IRQ_NIC			24
+#define RTL83XX_IRQ_GPIO_ABCD		23
+#define RTL83XX_IRQ_GPIO_EFGH		22
+#define RTL83XX_IRQ_RTC			21
+#define RTL83XX_IRQ_SWCORE		20
+#define RTL83XX_IRQ_WDT_IP1		19
+#define RTL83XX_IRQ_WDT_IP2		18
+
+#define RTL9300_UART1_IRQ		31
+#define RTL9300_UART0_IRQ		30
+#define RTL9300_USB_H2_IRQ		28
+#define RTL9300_NIC_IRQ			24
+#define RTL9300_SWCORE_IRQ		23
+#define RTL9300_GPIO_ABC_IRQ		13
+#define RTL9300_TC4_IRQ			11
+#define RTL9300_TC3_IRQ			10
+#define RTL9300_TC2_IRQ			 9
+#define RTL9300_TC1_IRQ			 8
+#define RTL9300_TC0_IRQ			 7
+
+
+/*
+ * MIPS32R2 counter
+ */
+#define RTL838X_COMPARE_IRQ	(RTL838X_IRQ_CPU_BASE + 7)
+
+/*
+ *  ICTL
+ *  Base address 0xb8003000UL
+ */
+#define RTL838X_ICTL1_IRQ	(RTL838X_IRQ_CPU_BASE + 2)
+#define RTL838X_ICTL2_IRQ	(RTL838X_IRQ_CPU_BASE + 3)
+#define RTL838X_ICTL3_IRQ	(RTL838X_IRQ_CPU_BASE + 4)
+#define RTL838X_ICTL4_IRQ	(RTL838X_IRQ_CPU_BASE + 5)
+#define RTL838X_ICTL5_IRQ	(RTL838X_IRQ_CPU_BASE + 6)
+
+#define GIMR			(0x00)
+#define UART0_IE		(1 << 31)
+#define UART1_IE		(1 << 30)
+#define TC0_IE			(1 << 29)
+#define TC1_IE			(1 << 28)
+#define OCPTO_IE		(1 << 27)
+#define HLXTO_IE		(1 << 26)
+#define SLXTO_IE		(1 << 25)
+#define NIC_IE			(1 << 24)
+#define GPIO_ABCD_IE		(1 << 23)
+#define GPIO_EFGH_IE		(1 << 22)
+#define RTC_IE			(1 << 21)
+#define WDT_IP1_IE		(1 << 19)
+#define WDT_IP2_IE		(1 << 18)
+
+#define GISR			(0x04)
+#define UART0_IP		(1 << 31)
+#define UART1_IP		(1 << 30)
+#define TC0_IP			(1 << 29)
+#define TC1_IP			(1 << 28)
+#define OCPTO_IP		(1 << 27)
+#define HLXTO_IP		(1 << 26)
+#define SLXTO_IP		(1 << 25)
+#define NIC_IP			(1 << 24)
+#define GPIO_ABCD_IP		(1 << 23)
+#define GPIO_EFGH_IP		(1 << 22)
+#define RTC_IP			(1 << 21)
+#define WDT_IP1_IP		(1 << 19)
+#define WDT_IP2_IP		(1 << 18)
+
+
+/* Interrupt Routing Selection */
+#define UART0_RS		2
+#define UART1_RS		1
+#define TC0_RS			5
+#define TC1_RS			1
+#define OCPTO_RS		1
+#define HLXTO_RS		1
+#define SLXTO_RS		1
+#define NIC_RS			4
+#define GPIO_ABCD_RS		4
+#define GPIO_EFGH_RS		4
+#define RTC_RS			4
+#define	SWCORE_RS		3
+#define WDT_IP1_RS		4
+#define WDT_IP2_RS		5
+
+/* Interrupt IRQ Assignments */
+#define UART0_IRQ		31
+#define UART1_IRQ		30
+#define TC0_IRQ			29
+#define TC1_IRQ			28
+#define OCPTO_IRQ		27
+#define HLXTO_IRQ		26
+#define SLXTO_IRQ		25
+#define NIC_IRQ			24
+#define GPIO_ABCD_IRQ		23
+#define GPIO_EFGH_IRQ		22
+#define RTC_IRQ			21
+#define	SWCORE_IRQ		20
+#define WDT_IP1_IRQ		19
+#define WDT_IP2_IRQ		18
+
+#define SYSTEM_FREQ		200000000
+#define RTL838X_UART0_BASE	((volatile void *)(0xb8002000UL))
+#define RTL838X_UART0_BAUD	38400  /* ex. 19200 or 38400 or 57600 or 115200 */
+#define RTL838X_UART0_FREQ	(SYSTEM_FREQ - RTL838X_UART0_BAUD * 24)
+#define RTL838X_UART0_MAPBASE	0x18002000UL
+#define RTL838X_UART0_MAPSIZE	0x100
+#define RTL838X_UART0_IRQ	UART0_IRQ
+
+#define RTL838X_UART1_BASE	((volatile void *)(0xb8002100UL))
+#define RTL838X_UART1_BAUD	38400  /* ex. 19200 or 38400 or 57600 or 115200 */
+#define RTL838X_UART1_FREQ	(SYSTEM_FREQ - RTL838X_UART1_BAUD * 24)
+#define RTL838X_UART1_MAPBASE	0x18002100UL
+#define RTL838X_UART1_MAPSIZE	0x100
+#define RTL838X_UART1_IRQ	UART1_IRQ
+
+#define UART0_RBR		(RTL838X_UART0_BASE + 0x000)
+#define UART0_THR		(RTL838X_UART0_BASE + 0x000)
+#define UART0_DLL		(RTL838X_UART0_BASE + 0x000)
+#define UART0_IER		(RTL838X_UART0_BASE + 0x004)
+#define UART0_DLM		(RTL838X_UART0_BASE + 0x004)
+#define UART0_IIR		(RTL838X_UART0_BASE + 0x008)
+#define UART0_FCR		(RTL838X_UART0_BASE + 0x008)
+#define UART0_LCR		(RTL838X_UART0_BASE + 0x00C)
+#define UART0_MCR		(RTL838X_UART0_BASE + 0x010)
+#define UART0_LSR		(RTL838X_UART0_BASE + 0x014)
+
+#define UART1_RBR		(RTL838X_UART1_BASE + 0x000)
+#define UART1_THR		(RTL838X_UART1_BASE + 0x000)
+#define UART1_DLL		(RTL838X_UART1_BASE + 0x000)
+#define UART1_IER		(RTL838X_UART1_BASE + 0x004)
+#define UART1_DLM		(RTL838X_UART1_BASE + 0x004)
+#define UART1_IIR		(RTL838X_UART1_BASE + 0x008)
+#define UART1_FCR		(RTL838X_UART1_BASE + 0x008)
+#define UART1_LCR		(RTL838X_UART1_BASE + 0x00C)
+#define UART1_MCR		(RTL838X_UART1_BASE + 0x010)
+#define UART1_LSR		(RTL838X_UART1_BASE + 0x014)
+
+/*
+ * Memory Controller
+ */
+#define MC_MCR			0xB8001000
+#define MC_MCR_VAL		0x00000000
+
+#define MC_DCR			0xB8001004
+#define MC_DCR0_VAL		0x54480000
+
+#define MC_DTCR			0xB8001008
+#define MC_DTCR_VAL		0xFFFF05C0
+
+/*
+ * GPIO
+ */
+#define GPIO_CTRL_REG_BASE		((volatile void *) 0xb8003500)
+#define RTL838X_GPIO_PABC_CNR		(GPIO_CTRL_REG_BASE + 0x0)
+#define RTL838X_GPIO_PABC_TYPE		(GPIO_CTRL_REG_BASE + 0x04)
+#define RTL838X_GPIO_PABC_DIR		(GPIO_CTRL_REG_BASE + 0x8)
+#define RTL838X_GPIO_PABC_DATA		(GPIO_CTRL_REG_BASE + 0xc)
+#define RTL838X_GPIO_PABC_ISR		(GPIO_CTRL_REG_BASE + 0x10)
+#define RTL838X_GPIO_PAB_IMR		(GPIO_CTRL_REG_BASE + 0x14)
+#define RTL838X_GPIO_PC_IMR		(GPIO_CTRL_REG_BASE + 0x18)
+
+#define RTL838X_MODEL_NAME_INFO		(0x00D4)
+#define RTL839X_MODEL_NAME_INFO		(0x0FF0)
+#define RTL93XX_MODEL_NAME_INFO		(0x0004)
+
+#define RTL838X_LED_GLB_CTRL		(0xA000)
+#define RTL839X_LED_GLB_CTRL		(0x00E4)
+#define RTL9302_LED_GLB_CTRL		(0xcc00)
+#define RTL930X_LED_GLB_CTRL		(0xC400)
+#define RTL931X_LED_GLB_CTRL		(0x0600)
+
+#define RTL838X_EXT_GPIO_DIR		(0xA08C)
+#define RTL839X_EXT_GPIO_DIR		(0x0214)
+#define RTL838X_EXT_GPIO_DATA		(0xA094)
+#define RTL839X_EXT_GPIO_DATA		(0x021c)
+#define RTL838X_EXT_GPIO_INDRT_ACCESS	(0xA09C)
+#define RTL839X_EXT_GPIO_INDRT_ACCESS	(0x0224)
+#define RTL838X_EXTRA_GPIO_CTRL		(0xA0E0)
+#define RTL838X_DMY_REG5		(0x0144)
+#define RTL838X_EXTRA_GPIO_CTRL		(0xA0E0)
+
+#define RTL838X_GMII_INTF_SEL		(0x1000)
+#define RTL838X_IO_DRIVING_ABILITY_CTRL	(0x1010)
+
+#define RTL838X_GPIO_A7		31
+#define RTL838X_GPIO_A6		30
+#define RTL838X_GPIO_A5		29
+#define RTL838X_GPIO_A4		28
+#define RTL838X_GPIO_A3		27
+#define RTL838X_GPIO_A2		26
+#define RTL838X_GPIO_A1		25
+#define RTL838X_GPIO_A0		24
+#define RTL838X_GPIO_B7		23
+#define RTL838X_GPIO_B6		22
+#define RTL838X_GPIO_B5		21
+#define RTL838X_GPIO_B4		20
+#define RTL838X_GPIO_B3		19
+#define RTL838X_GPIO_B2		18
+#define RTL838X_GPIO_B1		17
+#define RTL838X_GPIO_B0		16
+#define RTL838X_GPIO_C7		15
+#define RTL838X_GPIO_C6		14
+#define RTL838X_GPIO_C5		13
+#define RTL838X_GPIO_C4		12
+#define RTL838X_GPIO_C3		11
+#define RTL838X_GPIO_C2		10
+#define RTL838X_GPIO_C1		9
+#define RTL838X_GPIO_C0		8
+
+#define RTL838X_INT_RW_CTRL		(0x0058)
+#define RTL838X_EXT_VERSION		(0x00D0)
+#define RTL838X_PLL_CML_CTRL		(0x0FF8)
+#define RTL838X_STRAP_DBG		(0x100C)
+
+/*
+ * Reset
+ */
+#define	RGCR				(0x1E70)
+#define RTL838X_RST_GLB_CTRL_0		(0x003c)
+#define RTL838X_RST_GLB_CTRL_1		(0x0040)
+#define RTL839X_RST_GLB_CTRL		(0x0014)
+#define RTL930X_RST_GLB_CTRL_0		(0x000c)
+#define RTL931X_RST_GLB_CTRL		(0x0400)
+
+/* LED control by switch */
+#define RTL838X_LED_MODE_SEL		(0x1004)
+#define RTL838X_LED_MODE_CTRL		(0xA004)
+#define RTL838X_LED_P_EN_CTRL		(0xA008)
+
+/* LED control by software */
+#define RTL838X_LED_SW_CTRL		(0x0128)
+#define RTL839X_LED_SW_CTRL		(0xA00C)
+#define RTL838X_LED_SW_P_EN_CTRL	(0xA010)
+#define RTL839X_LED_SW_P_EN_CTRL	(0x012C)
+#define RTL838X_LED0_SW_P_EN_CTRL	(0xA010)
+#define RTL839X_LED0_SW_P_EN_CTRL	(0x012C)
+#define RTL838X_LED1_SW_P_EN_CTRL	(0xA014)
+#define RTL839X_LED1_SW_P_EN_CTRL	(0x0130)
+#define RTL838X_LED2_SW_P_EN_CTRL	(0xA018)
+#define RTL839X_LED2_SW_P_EN_CTRL	(0x0134)
+#define RTL838X_LED_SW_P_CTRL		(0xA01C)
+#define RTL839X_LED_SW_P_CTRL		(0x0144)
+
+#define RTL839X_MAC_EFUSE_CTRL		(0x02ac)
+
+/*
+ * MDIO via Realtek's SMI interface
+ */
+#define RTL838X_SMI_GLB_CTRL		(0xa100)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_0	(0xa1b8)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_1	(0xa1bc)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_2	(0xa1c0)
+#define RTL838X_SMI_ACCESS_PHY_CTRL_3	(0xa1c4)
+#define RTL838X_SMI_PORT0_5_ADDR_CTRL	(0xa1c8)
+#define RTL838X_SMI_POLL_CTRL		(0xa17c)
+
+#define RTL839X_SMI_GLB_CTRL		(0x03f8)
+#define RTL839X_SMI_PORT_POLLING_CTRL	(0x03fc)
+#define RTL839X_PHYREG_ACCESS_CTRL	(0x03DC)
+#define RTL839X_PHYREG_CTRL		(0x03E0)
+#define RTL839X_PHYREG_PORT_CTRL	(0x03E4)
+#define RTL839X_PHYREG_DATA_CTRL	(0x03F0)
+#define RTL839X_PHYREG_MMD_CTRL		(0x3F4)
+
+#define RTL930X_SMI_GLB_CTRL		(0xCA00)
+#define RTL930X_SMI_POLL_CTRL		(0xca90)
+#define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08)
+#define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C)
+#define RTL930X_SMI_PORT0_5_ADDR	(0xCB80)
+#define RTL930X_SMI_ACCESS_PHY_CTRL_0	(0xCB70)
+#define RTL930X_SMI_ACCESS_PHY_CTRL_1	(0xCB74)
+#define RTL930X_SMI_ACCESS_PHY_CTRL_2	(0xCB78)
+#define RTL930X_SMI_ACCESS_PHY_CTRL_3	(0xCB7C)
+
+#define RTL931X_SMI_GLB_CTRL1		(0x0CBC)
+#define RTL931X_SMI_GLB_CTRL0		(0x0CC0)
+#define RTL931X_SMI_PORT_POLLING_CTRL	(0x0CCC)
+#define RTL931X_SMI_INDRT_ACCESS_CTRL_0	(0x0C00)
+#define RTL931X_SMI_INDRT_ACCESS_CTRL_1	(0x0C04)
+#define RTL931X_SMI_INDRT_ACCESS_CTRL_2	(0x0C08)
+#define RTL931X_SMI_INDRT_ACCESS_CTRL_3	(0x0C10)
+#define RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL (0x0C14)
+#define RTL931X_SMI_INDRT_ACCESS_MMD_CTRL (0xC18)
+
+#define RTL930X_SMI_GLB_CTRL		(0xCA00)
+#define RTL930X_SMI_POLL_CTRL		(0xca90)
+#define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08)
+#define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C)
+#define RTL930X_SMI_PORT0_5_ADDR	(0xCB80)
+#define RTL930X_SMI_ACCESS_PHY_CTRL_0	(0xCB70)
+#define RTL930X_SMI_ACCESS_PHY_CTRL_1	(0xCB74)
+#define RTL930X_SMI_ACCESS_PHY_CTRL_2	(0xCB78)
+#define RTL930X_SMI_ACCESS_PHY_CTRL_3	(0xCB7C)
+
+#define RTL931X_SMI_GLB_CTRL1		(0x0CBC)
+#define RTL931X_SMI_GLB_CTRL0		(0x0CC0)
+#define RTL931X_SMI_PORT_POLLING_CTRL	(0x0CCC)
+#define RTL931X_SMI_INDRT_ACCESS_CTRL_0	(0x0C00)
+#define RTL931X_SMI_INDRT_ACCESS_CTRL_1	(0x0C04)
+#define RTL931X_SMI_INDRT_ACCESS_CTRL_2	(0x0C08)
+#define RTL931X_SMI_INDRT_ACCESS_CTRL_3	(0x0C10)
+
+/*
+ * Switch interrupts
+ */
+#define RTL838X_IMR_GLB			(0x1100)
+#define RTL838X_IMR_PORT_LINK_STS_CHG	(0x1104)
+#define RTL838X_ISR_GLB_SRC		(0x1148)
+#define RTL838X_ISR_PORT_LINK_STS_CHG	(0x114C)
+
+#define RTL839X_IMR_GLB			(0x0064)
+#define RTL839X_IMR_PORT_LINK_STS_CHG	(0x0068)
+#define RTL839X_ISR_GLB_SRC		(0x009c)
+#define RTL839X_ISR_PORT_LINK_STS_CHG	(0x00a0)
+
+#define RTL930X_IMR_GLB			(0xC628)
+#define RTL930X_IMR_PORT_LINK_STS_CHG	(0xC62C)
+#define RTL930X_ISR_GLB			(0xC658)
+#define RTL930X_ISR_PORT_LINK_STS_CHG	(0xC660)
+
+// IMR_GLB does not exit on RTL931X
+#define RTL931X_IMR_PORT_LINK_STS_CHG	(0x126C)
+#define RTL931X_ISR_GLB_SRC		(0x12B4)
+#define RTL931X_ISR_PORT_LINK_STS_CHG	(0x12B8)
+
+/* Definition of family IDs */
+#define RTL8389_FAMILY_ID   (0x8389)
+#define RTL8328_FAMILY_ID   (0x8328)
+#define RTL8390_FAMILY_ID   (0x8390)
+#define RTL8350_FAMILY_ID   (0x8350)
+#define RTL8380_FAMILY_ID   (0x8380)
+#define RTL8330_FAMILY_ID   (0x8330)
+#define RTL9300_FAMILY_ID   (0x9300)
+#define RTL9310_FAMILY_ID   (0x9310)
+
+/* Basic SoC Features */
+#define RTL838X_CPU_PORT			28
+#define RTL839X_CPU_PORT			52
+#define RTL930X_CPU_PORT			28
+#define RTL931X_CPU_PORT			56
+
+struct rtl83xx_soc_info {
+	unsigned char *name;
+	unsigned int id;
+	unsigned int family;
+	unsigned char *compatible;
+	volatile void *sw_base;
+	volatile void *icu_base;
+	int cpu_port;
+};
+
+/* rtl83xx-related functions used across subsystems */
+int rtl838x_smi_wait_op(int timeout);
+int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
+int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val);
+
+#endif   /* _MACH_RTL838X_H_ */

target/linux/realtek/files-5.4/arch/mips/rtl838x/Makefile

@@ -0,0 +1,5 @@
+#
+# Makefile for the rtl838x specific parts of the kernel
+#
+
+obj-y := setup.o prom.o irq.o

target/linux/realtek/files-5.4/arch/mips/rtl838x/Platform

@@ -0,0 +1,6 @@
+#
+# Realtek RTL838x SoCs
+#
+platform-$(CONFIG_RTL838X) += rtl838x/
+cflags-$(CONFIG_RTL838X)   += -I$(srctree)/arch/mips/include/asm/mach-rtl838x/
+load-$(CONFIG_RTL838X)     += 0xffffffff80000000

target/linux/realtek/files-5.4/arch/mips/rtl838x/irq.c

@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Realtek RTL83XX architecture specific IRQ handling
+ *
+ * based on the original BSP
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ * Copyright (C) 2020 B. Koblitz
+ * Copyright (C) 2020 Bert Vermeulen <bert@biot.com>
+ * Copyright (C) 2020 John Crispin <john@phrozen.org>
+ */
+
+#include <linux/irqchip.h>
+#include <linux/spinlock.h>
+#include <linux/of_address.h>
+#include <asm/irq_cpu.h>
+#include <linux/of_irq.h>
+#include <asm/cevt-r4k.h>
+
+#include <mach-rtl83xx.h>
+#include "irq.h"
+
+#define REALTEK_CPU_IRQ_SHARED0		(MIPS_CPU_IRQ_BASE + 2)
+#define REALTEK_CPU_IRQ_UART		(MIPS_CPU_IRQ_BASE + 3)
+#define REALTEK_CPU_IRQ_SWITCH		(MIPS_CPU_IRQ_BASE + 4)
+#define REALTEK_CPU_IRQ_SHARED1		(MIPS_CPU_IRQ_BASE + 5)
+#define REALTEK_CPU_IRQ_EXTERNAL	(MIPS_CPU_IRQ_BASE + 6)
+#define REALTEK_CPU_IRQ_COUNTER		(MIPS_CPU_IRQ_BASE + 7)
+
+#define REG(x)				(rtl83xx_ictl_base + x)
+
+extern struct rtl83xx_soc_info soc_info;
+
+static DEFINE_RAW_SPINLOCK(irq_lock);
+static void __iomem *rtl83xx_ictl_base;
+
+static void rtl83xx_ictl_enable_irq(struct irq_data *i)
+{
+	unsigned long flags;
+	u32 value;
+
+	raw_spin_lock_irqsave(&irq_lock, flags);
+
+	value = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR));
+	value |= BIT(i->hwirq);
+	rtl83xx_w32(value, REG(RTL83XX_ICTL_GIMR));
+
+	raw_spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+static void rtl83xx_ictl_disable_irq(struct irq_data *i)
+{
+	unsigned long flags;
+	u32 value;
+
+	raw_spin_lock_irqsave(&irq_lock, flags);
+
+	value = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR));
+	value &= ~BIT(i->hwirq);
+	rtl83xx_w32(value, REG(RTL83XX_ICTL_GIMR));
+
+	raw_spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+static struct irq_chip rtl83xx_ictl_irq = {
+	.name = "RTL83xx",
+	.irq_enable = rtl83xx_ictl_enable_irq,
+	.irq_disable = rtl83xx_ictl_disable_irq,
+	.irq_ack = rtl83xx_ictl_disable_irq,
+	.irq_mask = rtl83xx_ictl_disable_irq,
+	.irq_unmask = rtl83xx_ictl_enable_irq,
+	.irq_eoi = rtl83xx_ictl_enable_irq,
+};
+
+static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(hw, &rtl83xx_ictl_irq, handle_level_irq);
+
+	return 0;
+}
+
+static const struct irq_domain_ops irq_domain_ops = {
+	.map = intc_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static void rtl838x_irq_dispatch(struct irq_desc *desc)
+{
+	unsigned int pending = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR)) &
+				rtl83xx_r32(REG(RTL83XX_ICTL_GISR));
+
+	if (pending) {
+		struct irq_domain *domain = irq_desc_get_handler_data(desc);
+		generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
+	} else {
+		spurious_interrupt();
+	}
+}
+
+asmlinkage void plat_rtl83xx_irq_dispatch(void)
+{
+	unsigned int pending;
+
+	pending =  read_c0_cause() & read_c0_status() & ST0_IM;
+
+	if (pending & CAUSEF_IP7)
+		do_IRQ(REALTEK_CPU_IRQ_COUNTER);
+
+	else if (pending & CAUSEF_IP6)
+		do_IRQ(REALTEK_CPU_IRQ_EXTERNAL);
+
+	else if (pending & CAUSEF_IP5)
+		do_IRQ(REALTEK_CPU_IRQ_SHARED1);
+
+	else if (pending & CAUSEF_IP4)
+		do_IRQ(REALTEK_CPU_IRQ_SWITCH);
+
+	else if (pending & CAUSEF_IP3)
+		do_IRQ(REALTEK_CPU_IRQ_UART);
+
+	else if (pending & CAUSEF_IP2)
+		do_IRQ(REALTEK_CPU_IRQ_SHARED0);
+
+	else
+		spurious_interrupt();
+}
+
+static int icu_setup_domain(struct device_node *node)
+{
+	struct irq_domain *domain;
+
+	domain = irq_domain_add_simple(node, 32, 0,
+				       &irq_domain_ops, NULL);
+	irq_set_chained_handler_and_data(2, rtl838x_irq_dispatch, domain);
+	irq_set_chained_handler_and_data(3, rtl838x_irq_dispatch, domain);
+	irq_set_chained_handler_and_data(4, rtl838x_irq_dispatch, domain);
+	irq_set_chained_handler_and_data(5, rtl838x_irq_dispatch, domain);
+
+	rtl83xx_ictl_base = of_iomap(node, 0);
+	if (!rtl83xx_ictl_base)
+		return -EINVAL;
+
+	return 0;
+}
+
+static void __init rtl8380_icu_of_init(struct device_node *node, struct device_node *parent)
+{
+	if (icu_setup_domain(node))
+		return;
+
+	/* Disable all cascaded interrupts */
+	rtl83xx_w32(0, REG(RTL83XX_ICTL_GIMR));
+
+	/* Set up interrupt routing */
+	rtl83xx_w32(RTL83XX_IRR0_SETTING, REG(RTL83XX_IRR0));
+	rtl83xx_w32(RTL83XX_IRR1_SETTING, REG(RTL83XX_IRR1));
+	rtl83xx_w32(RTL83XX_IRR2_SETTING, REG(RTL83XX_IRR2));
+	rtl83xx_w32(RTL83XX_IRR3_SETTING, REG(RTL83XX_IRR3));
+
+	/* Clear timer interrupt */
+	write_c0_compare(0);
+
+	/* Enable all CPU interrupts */
+	write_c0_status(read_c0_status() | ST0_IM);
+
+	/* Enable timer0 and uart0 interrupts */
+	rtl83xx_w32(BIT(RTL83XX_IRQ_TC0) | BIT(RTL83XX_IRQ_UART0), REG(RTL83XX_ICTL_GIMR));
+}
+
+static void __init rtl8390_icu_of_init(struct device_node *node, struct device_node *parent)
+{
+	if (icu_setup_domain(node))
+		return;
+
+	/* Disable all cascaded interrupts */
+	rtl83xx_w32(0, REG(RTL83XX_ICTL_GIMR));
+
+	/* Set up interrupt routing */
+	rtl83xx_w32(RTL83XX_IRR0_SETTING, REG(RTL83XX_IRR0));
+	rtl83xx_w32(RTL8390_IRR1_SETTING, REG(RTL83XX_IRR1));
+	rtl83xx_w32(RTL83XX_IRR2_SETTING, REG(RTL83XX_IRR2));
+	rtl83xx_w32(RTL83XX_IRR3_SETTING, REG(RTL83XX_IRR3));
+
+	/* Clear timer interrupt */
+	write_c0_compare(0);
+
+	/* Enable all CPU interrupts */
+	write_c0_status(read_c0_status() | ST0_IM);
+
+	/* Enable timer0 and uart0 interrupts */
+	rtl83xx_w32(BIT(RTL83XX_IRQ_TC0) | BIT(RTL83XX_IRQ_UART0), REG(RTL83XX_ICTL_GIMR));
+}
+
+static void __init rtl9300_icu_of_init(struct device_node *node, struct device_node *parent)
+{
+	pr_info("RTL9300: Setting up IRQs\n");
+	if (icu_setup_domain(node))
+		return;
+
+	/* Disable all cascaded interrupts */
+	rtl83xx_w32(0, REG(RTL83XX_ICTL_GIMR));
+
+	/* Set up interrupt routing */
+	rtl83xx_w32(RTL9300_IRR0_SETTING, REG(RTL83XX_IRR0));
+	rtl83xx_w32(RTL9300_IRR1_SETTING, REG(RTL83XX_IRR1));
+	rtl83xx_w32(RTL9300_IRR2_SETTING, REG(RTL83XX_IRR2));
+	rtl83xx_w32(RTL9300_IRR3_SETTING, REG(RTL83XX_IRR3));
+
+	/* Clear timer interrupt */
+	write_c0_compare(0);
+
+	/* Enable all CPU interrupts */
+	write_c0_status(read_c0_status() | ST0_IM);
+}
+
+static struct of_device_id __initdata of_irq_ids[] = {
+	{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
+	{ .compatible = "realtek,rt8380-intc", .data = rtl8380_icu_of_init },
+	{ .compatible = "realtek,rt8390-intc", .data = rtl8390_icu_of_init },
+	{ .compatible = "realtek,rt9300-intc", .data = rtl9300_icu_of_init },
+	{},
+};
+
+void __init arch_init_irq(void)
+{
+	of_irq_init(of_irq_ids);
+}

target/linux/realtek/files-5.4/arch/mips/rtl838x/prom.c

@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * prom.c
+ * Early intialization code for the Realtek RTL838X SoC
+ *
+ * based on the original BSP by
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ * Copyright (C) 2020 B. Koblitz
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/of_fdt.h>
+#include <linux/libfdt.h>
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+#include <asm/page.h>
+#include <asm/cpu.h>
+
+#include <mach-rtl83xx.h>
+
+extern char arcs_cmdline[];
+extern const char __appended_dtb;
+
+struct rtl83xx_soc_info soc_info;
+const void *fdt;
+
+const char *get_system_type(void)
+{
+	return soc_info.name;
+}
+
+void __init prom_free_prom_memory(void)
+{
+
+}
+
+void __init device_tree_init(void)
+{
+	if (!fdt_check_header(&__appended_dtb)) {
+		fdt = &__appended_dtb;
+		pr_info("Using appended Device Tree.\n");
+	}
+	initial_boot_params = (void *)fdt;
+	unflatten_and_copy_device_tree();
+}
+
+static void __init prom_init_cmdline(void)
+{
+	int argc = fw_arg0;
+	char **argv = (char **) KSEG1ADDR(fw_arg1);
+	int i;
+
+	arcs_cmdline[0] = '\0';
+
+	for (i = 0; i < argc; i++) {
+		char *p = (char *) KSEG1ADDR(argv[i]);
+
+		if (CPHYSADDR(p) && *p) {
+			strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
+			strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
+		}
+	}
+	pr_info("Kernel command line: %s\n", arcs_cmdline);
+}
+
+void __init identify_rtl9302(void)
+{
+	switch (sw_r32(RTL93XX_MODEL_NAME_INFO) & 0xfffffff0) {
+	case 0x93020810:
+		soc_info.name = "RTL9302A 12x2.5G";
+		break;
+	case 0x93021010:
+		soc_info.name = "RTL9302B 8x2.5G";
+		break;
+	case 0x93021810:
+		soc_info.name = "RTL9302C 16x2.5G";
+		break;
+	case 0x93022010:
+		soc_info.name = "RTL9302D 24x2.5G";
+		break;
+	case 0x93020800:
+		soc_info.name = "RTL9302A";
+		break;
+	case 0x93021000:
+		soc_info.name = "RTL9302B";
+		break;
+	case 0x93021800:
+		soc_info.name = "RTL9302C";
+		break;
+	case 0x93022000:
+		soc_info.name = "RTL9302D";
+		break;
+	case 0x93023001:
+		soc_info.name = "RTL9302F";
+		break;
+	default:
+		soc_info.name = "RTL9302";
+	}
+}
+
+void __init prom_init(void)
+{
+	uint32_t model;
+
+	/* uart0 */
+	setup_8250_early_printk_port(0xb8002000, 2, 0);
+
+	model = sw_r32(RTL838X_MODEL_NAME_INFO);
+	pr_info("RTL838X model is %x\n", model);
+	model = model >> 16 & 0xFFFF;
+
+	if ((model != 0x8328) && (model != 0x8330) && (model != 0x8332)
+	    && (model != 0x8380) && (model != 0x8382)) {
+		model = sw_r32(RTL839X_MODEL_NAME_INFO);
+		pr_info("RTL839X model is %x\n", model);
+		model = model >> 16 & 0xFFFF;
+	}
+
+	if ((model & 0x8390) != 0x8380 && (model & 0x8390) != 0x8390) {
+		model = sw_r32(RTL93XX_MODEL_NAME_INFO);
+		pr_info("RTL93XX model is %x\n", model);
+		model = model >> 16 & 0xFFFF;
+	}
+
+	soc_info.id = model;
+
+	switch (model) {
+	case 0x8328:
+		soc_info.name = "RTL8328";
+		soc_info.family = RTL8328_FAMILY_ID;
+		break;
+	case 0x8332:
+		soc_info.name = "RTL8332";
+		soc_info.family = RTL8380_FAMILY_ID;
+		break;
+	case 0x8380:
+		soc_info.name = "RTL8380";
+		soc_info.family = RTL8380_FAMILY_ID;
+		break;
+	case 0x8382:
+		soc_info.name = "RTL8382";
+		soc_info.family = RTL8380_FAMILY_ID;
+		break;
+	case 0x8390:
+		soc_info.name = "RTL8390";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	case 0x8391:
+		soc_info.name = "RTL8391";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	case 0x8392:
+		soc_info.name = "RTL8392";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	case 0x8393:
+		soc_info.name = "RTL8393";
+		soc_info.family = RTL8390_FAMILY_ID;
+		break;
+	case 0x9301:
+		soc_info.name = "RTL9301";
+		soc_info.family = RTL9300_FAMILY_ID;
+		break;
+	case 0x9302:
+		identify_rtl9302();
+		soc_info.family = RTL9300_FAMILY_ID;
+		break;
+	case 0x9313:
+		soc_info.name = "RTL9313";
+		soc_info.family = RTL9310_FAMILY_ID;
+		break;
+	default:
+		soc_info.name = "DEFAULT";
+		soc_info.family = 0;
+	}
+
+	pr_info("SoC Type: %s\n", get_system_type());
+
+	prom_init_cmdline();
+}

target/linux/realtek/files-5.4/arch/mips/rtl838x/setup.c

@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Setup for the Realtek RTL838X SoC:
+ *	Memory, Timer and Serial
+ *
+ * Copyright (C) 2020 B. Koblitz
+ * based on the original BSP by
+ * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
+ *
+ */
+
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/of_fdt.h>
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/bootinfo.h>
+#include <asm/reboot.h>
+#include <asm/time.h>
+#include <asm/prom.h>
+#include <asm/smp-ops.h>
+
+#include "mach-rtl83xx.h"
+
+extern struct rtl83xx_soc_info soc_info;
+
+u32 pll_reset_value;
+
+static void rtl838x_restart(char *command)
+{
+	u32 pll = sw_r32(RTL838X_PLL_CML_CTRL);
+
+	pr_info("System restart.\n");
+	pr_info("PLL control register: %x, applying reset value %x\n",
+		pll, pll_reset_value);
+
+	sw_w32(3, RTL838X_INT_RW_CTRL);
+	sw_w32(pll_reset_value, RTL838X_PLL_CML_CTRL);
+	sw_w32(0, RTL838X_INT_RW_CTRL);
+
+	/* Reset Global Control1 Register */
+	sw_w32(1, RTL838X_RST_GLB_CTRL_1);
+}
+
+static void rtl839x_restart(char *command)
+{
+	/* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */
+	void (*f)(void) = (void *) 0xbfc00000;
+
+	pr_info("System restart.\n");
+	/* Reset SoC */
+	sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL);
+	/* and call reset vector */
+	f();
+	/* If this fails, halt the CPU */
+	while
+		(1);
+}
+
+static void rtl930x_restart(char *command)
+{
+	pr_info("System restart.\n");
+	sw_w32(0x1, RTL930X_RST_GLB_CTRL_0);
+	while
+		(1);
+}
+
+static void rtl931x_restart(char *command)
+{
+	u32 v;
+
+	pr_info("System restart.\n");
+	sw_w32(1, RTL931X_RST_GLB_CTRL);
+	v = sw_r32(RTL931X_RST_GLB_CTRL);
+	sw_w32(0x101, RTL931X_RST_GLB_CTRL);
+	msleep(15);
+	sw_w32(v, RTL931X_RST_GLB_CTRL);
+	msleep(15);
+	sw_w32(0x101, RTL931X_RST_GLB_CTRL);
+}
+
+static void rtl838x_halt(void)
+{
+	pr_info("System halted.\n");
+	while
+		(1);
+}
+
+static void __init rtl838x_setup(void)
+{
+	pr_info("Registering _machine_restart\n");
+	_machine_restart = rtl838x_restart;
+	_machine_halt = rtl838x_halt;
+
+	/* This PLL value needs to be restored before a reset and will then be
+	 * preserved over a SoC reset. A wrong value prevents the SoC from
+	 * connecting to the SPI flash controller at boot and reading the
+	 * reset routine */
+	pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL);
+
+	/* Setup System LED. Bit 15 then allows to toggle it */
+	sw_w32_mask(0, 3 << 16, RTL838X_LED_GLB_CTRL);
+}
+
+static void __init rtl839x_setup(void)
+{
+	pr_info("Registering _machine_restart\n");
+	_machine_restart = rtl839x_restart;
+	_machine_halt = rtl838x_halt;
+
+	/* Setup System LED. Bit 14 of RTL839X_LED_GLB_CTRL then allows to toggle it */
+	sw_w32_mask(0, 3 << 15, RTL839X_LED_GLB_CTRL);
+}
+
+static void __init rtl930x_setup(void)
+{
+	pr_info("Registering _machine_restart\n");
+	_machine_restart = rtl930x_restart;
+	_machine_halt = rtl838x_halt;
+
+	if (soc_info.id == 0x9302)
+		sw_w32_mask(0, 3 << 13, RTL9302_LED_GLB_CTRL);
+	else
+		sw_w32_mask(0, 3 << 13, RTL930X_LED_GLB_CTRL);
+}
+
+static void __init rtl931x_setup(void)
+{
+	pr_info("Registering _machine_restart\n");
+	_machine_restart = rtl931x_restart;
+	_machine_halt = rtl838x_halt;
+	sw_w32_mask(0, 3 << 12, RTL931X_LED_GLB_CTRL);
+}
+
+void __init plat_mem_setup(void)
+{
+	void *dtb;
+
+	set_io_port_base(KSEG1);
+	_machine_restart = rtl838x_restart;
+
+	if (fw_passed_dtb) /* UHI interface */
+		dtb = (void *)fw_passed_dtb;
+	else if (__dtb_start != __dtb_end)
+		dtb = (void *)__dtb_start;
+	else
+		panic("no dtb found");
+
+	/*
+	 * Load the devicetree. This causes the chosen node to be
+	 * parsed resulting in our memory appearing
+	 */
+	__dt_setup_arch(dtb);
+
+	switch (soc_info.family) {
+	case RTL8380_FAMILY_ID:
+		rtl838x_setup();
+		break;
+	case RTL8390_FAMILY_ID:
+		rtl839x_setup();
+		break;
+	case RTL9300_FAMILY_ID:
+		rtl930x_setup();
+		break;
+	case RTL9310_FAMILY_ID:
+		rtl931x_setup();
+		break;
+	}
+}
+
+void __init plat_time_init(void)
+{
+	struct device_node *np;
+	u32 freq = 500000000;
+
+	of_clk_init(NULL);
+	timer_probe();
+
+	np = of_find_node_by_name(NULL, "cpus");
+	if (!np) {
+		pr_err("Missing 'cpus' DT node, using default frequency.");
+	} else {
+		if (of_property_read_u32(np, "frequency", &freq) < 0)
+			pr_err("No 'frequency' property in DT, using default.");
+		else
+			pr_info("CPU frequency from device tree: %dMHz", freq / 1000000);
+		of_node_put(np);
+	}
+
+	mips_hpt_frequency = freq / 2;
+}