Initial commit
This commit is contained in:
domenico
@@ -0,0 +1,404 @@
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From 0720be5371c806c1b89936984a321248fa739bea Mon Sep 17 00:00:00 2001
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From: David Bauer <mail@david-bauer.net>
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Date: Fri, 10 Jul 2020 15:57:46 +0200
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Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S
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This adds support for the NanoPi R2S from FriendlyARM.
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Rockchip RK3328 SoC
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1GB DDR4 RAM
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Gigabit Ethernet (WAN)
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Gigabit Ethernet (USB3) (LAN)
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USB 2.0 Host Port
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MicroSD slot
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Reset button
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WAN - LAN - SYS LED
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Signed-off-by: David Bauer <mail@david-bauer.net>
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---
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arch/arm64/boot/dts/rockchip/Makefile | 1 +
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.../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 368 ++++++++++++++++++
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2 files changed, 369 insertions(+)
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
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--- a/arch/arm64/boot/dts/rockchip/Makefile
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+++ b/arch/arm64/boot/dts/rockchip/Makefile
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@@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
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@@ -0,0 +1,368 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
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+ */
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/input/input.h>
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+#include <dt-bindings/gpio/gpio.h>
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+#include "rk3328.dtsi"
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+
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+/ {
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+ model = "FriendlyElec NanoPi R2S";
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+ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
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+
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+ chosen {
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+ stdout-path = "serial2:1500000n8";
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+ };
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+
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+ gmac_clk: gmac-clock {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ clock-output-names = "gmac_clk";
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+ #clock-cells = <0>;
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+ };
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+
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+ keys {
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+ compatible = "gpio-keys";
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+ pinctrl-0 = <&reset_button_pin>;
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+ pinctrl-names = "default";
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+
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+ reset {
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+ label = "reset";
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+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
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+ linux,code = <KEY_RESTART>;
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+ debounce-interval = <50>;
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+ };
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
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+ pinctrl-names = "default";
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+
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+ lan_led: led-0 {
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+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
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+ label = "nanopi-r2s:green:lan";
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+ };
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+
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+ sys_led: led-1 {
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+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
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+ label = "nanopi-r2s:red:sys";
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+ };
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+
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+ wan_led: led-2 {
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+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
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+ label = "nanopi-r2s:green:wan";
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+ };
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+ };
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+
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+ vcc_io_sdio: sdmmcio-regulator {
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+ compatible = "regulator-gpio";
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+ enable-active-high;
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+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
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+ pinctrl-0 = <&sdio_vcc_pin>;
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+ pinctrl-names = "default";
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+ regulator-name = "vcc_io_sdio";
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+ regulator-always-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-settling-time-us = <5000>;
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+ regulator-type = "voltage";
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+ startup-delay-us = <2000>;
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+ states = <1800000 0x1
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+ 3300000 0x0>;
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+ vin-supply = <&vcc_io_33>;
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+ };
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+
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+ vcc_sd: sdmmc-regulator {
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+ compatible = "regulator-fixed";
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+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
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+ pinctrl-0 = <&sdmmc0m1_gpio>;
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+ pinctrl-names = "default";
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+ regulator-name = "vcc_sd";
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ vin-supply = <&vcc_io_33>;
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+ };
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+
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+ vdd_5v: vdd-5v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vdd_5v";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ };
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+};
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+
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+&cpu0 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu1 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu2 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu3 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&gmac2io {
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+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
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+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
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+ clock_in_out = "input";
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+ phy-handle = <&rtl8211e>;
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+ phy-mode = "rgmii";
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+ phy-supply = <&vcc_io_33>;
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+ pinctrl-0 = <&rgmiim1_pins>;
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+ pinctrl-names = "default";
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+ rx_delay = <0x18>;
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+ snps,aal;
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+ tx_delay = <0x24>;
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+ status = "okay";
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+
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+ mdio {
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+ compatible = "snps,dwmac-mdio";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ rtl8211e: ethernet-phy@1 {
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+ reg = <1>;
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+ pinctrl-0 = <ð_phy_reset_pin>;
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+ pinctrl-names = "default";
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+ reset-assert-us = <10000>;
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+ reset-deassert-us = <50000>;
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+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+};
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+
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+&i2c1 {
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+ status = "okay";
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+
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+ rk805: pmic@18 {
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+ compatible = "rockchip,rk805";
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+ reg = <0x18>;
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+ interrupt-parent = <&gpio1>;
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+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
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+ #clock-cells = <1>;
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+ clock-output-names = "xin32k", "rk805-clkout2";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ pinctrl-0 = <&pmic_int_l>;
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+ pinctrl-names = "default";
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+ rockchip,system-power-controller;
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+ wakeup-source;
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+
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+ vcc1-supply = <&vdd_5v>;
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+ vcc2-supply = <&vdd_5v>;
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+ vcc3-supply = <&vdd_5v>;
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+ vcc4-supply = <&vdd_5v>;
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+ vcc5-supply = <&vcc_io_33>;
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+ vcc6-supply = <&vdd_5v>;
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+
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+ regulators {
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+ vdd_log: DCDC_REG1 {
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+ regulator-name = "vdd_log";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <712500>;
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+ regulator-max-microvolt = <1450000>;
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+ regulator-ramp-delay = <12500>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1000000>;
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+ };
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+ };
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+
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+ vdd_arm: DCDC_REG2 {
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+ regulator-name = "vdd_arm";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <712500>;
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+ regulator-max-microvolt = <1450000>;
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+ regulator-ramp-delay = <12500>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <950000>;
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+ };
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+ };
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+
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+ vcc_ddr: DCDC_REG3 {
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+ regulator-name = "vcc_ddr";
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+ regulator-always-on;
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+ regulator-boot-on;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+
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+ vcc_io_33: DCDC_REG4 {
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+ regulator-name = "vcc_io_33";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <3300000>;
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+ };
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+ };
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+
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+ vcc_18: LDO_REG1 {
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+ regulator-name = "vcc_18";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1800000>;
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+ };
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+ };
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+
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+ vcc18_emmc: LDO_REG2 {
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+ regulator-name = "vcc18_emmc";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1800000>;
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+ };
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+ };
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+
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+ vdd_10: LDO_REG3 {
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+ regulator-name = "vdd_10";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1000000>;
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+ regulator-max-microvolt = <1000000>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1000000>;
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+ };
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+ };
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+ };
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+ };
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+};
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+
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+&io_domains {
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+ pmuio-supply = <&vcc_io_33>;
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+ vccio1-supply = <&vcc_io_33>;
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+ vccio2-supply = <&vcc18_emmc>;
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+ vccio3-supply = <&vcc_io_sdio>;
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+ vccio4-supply = <&vcc_18>;
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+ vccio5-supply = <&vcc_io_33>;
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+ vccio6-supply = <&vcc_io_33>;
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+ status = "okay";
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+};
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+
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+&pinctrl {
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+ button {
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||||
+ reset_button_pin: reset-button-pin {
|
||||
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
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+ };
|
||||
+
|
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+ ethernet-phy {
|
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+ eth_phy_reset_pin: eth-phy-reset-pin {
|
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+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ lan_led_pin: lan-led-pin {
|
||||
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ sys_led_pin: sys-led-pin {
|
||||
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led_pin: wan-led-pin {
|
||||
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sd {
|
||||
+ sdio_vcc_pin: sdio-vcc-pin {
|
||||
+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
|
||||
+ pinctrl-names = "default";
|
||||
+ sd-uhs-sdr12;
|
||||
+ sd-uhs-sdr25;
|
||||
+ sd-uhs-sdr50;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc_sd>;
|
||||
+ vqmmc-supply = <&vcc_io_sdio>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <0>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb20_otg {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@@ -0,0 +1,74 @@
|
||||
From 82985725e071f2a5735052f18e109a32aeac3a0b Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Sun, 26 Jul 2020 02:38:31 +0200
|
||||
Subject: [PATCH] net: usb: r8152: add LED configuration from OF
|
||||
|
||||
This adds the ability to configure the LED configuration register using
|
||||
OF. This way, the correct value for board specific LED configuration can
|
||||
be determined.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
drivers/net/usb/r8152.c | 23 +++++++++++++++++++++++
|
||||
1 file changed, 23 insertions(+)
|
||||
|
||||
--- a/drivers/net/usb/r8152.c
|
||||
+++ b/drivers/net/usb/r8152.c
|
||||
@@ -11,6 +11,7 @@
|
||||
#include <linux/mii.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/usb.h>
|
||||
+#include <linux/of.h>
|
||||
#include <linux/crc32.h>
|
||||
#include <linux/if_vlan.h>
|
||||
#include <linux/uaccess.h>
|
||||
@@ -4336,6 +4337,22 @@ static void rtl_tally_reset(struct r8152
|
||||
ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
|
||||
}
|
||||
|
||||
+static int r8152_led_configuration(struct r8152 *tp)
|
||||
+{
|
||||
+ u32 led_data;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = of_property_read_u32(tp->udev->dev.of_node, "realtek,led-data",
|
||||
+ &led_data);
|
||||
+
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_LEDSEL, led_data);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static void r8152b_init(struct r8152 *tp)
|
||||
{
|
||||
u32 ocp_data;
|
||||
@@ -4377,6 +4394,8 @@ static void r8152b_init(struct r8152 *tp
|
||||
ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
|
||||
ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
|
||||
ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
|
||||
+
|
||||
+ r8152_led_configuration(tp);
|
||||
}
|
||||
|
||||
static void r8153_init(struct r8152 *tp)
|
||||
@@ -4511,6 +4530,8 @@ static void r8153_init(struct r8152 *tp)
|
||||
tp->coalesce = COALESCE_SLOW;
|
||||
break;
|
||||
}
|
||||
+
|
||||
+ r8152_led_configuration(tp);
|
||||
}
|
||||
|
||||
static void r8153b_init(struct r8152 *tp)
|
||||
@@ -4587,6 +4608,8 @@ static void r8153b_init(struct r8152 *tp
|
||||
rtl_tally_reset(tp);
|
||||
|
||||
tp->coalesce = 15000; /* 15 us */
|
||||
+
|
||||
+ r8152_led_configuration(tp);
|
||||
}
|
||||
|
||||
static int rtl8152_pre_reset(struct usb_interface *intf)
|
||||
@@ -0,0 +1,54 @@
|
||||
From 3ee05f4aa64fc86af3be5bc176ba5808de9260a7 Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Sun, 26 Jul 2020 15:30:33 +0200
|
||||
Subject: [PATCH] dt-bindings: net: add RTL8152 binding documentation
|
||||
|
||||
Add binding documentation for the Realtek RTL8152 / RTL8153 USB ethernet
|
||||
adapters.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
.../bindings/net/realtek,rtl8152.yaml | 36 +++++++++++++++++++
|
||||
1 file changed, 36 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/net/realtek,rtl8152.yaml
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/net/realtek,rtl8152.yaml
|
||||
@@ -0,0 +1,36 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0
|
||||
+%YAML 1.2
|
||||
+---
|
||||
+$id: http://devicetree.org/schemas/net/realtek,rtl8152.yaml#
|
||||
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
+
|
||||
+title: Realtek RTL8152/RTL8153 series USB ethernet
|
||||
+
|
||||
+maintainers:
|
||||
+ - David Bauer <mail@david-bauer.net>
|
||||
+
|
||||
+properties:
|
||||
+ compatible:
|
||||
+ oneOf:
|
||||
+ - items:
|
||||
+ - enum:
|
||||
+ - realtek,rtl8152
|
||||
+ - realtek,rtl8153
|
||||
+
|
||||
+ reg:
|
||||
+ description: The device number on the USB bus
|
||||
+
|
||||
+ realtek,led-data:
|
||||
+ description: Value to be written to the LED configuration register.
|
||||
+
|
||||
+required:
|
||||
+ - compatible
|
||||
+ - reg
|
||||
+
|
||||
+examples:
|
||||
+ - |
|
||||
+ usb-eth@2 {
|
||||
+ compatible = "realtek,rtl8153";
|
||||
+ reg = <2>;
|
||||
+ realtek,led-data = <0x87>;
|
||||
+ };
|
||||
\ No newline at end of file
|
||||
@@ -0,0 +1,54 @@
|
||||
From 8a469ee35606ba65448d54e5a2a23302f7e79e3c Mon Sep 17 00:00:00 2001
|
||||
From: Carlos de Paula <me@carlosedp.com>
|
||||
Date: Tue, 18 Feb 2020 17:10:37 -0500
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add txpbl node for RK3399/RK3328
|
||||
|
||||
Some rockchip SoCs like the RK3399 and RK3328 exhibit an issue
|
||||
where tx checksumming does not work with packets larger than 1498.
|
||||
|
||||
The default Programmable Buffer Length for TX in these GMAC's is
|
||||
not suitable for MTUs higher than 1498. The workaround is to disable
|
||||
TX offloading with 'ethtool -K eth0 tx off rx off' causing performance
|
||||
impacts as it disables hardware checksumming.
|
||||
|
||||
This patch sets snps,txpbl to 0x4 which is a safe number tested ok for
|
||||
the most popular MTU value of 1500.
|
||||
|
||||
For reference, see https://lkml.org/lkml/2019/4/1/1382.
|
||||
|
||||
Signed-off-by: Carlos de Paula <me@carlosedp.com>
|
||||
Link: https://lore.kernel.org/r/20200218221040.10955-1-me@carlosedp.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 ++
|
||||
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 +
|
||||
2 files changed, 3 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -857,6 +857,7 @@
|
||||
resets = <&cru SRST_GMAC2IO_A>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
||||
+ snps,txpbl = <0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -878,6 +879,7 @@
|
||||
reset-names = "stmmaceth", "mac-phy";
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <&phy>;
|
||||
+ snps,txpbl = <0x4>;
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -291,6 +291,7 @@
|
||||
resets = <&cru SRST_A_GMAC>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
||||
+ snps,txpbl = <0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
From bc6c96d850419e71dbc9b0094ccc9b668ba9be43 Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Mon, 28 Sep 2020 22:54:52 +0200
|
||||
Subject: [PATCH] rockchip: rk3328: add compatible to NanoPi R2S ethernet PHY
|
||||
|
||||
This adds the compatible property to the NanoPi R2S ethernet PHY node.
|
||||
Otherwise, the PHY might not be probed, as the PHY ID reads all 0xff
|
||||
when it is still in reset.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -134,6 +134,8 @@
|
||||
#size-cells = <0>;
|
||||
|
||||
rtl8211e: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-id001c.c915",
|
||||
+ "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
pinctrl-0 = <ð_phy_reset_pin>;
|
||||
pinctrl-names = "default";
|
||||
@@ -0,0 +1,27 @@
|
||||
From f2962ed3805c5b74948d00e4e6fbb33388261ba8 Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Sun, 4 Oct 2020 16:43:29 +0200
|
||||
Subject: [PATCH] rockchip: rk3328: fix NanoPi R2S GMAC clock name
|
||||
|
||||
This commit fixes the name for the GMAC clock to gmac_clkin, as this is
|
||||
the name of the clock provided by the rk3328-clk driver.
|
||||
|
||||
Without this commit, the GMAC will not work in TX direction.
|
||||
|
||||
Suggested-by: Tobias Waldvogel <tobias.waldvogel@gmail.com>
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -20,7 +20,7 @@
|
||||
gmac_clk: gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
- clock-output-names = "gmac_clk";
|
||||
+ clock-output-names = "gmac_clkin";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
@@ -0,0 +1,177 @@
|
||||
From db792e9adbf85ffc9d6b0b060ac3c8e3148c8992 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Fri, 19 Mar 2021 13:16:27 +0800
|
||||
Subject: [PATCH] rockchip: rk3399: Add support for FriendlyARM NanoPi R4S
|
||||
|
||||
This adds support for the NanoPi R4S from FriendlyArm.
|
||||
|
||||
Rockchip RK3399 SoC
|
||||
1GB DDR3 or 4GB LPDDR4 RAM
|
||||
Gigabit Ethernet (WAN)
|
||||
Gigabit Ethernet (PCIe) (LAN)
|
||||
USB 3.0 Port x 2
|
||||
MicroSD slot
|
||||
Reset button
|
||||
WAN - LAN - SYS LED
|
||||
|
||||
Co-developed-by: Jensen Huang <jensenhuang@friendlyarm.com>
|
||||
Signed-off-by: Jensen Huang <jensenhuang@friendlyarm.com>
|
||||
[minor adjustments]
|
||||
Co-developed-by: Marty Jones <mj8263788@gmail.com>
|
||||
Signed-off-by: Marty Jones <mj8263788@gmail.com>
|
||||
[further adjustments, fixed format issues]
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210319051627.814-2-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 133 +++++++++++++++++++++
|
||||
2 files changed, 134 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-le
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -0,0 +1,133 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * FriendlyElec NanoPC-T4 board device tree source
|
||||
+ *
|
||||
+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyarm.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2018 Collabora Ltd.
|
||||
+ *
|
||||
+ * Copyright (c) 2020 Jensen Huang <jensenhuang@friendlyarm.com>
|
||||
+ * Copyright (c) 2020 Marty Jones <mj8263788@gmail.com>
|
||||
+ * Copyright (c) 2021 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3399-nanopi4.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R4S";
|
||||
+ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
|
||||
+
|
||||
+ /delete-node/ display-subsystem;
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
|
||||
+
|
||||
+ /delete-node/ status;
|
||||
+
|
||||
+ lan_led: led-lan {
|
||||
+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "green:lan";
|
||||
+ };
|
||||
+
|
||||
+ sys_led: led-sys {
|
||||
+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "red:sys";
|
||||
+ default-state = "on";
|
||||
+ };
|
||||
+
|
||||
+ wan_led: led-wan {
|
||||
+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "green:wan";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-keys {
|
||||
+ pinctrl-0 = <&reset_button_pin>;
|
||||
+
|
||||
+ /delete-node/ power;
|
||||
+
|
||||
+ reset {
|
||||
+ debounce-interval = <50>;
|
||||
+ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
|
||||
+ label = "reset";
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_5v: vdd-5v {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vdd_5v";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&emmc_phy {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&i2c4 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&pcie0 {
|
||||
+ max-link-speed = <1>;
|
||||
+ num-lanes = <1>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_sys>;
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gpio-leds {
|
||||
+ /delete-node/ leds-gpio;
|
||||
+
|
||||
+ lan_led_pin: lan-led-pin {
|
||||
+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ sys_led_pin: sys-led-pin {
|
||||
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led_pin: wan-led-pin {
|
||||
+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rockchip-key {
|
||||
+ /delete-node/ power-key;
|
||||
+
|
||||
+ reset_button_pin: reset-button-pin {
|
||||
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&sdio0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_host {
|
||||
+ phy-supply = <&vdd_5v>;
|
||||
+};
|
||||
+
|
||||
+&u2phy1_host {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3_0 {
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&vcc3v3_sys {
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+};
|
||||
@@ -0,0 +1,31 @@
|
||||
From af20b3384e8723077cc6484160b0cf4e9be321de Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Mon, 7 Jun 2021 15:45:37 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S
|
||||
|
||||
NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which
|
||||
stores the MAC address.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -68,6 +68,15 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+&i2c2 {
|
||||
+ eeprom@51 {
|
||||
+ compatible = "microchip,24c02", "atmel,24c02";
|
||||
+ reg = <0x51>;
|
||||
+ pagesize = <16>;
|
||||
+ read-only; /* This holds our MAC */
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&i2c4 {
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -0,0 +1,31 @@
|
||||
From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Fri, 10 Jul 2020 21:38:20 +0200
|
||||
Subject: [PATCH] rockchip: use system LED for OpenWrt
|
||||
|
||||
Use the SYS LED on the casing for showing system status.
|
||||
|
||||
This patch is kept separate from the NanoPi R2S support patch, as i plan
|
||||
on submitting the device support upstream.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++-
|
||||
1 file changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -13,6 +13,13 @@
|
||||
model = "FriendlyElec NanoPi R2S";
|
||||
compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
|
||||
|
||||
+ aliases {
|
||||
+ led-boot = &sys_led;
|
||||
+ led-failsafe = &sys_led;
|
||||
+ led-running = &sys_led;
|
||||
+ led-upgrade = &sys_led;
|
||||
+ };
|
||||
+
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
@@ -0,0 +1,62 @@
|
||||
From: William Wu <william.wu@rock-chips.com>
|
||||
|
||||
RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
|
||||
core's general architecture. It can act as static xHCI host
|
||||
controller, static device controller, USB 3.0/2.0 OTG basing
|
||||
on ID of USB3.0 PHY.
|
||||
|
||||
Signed-off-by: William Wu <william.wu@rock-chips.com>
|
||||
Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
|
||||
|
||||
---
|
||||
|
||||
NOTE: This binding still has issues. From the original thread:
|
||||
|
||||
the rk3328 usb3-phy has an issue with detecting any plugin events
|
||||
after a previous device got removed - see the inno-usb3-phy driver
|
||||
in the vendor kernel.
|
||||
|
||||
The current state is good-enough for enabling the USB3 attached LAN
|
||||
port of the NanoPi R2S. However, it might explode depending on your
|
||||
use-case. You've been warned.
|
||||
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++
|
||||
1 file changed, 27 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -938,6 +938,33 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ usbdrd3: usb@ff600000 {
|
||||
+ compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
|
||||
+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
|
||||
+ <&cru ACLK_USB3OTG>;
|
||||
+ clock-names = "ref_clk", "suspend_clk",
|
||||
+ "bus_clk";
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+ ranges;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ usbdrd_dwc3: dwc3@ff600000 {
|
||||
+ compatible = "snps,dwc3";
|
||||
+ reg = <0x0 0xff600000 0x0 0x100000>;
|
||||
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ dr_mode = "otg";
|
||||
+ phy_type = "utmi_wide";
|
||||
+ snps,dis_enblslpm_quirk;
|
||||
+ snps,dis-u2-freeclk-exists-quirk;
|
||||
+ snps,dis_u2_susphy_quirk;
|
||||
+ snps,dis_u3_susphy_quirk;
|
||||
+ snps,dis-del-phy-power-chg-quirk;
|
||||
+ snps,dis-tx-ipgap-linecheck-quirk;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
gic: interrupt-controller@ff811000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
@@ -0,0 +1,60 @@
|
||||
From 0fc3b9b7619c4878f73a6a7989863f0d1a3fd392 Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Fri, 10 Jul 2020 21:12:16 +0200
|
||||
Subject: [PATCH] rockchip: enabled LAN port on NanoPi R2S
|
||||
|
||||
Enable the USB3 port on the FriendlyARM NanoPi R2S.
|
||||
This is required for the USB3 attached LAN port to work.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 27 +++++++++++++++++++
|
||||
1 file changed, 27 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -44,6 +44,18 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ vcc_rtl8153: vcc-rtl8153-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&rtl8153_en_drv>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-name = "vcc_rtl8153";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ enable-active-high;
|
||||
+ };
|
||||
+
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
|
||||
@@ -269,6 +281,12 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ usb {
|
||||
+ rtl8153_en_drv: rtl8153-en-drv {
|
||||
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
@@ -375,3 +393,12 @@
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
+
|
||||
+&usbdrd3 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd_dwc3 {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+};
|
||||
@@ -0,0 +1,28 @@
|
||||
From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Sun, 26 Jul 2020 13:32:59 +0200
|
||||
Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S
|
||||
|
||||
This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
|
||||
NanoPi R2S. Add the correct value for the RTL8153 LED configuration
|
||||
register to match the blink behavior of the other port on the device.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -401,4 +401,11 @@
|
||||
&usbdrd_dwc3 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
+
|
||||
+ usb-eth@2 {
|
||||
+ compatible = "realtek,rtl8153";
|
||||
+ reg = <2>;
|
||||
+
|
||||
+ realtek,led-data = <0x87>;
|
||||
+ };
|
||||
};
|
||||
@@ -0,0 +1,32 @@
|
||||
From e12f67fe83446432ef16704c22ec23bd1dbcd094 Mon Sep 17 00:00:00 2001
|
||||
From: Vicente Bergas <vicencb@gmail.com>
|
||||
Date: Tue, 1 Dec 2020 16:41:32 +0100
|
||||
Subject: arm64: dts: rockchip: use USB host by default on rk3399-rock-pi-4
|
||||
|
||||
Based on the board schematics at
|
||||
https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf
|
||||
on page 19 there is an USB Type-A receptacle being used as an USB-OTG port.
|
||||
|
||||
But the Type-A connector is not valid for OTG operation, for this reason
|
||||
there is a switch to select host or device role.
|
||||
This is non-compliant and error prone because switching is manual.
|
||||
So, use host mode as it corresponds for a Type-A receptacle.
|
||||
|
||||
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20201201154132.1286-4-vicencb@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
|
||||
@@ -684,7 +684,7 @@
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
status = "okay";
|
||||
- dr_mode = "otg";
|
||||
+ dr_mode = "host";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
Reference in New Issue
Block a user