63 lines
1.3 KiB
Diff
63 lines
1.3 KiB
Diff
From aafb63a926b790b64a5ed83377f07b90ec7ba7c0 Mon Sep 17 00:00:00 2001
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From: Claudiu Manoil <claudiu.manoil@nxp.com>
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Date: Thu, 20 Jun 2019 19:53:55 +0300
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Subject: [PATCH] arm64: dts: fsl: ls1028a: Enable switch PHYs on RDB
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Just link the switch PHY nodes to the central MDIO
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controller PCIe endpoint node on ls1028 (implemented
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as PF3) so that PHYs are configurable via MDIO.
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Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 39 +++++++++++++++++++++++
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1 file changed, 39 insertions(+)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
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@@ -208,6 +208,45 @@
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status = "disabled";
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};
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+&enetc_mdio_pf3 {
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+ qsgmii_phy1: ethernet-phy@4 {
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+ reg = <0x10>;
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+ };
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+
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+ qsgmii_phy2: ethernet-phy@5 {
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+ reg = <0x11>;
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+ };
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+
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+ qsgmii_phy3: ethernet-phy@6 {
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+ reg = <0x12>;
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+ };
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+
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+ qsgmii_phy4: ethernet-phy@7 {
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+ reg = <0x13>;
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+ };
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+};
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+
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+/* l2switch ports */
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+&switch_port0 {
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+ phy-handle = <&qsgmii_phy1>;
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+ phy-connection-type = "qsgmii";
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+};
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+
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+&switch_port1 {
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+ phy-handle = <&qsgmii_phy2>;
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+ phy-connection-type = "qsgmii";
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+};
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+
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+&switch_port2 {
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+ phy-handle = <&qsgmii_phy3>;
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+ phy-connection-type = "qsgmii";
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+};
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+
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+&switch_port3 {
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+ phy-handle = <&qsgmii_phy4>;
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+ phy-connection-type = "qsgmii";
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+};
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+
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&sai4 {
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status = "okay";
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};
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