Initial commit

package/boot/uboot-sunxi/Makefile

@@ -0,0 +1,444 @@
+#
+# Copyright (C) 2013-2016 OpenWrt.org
+# Copyright (C) 2017 Yousong Zhou
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_VERSION:=2024.01
+
+PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3
+
+PKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>
+
+UBOOT_USE_INTREE_DTC:=1
+
+include $(INCLUDE_DIR)/u-boot.mk
+include $(INCLUDE_DIR)/package.mk
+
+define U-Boot/Default
+  BUILD_TARGET:=sunxi
+  UBOOT_IMAGE:=u-boot-sunxi-with-spl.bin
+  UENV:=default
+  HIDDEN:=1
+endef
+
+define U-Boot/a64-olinuxino
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=Olimex A64-OLinuXino
+  BUILD_DEVICES:=olimex_a64-olinuxino
+  DEPENDS:=+PACKAGE_u-boot-olimex_a64-olinuxino:trusted-firmware-a-sunxi-a64
+  UENV:=a64
+  ATF:=a64
+endef
+
+define U-Boot/a64-olinuxino-emmc
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=Olimex A64-OLinuXino eMMC
+  BUILD_DEVICES:=olimex_a64-olinuxino-emmc
+  DEPENDS:=+PACKAGE_u-boot-olimex_a64-olinuxino-emmc:trusted-firmware-a-sunxi-a64
+  UENV:=a64
+  ATF:=a64
+endef
+
+define U-Boot/A10-OLinuXino-Lime
+  BUILD_SUBTARGET:=cortexa8
+  NAME:=A10 OLinuXino LIME
+  BUILD_DEVICES:=olimex_a10-olinuxino-lime
+endef
+
+define U-Boot/A13-OLinuXino
+  BUILD_SUBTARGET:=cortexa8
+  NAME:=A13 OlinuXino
+  BUILD_DEVICES:=olimex_a13-olinuxino
+endef
+
+define U-Boot/A20-OLinuXino-Lime
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=A20 OLinuXino LIME
+  BUILD_DEVICES:=olimex_a20-olinuxino-lime
+endef
+
+define U-Boot/A20-OLinuXino-Lime2
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=A20 OLinuXino LIME2
+  BUILD_DEVICES:=olimex_a20-olinuxino-lime2
+endef
+
+define U-Boot/A20-OLinuXino-Lime2-eMMC
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=A20 OLinuXino LIME2 eMMC
+  BUILD_DEVICES:=olimex_a20-olinuxino-lime2-emmc
+endef
+
+define U-Boot/A20-OLinuXino_MICRO
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=A20 OLinuXino MICRO
+  BUILD_DEVICES:=olimex_a20-olinuxino-micro
+endef
+
+define U-Boot/Bananapi
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Bananapi
+  BUILD_DEVICES:=lemaker_bananapi
+endef
+
+define U-Boot/Bananapro
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Bananapro
+  BUILD_DEVICES:=lemaker_bananapro
+endef
+
+define U-Boot/Cubieboard
+  BUILD_SUBTARGET:=cortexa8
+  NAME:=Cubieboard
+  BUILD_DEVICES:=cubietech_a10-cubieboard
+endef
+
+define U-Boot/Cubieboard2
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Cubieboard2
+  BUILD_DEVICES:=cubietech_cubieboard2
+endef
+
+define U-Boot/Cubietruck
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Cubietruck
+  BUILD_DEVICES:=cubietech_cubietruck
+endef
+
+define U-Boot/Hummingbird_A31
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Hummingbird A31 board
+endef
+
+define U-Boot/Marsboard_A10
+  BUILD_SUBTARGET:=cortexa8
+  NAME:=HAOYU Marsboard A10
+  BUILD_DEVICES:=haoyu_a10-marsboard
+endef
+
+define U-Boot/Mele_M9
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Mele M9 (A31)
+  BUILD_DEVICES:=mele_m9
+endef
+
+define U-Boot/OLIMEX_A13_SOM
+  BUILD_SUBTARGET:=cortexa8
+  NAME:=Olimex A13 SOM
+  BUILD_DEVICES:=olimex_a13-olimex-som
+endef
+
+define U-Boot/Linksprite_pcDuino
+  BUILD_SUBTARGET:=cortexa8
+  NAME:=Linksprite pcDuino
+  BUILD_DEVICES:=linksprite_a10-pcduino
+endef
+
+define U-Boot/LicheePi_Zero
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Lichee Pi Zero V3s
+  BUILD_DEVICES:=licheepi_licheepi-zero-dock
+endef
+
+define U-Boot/Linksprite_pcDuino3
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Linksprite pcDuino3
+  BUILD_DEVICES:=linksprite_pcduino3
+endef
+
+define U-Boot/Linksprite_pcDuino3_Nano
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Linksprite pcDuino3 Nano
+  BUILD_DEVICES:=linksprite_pcduino3-nano
+endef
+
+define U-Boot/Lamobo_R1
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Lamobo R1
+  BUILD_DEVICES:=lamobo_lamobo-r1
+endef
+
+define U-Boot/nanopi_m1_plus
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=NanoPi M1 Plus (H3)
+  BUILD_DEVICES:=friendlyarm_nanopi-m1-plus
+endef
+
+define U-Boot/zeropi
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=ZeroPi (H3)
+  BUILD_DEVICES:=friendlyarm_zeropi
+endef
+
+define U-Boot/nanopi_neo_air
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=U-Boot for NanoPi NEO Air (H3)
+  BUILD_DEVICES:=friendlyarm_nanopi-neo-air
+endef
+
+define U-Boot/nanopi_neo
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=U-Boot for NanoPi NEO (H3)
+  BUILD_DEVICES:=friendlyarm_nanopi-neo
+endef
+
+define U-Boot/nanopi_r1
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=U-Boot for NanoPi R1 (H3)
+  BUILD_DEVICES:=friendlyarm_nanopi-r1
+endef
+
+define U-Boot/orangepi_r1
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Orange Pi R1 (H2+)
+  BUILD_DEVICES:=xunlong_orangepi-r1
+endef
+
+define U-Boot/orangepi_zero
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Orange Pi Zero (H2+)
+  BUILD_DEVICES:=xunlong_orangepi-zero
+endef
+
+define U-Boot/orangepi_one
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Orange Pi One (H3)
+  BUILD_DEVICES:=xunlong_orangepi-one
+endef
+
+define U-Boot/orangepi_one_plus
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=Orange Pi One Plus (H6)
+  DEPENDS:=+PACKAGE_u-boot-orangepi_one_plus:trusted-firmware-a-sunxi-h6
+  BUILD_DEVICES:=xunlong_orangepi-one-plus
+  UENV:=h6
+  ATF:=h6
+endef
+
+define U-Boot/orangepi_pc
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Orange Pi PC (H3)
+  BUILD_DEVICES:=xunlong_orangepi-pc
+endef
+
+define U-Boot/orangepi_pc_plus
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Orange Pi PC Plus (H3)
+  BUILD_DEVICES:=xunlong_orangepi-pc-plus
+endef
+
+define U-Boot/orangepi_plus
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Orange Pi Plus (H3)
+  BUILD_DEVICES:=xunlong_orangepi-plus
+endef
+
+define U-Boot/orangepi_2
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Orange Pi 2 (H3)
+  BUILD_DEVICES:=xunlong_orangepi-2
+endef
+
+define U-Boot/pangolin
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Theobroma A31-yQ7 devboard
+  UENV:=pangolin
+endef
+
+define U-Boot/libretech_all_h3_cc_h5
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=Libre Computer ALL-H3-CC H5
+  BUILD_DEVICES:=libretech_all-h3-cc-h5
+  DEPENDS:=+PACKAGE_u-boot-libretech_all_h3_cc_h5:trusted-firmware-a-sunxi-a64
+  UENV:=a64
+  ATF:=a64
+endef
+
+define U-Boot/nanopi_neo_plus2
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=NanoPi NEO Plus2 (H5)
+  BUILD_DEVICES:=friendlyarm_nanopi-neo-plus2
+  DEPENDS:=+PACKAGE_u-boot-nanopi_neo_plus2:trusted-firmware-a-sunxi-a64
+  UENV:=a64
+  ATF:=a64
+endef
+
+define U-Boot/nanopi_neo2
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=NanoPi NEO2 (H5)
+  BUILD_DEVICES:=friendlyarm_nanopi-neo2
+  DEPENDS:=+PACKAGE_u-boot-nanopi_neo2:trusted-firmware-a-sunxi-a64
+  UENV:=a64
+  ATF:=a64
+endef
+
+define U-Boot/nanopi_r1s_h5
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=NanoPi R1S (H5)
+  BUILD_DEVICES:=friendlyarm_nanopi-r1s-h5
+  DEPENDS:=+PACKAGE_u-boot-nanopi_r1s_h5:trusted-firmware-a-sunxi-a64
+  UENV:=a64
+  ATF:=a64
+endef
+
+define U-Boot/pine64_plus
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=Pine64 Plus A64
+  BUILD_DEVICES:=pine64_pine64-plus
+  DEPENDS:=+PACKAGE_u-boot-pine64_plus:trusted-firmware-a-sunxi-a64
+  UENV:=a64
+  ATF:=a64
+endef
+
+define U-Boot/bananapi_m2_plus_h3
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Bananapi M2 Plus H3
+  BUILD_DEVICES:=sinovoip_bananapi-m2-plus
+endef
+
+define U-Boot/Sinovoip_BPI_M3
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Bananapi M3
+  BUILD_DEVICES:=sinovoip_bananapi-m3
+endef
+
+define U-Boot/sopine_baseboard
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=Sopine Baseboard
+  BUILD_DEVICES:=pine64_sopine-baseboard
+  DEPENDS:=+PACKAGE_u-boot-sopine_baseboard:trusted-firmware-a-sunxi-a64
+  UENV:=a64
+  ATF:=a64
+endef
+
+
+define U-Boot/orangepi_zero_plus
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=Xunlong Orange Pi Zero Plus
+  BUILD_DEVICES:=xunlong_orangepi-zero-plus
+  DEPENDS:=+PACKAGE_u-boot-orangepi_zero_plus:trusted-firmware-a-sunxi-a64
+  UENV:=a64
+  ATF:=a64
+endef
+
+define U-Boot/orangepi_pc2
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=Xunlong Orange Pi PC2
+  BUILD_DEVICES:=xunlong_orangepi-pc2
+  DEPENDS:=+PACKAGE_u-boot-orangepi_pc2:trusted-firmware-a-sunxi-a64
+  UENV:=a64
+  ATF:=a64
+endef
+
+define U-Boot/orangepi_zero2
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=Xunlong Orange Pi Zero2
+  BUILD_DEVICES:=xunlong_orangepi-zero2
+  DEPENDS:=+PACKAGE_u-boot-orangepi_zero2:trusted-firmware-a-sunxi-h616
+  UENV:=h616
+  ATF:=h616
+endef
+
+define U-Boot/orangepi_zero3
+  BUILD_SUBTARGET:=cortexa53
+  NAME:=Xunlong Orange Pi Zero3
+  BUILD_DEVICES:=xunlong_orangepi-zero3
+  DEPENDS:=+PACKAGE_u-boot-orangepi_zero3:trusted-firmware-a-sunxi-h616
+  UENV:=h616
+  ATF:=h616
+endef
+
+define U-Boot/Bananapi_M2_Ultra
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Bananapi M2 Ultra
+  BUILD_DEVICES:=sinovoip_bananapi-m2-ultra
+endef
+
+define U-Boot/bananapi_m2_berry
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Bananapi M2 Berry
+  BUILD_DEVICES:=sinovoip_bananapi-m2-berry
+endef
+
+define U-Boot/bananapi_p2_zero
+  BUILD_SUBTARGET:=cortexa7
+  NAME:=Bananapi P2 Zero
+  BUILD_DEVICES:=sinovoip_bananapi-p2-zero
+endef
+
+
+UBOOT_TARGETS := \
+	a64-olinuxino \
+	a64-olinuxino-emmc \
+	A10-OLinuXino-Lime \
+	A13-OLinuXino \
+	A20-OLinuXino-Lime \
+	A20-OLinuXino-Lime2 \
+	A20-OLinuXino-Lime2-eMMC \
+	A20-OLinuXino_MICRO \
+	bananapi_m2_plus_h3 \
+	Bananapi \
+	bananapi_m2_berry \
+	bananapi_p2_zero \
+	Bananapi_M2_Ultra \
+	Bananapro \
+	Cubieboard \
+	Cubieboard2 \
+	Cubietruck \
+	Hummingbird_A31 \
+	Marsboard_A10 \
+	Mele_M9 \
+	OLIMEX_A13_SOM \
+	LicheePi_Zero \
+	Linksprite_pcDuino \
+	Linksprite_pcDuino3 \
+	Linksprite_pcDuino3_Nano \
+	Lamobo_R1 \
+	nanopi_m1_plus \
+	zeropi \
+	nanopi_neo \
+	nanopi_neo_air \
+	nanopi_neo_plus2 \
+	nanopi_neo2 \
+	nanopi_r1 \
+	nanopi_r1s_h5 \
+	orangepi_zero \
+	orangepi_r1 \
+	orangepi_one \
+	orangepi_one_plus \
+	orangepi_pc \
+	orangepi_pc_plus \
+	orangepi_plus \
+	orangepi_2 \
+	orangepi_pc2 \
+	orangepi_zero2 \
+	orangepi_zero3 \
+	pangolin \
+	pine64_plus \
+	Sinovoip_BPI_M3 \
+	sopine_baseboard \
+	orangepi_zero_plus \
+	libretech_all_h3_cc_h5
+
+UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
+
+UBOOT_MAKE_FLAGS += \
+	BL31=$(STAGING_DIR_IMAGE)/bl31_sunxi-$(ATF).bin SCP=/dev/null
+
+define Build/InstallDev
+	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
+	$(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-u-boot-with-spl.bin
+	mkimage -C none -A arm -T script -d uEnv-$(UENV).txt \
+		$(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-boot.scr
+endef
+
+define Package/u-boot/install/default
+endef
+
+$(eval $(call BuildPackage/U-Boot))

package/boot/uboot-sunxi/patches/002-add-olimex-a13-som.patch

@@ -0,0 +1,20 @@
+--- /dev/null
++++ b/configs/OLIMEX_A13_SOM_defconfig
+@@ -0,0 +1,17 @@
++CONFIG_SPL=y
++CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
++CONFIG_ARM=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_MACH_SUN5I=y
++CONFIG_DRAM_CLK=408
++CONFIG_DRAM_ZQ=123
++CONFIG_DRAM_EMR1=0
++# CONFIG_CMD_IMLS is not set
++# CONFIG_CMD_FLASH is not set
++# CONFIG_CMD_FPGA is not set
++CONFIG_DM_SERIAL=y
++CONFIG_USB=y
++CONFIG_DM_USB=y
++CONFIG_SYS_NS16550=y
++CONFIG_SUNXI_NO_PMIC=y
++CONFIG_USB_EHCI_HCD=y

package/boot/uboot-sunxi/patches/062-A20-improve-gmac-upload.patch

@@ -0,0 +1,12 @@
+  GNU nano 2.7.4                                                    File: 062-A20-improve-gmac-upload.patch
+
+--- a/configs/A20-OLinuXino-Lime2_defconfig
++++ b/configs/A20-OLinuXino-Lime2_defconfig
+@@ -25,6 +25,7 @@ CONFIG_ETH_DESIGNWARE=y
+ CONFIG_RGMII=y
+ CONFIG_MII=y
+ CONFIG_SUN7I_GMAC=y
++CONFIG_GMAC_TX_DELAY=1
+ CONFIG_AXP_ALDO3_VOLT=2800
+ CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y
+ CONFIG_AXP_ALDO3_INRUSH_QUIRK=y

package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch

@@ -0,0 +1,32 @@
+From a58eb20fb80f478038243e9e0f30f6984725e265 Mon Sep 17 00:00:00 2001
+From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+Date: Tue, 6 Jan 2015 15:47:18 +0100
+Subject: sun6i: Sync PLL1 multipliers/dividers with Boot1
+
+This change syncs up the multipliers and dividers used to initialize
+PLL1 (i.e. the fast clock driving the ARM cores) with the values used
+in Allwinner's Boot1 on sun6i.
+
+More specifically, the following settings are now used:
+ * up to 768MHz:  mul=2, div=2 (was: mul=1, div=1)
+ * up to 1152MHz: mul=3, div=2 (unchanged)
+ * above 1152MHz: mul=4, div=2 (was: mul=2, div=1)
+
+--- a/arch/arm/mach-sunxi/clock_sun6i.c
++++ b/arch/arm/mach-sunxi/clock_sun6i.c
+@@ -131,11 +131,12 @@ void clock_set_pll1(unsigned int clk)
+ 	struct sunxi_ccm_reg * const ccm =
+ 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ 	const int p = 0;
+-	int k = 1;
+-	int m = 1;
++	int k = 2;
++	int m = 2;
+ 
+ 	if (clk > 1152000000) {
+-		k = 2;
++		k = 4;
++		m = 2;
+ 	} else if (clk > 768000000) {
+ 		k = 4;
+ 		m = 2;

package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch

@@ -0,0 +1,69 @@
+From b2b385df5095fff80b4655142f58a2a6801e6c80 Mon Sep 17 00:00:00 2001
+From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+Date: Tue, 6 Jan 2015 21:26:44 +0100
+Subject: sun6i: Fix and document PLL LDO voltage selection
+
+The PRCM_PLL_CTRL_LDO_OUT_L and PRCM_PLL_CTRL_LDO_OUT_H macros had
+their meaning reversed. This is fixed by this change-set. With this
+changed, the PRCM_PLL_CTRL_LDO_OUT_L(1370) now becomes self-evident
+as setting the voltage to 1.37v (which it had done all along, even
+though stating a different target voltage).
+
+After changing the PLL LDO setting, it will take a little while for
+the voltage output to settle. A sdelay()-based loop waits the same
+order of magnitude as Boot1.
+
+Furthermore, a bit of documentation is added to clarify that the
+required setting for the PLL LDO is 1.37v as per the A31 manual.
+
+--- a/arch/arm/mach-sunxi/clock_sun6i.c
++++ b/arch/arm/mach-sunxi/clock_sun6i.c
+@@ -28,13 +28,26 @@ void clock_init_safe(void)
+ 	struct sunxi_prcm_reg * const prcm =
+ 		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+ 
+-	/* Set PLL ldo voltage without this PLL6 does not work properly */
++	/* Set PLL ldo voltage without this PLL6 does not work properly.
++	 *
++	 * As the A31 manual states, that "before enable PLL, PLLVDD
++	 * LDO should be set to 1.37v", we need to configure this to 2.5v
++	 * in the "PLL Input Power Select" (0 << 15) and (7 << 16).
++	 */
+ 	clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
+ 			PRCM_PLL_CTRL_LDO_KEY);
+ 	clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
+ 		PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
+-		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
++		PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370));
+ 	clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
++
++	/* Give the PLL LDO voltage setting some time to take hold.
++	 * Notes:
++	 *   1) We need to use sdelay() as the timers aren't set up yet.
++	 *   2) The 100k iterations come from Boot1, which spin's for 100k
++	 *      iterations through a loop.
++	 */
++	sdelay(100000);
+ #endif
+ 
+ #if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
+--- a/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h
++++ b/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h
+@@ -110,13 +110,13 @@
+ #define PRCM_PLL_CTRL_LDO_OUT_MASK \
+ 	__PRCM_PLL_CTRL_LDO_OUT(0x7)
+ /* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
+-#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
+-	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
+ #define PRCM_PLL_CTRL_LDO_OUT_H(n) \
++	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
++#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
+ 	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
+-#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
+-	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
+ #define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
++	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
++#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
+ 	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
+ #define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
+ #define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)

package/boot/uboot-sunxi/patches/200-mkimage-check-environment-for-dtc-binary-location.patch

@@ -0,0 +1,35 @@
+From 637800493945ffed2f454756300437a4ec86e3b1 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Wed, 19 Jul 2017 22:23:15 +0200
+Subject: mkimage: check environment for dtc binary location
+
+Currently mkimage assumes the dtc binary is in the path and fails
+otherwise. This patch makes it check the DTC environment variable first
+for the dtc binary and then fall back to the default path. This makes
+it possible to call the u-boot build with make DTC=... and build a fit
+image with the dtc binary not being the the default path.
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+Cc: Simon Glass <sjg@chromium.org>
+---
+ tools/fit_image.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/tools/fit_image.c
++++ b/tools/fit_image.c
+@@ -774,9 +774,14 @@ static int fit_handle_file(struct image_
+ 		}
+ 		*cmd = '\0';
+ 	} else if (params->datafile) {
++		const char* dtc = getenv("DTC");
++
++		if (!dtc)
++			dtc = MKIMAGE_DTC;
++
+ 		/* dtc -I dts -O dtb -p 500 -o tmpfile datafile */
+ 		snprintf(cmd, sizeof(cmd), "%s %s -o \"%s\" \"%s\"",
+-			 MKIMAGE_DTC, params->dtc, tmpfile, params->datafile);
++			 dtc, params->dtc, tmpfile, params->datafile);
+ 		debug("Trying to execute \"%s\"\n", cmd);
+ 	} else {
+ 		snprintf(cmd, sizeof(cmd), "cp \"%s\" \"%s\"",

package/boot/uboot-sunxi/patches/252-sunxi-h3-add-support-for-nanopi-r1.patch

@@ -0,0 +1,38 @@
+From 0e8043aff1aae95d1f7b7422b91b57d9569860d3 Mon Sep 17 00:00:00 2001
+From: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
+Date: Mon, 12 Oct 2020 18:39:53 +0000
+Subject: [PATCH] sunxi: add support for FriendlyARM NanoPi R1
+
+Signed-off-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
+---
+ arch/arm/dts/Makefile               |   1 +
+ arch/arm/dts/sun8i-h3-nanopi-r1.dts | 146 ++++++++++++++++++++++++++++
+ configs/nanopi_r1_defconfig         |  22 +++++
+ 3 files changed, 169 insertions(+)
+ create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts
+ create mode 100644 configs/nanopi_r1_defconfig
+
+--- /dev/null
++++ b/configs/nanopi_r1_defconfig
+@@ -0,0 +1,21 @@
++CONFIG_ARM=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_SPL=y
++CONFIG_MACH_SUN8I_H3=y
++CONFIG_DRAM_CLK=408
++CONFIG_DRAM_ZQ=3881979
++CONFIG_DRAM_ODT_EN=y
++CONFIG_MACPWR="PD6"
++# CONFIG_VIDEO_DE2 is not set
++CONFIG_NR_DRAM_BANKS=1
++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
++CONFIG_CONSOLE_MUX=y
++# CONFIG_CMD_FLASH is not set
++# CONFIG_SPL_DOS_PARTITION is not set
++# CONFIG_SPL_EFI_PARTITION is not set
++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-r1"
++CONFIG_SUN8I_EMAC=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
++CONFIG_MMC_SUNXI_SLOT_EXTRA=2

package/boot/uboot-sunxi/patches/254-sunxi-h2-add-bpi-p2-zero.patch

@@ -0,0 +1,307 @@
+--- /dev/null
++++ b/arch/arm/dts/sun8i-h2-plus-bananapi-p2-zero.dts
+@@ -0,0 +1,291 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2023 Zoltan HERPAI <wigyori@uid0.hu>
++ *
++ * Based on sun8i-h2-plus-bananapi-m2-zero.dts, which is:
++ *   Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
++ */
++
++/dts-v1/;
++#include "sun8i-h3.dtsi"
++#include "sunxi-common-regulators.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
++/ {
++	model = "Banana Pi BPI-P2-Zero";
++	compatible = "sinovoip,bpi-p2-zero", "allwinner,sun8i-h2-plus";
++
++	aliases {
++		serial0 = &uart0;
++		serial1 = &uart1;
++		ethernet0 = &emac;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "c";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		pwr_led {
++			label = "bananapi-p2-zero:red:pwr";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */
++			default-state = "on";
++		};
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++
++		switch-4 {
++			label = "power";
++			linux,code = <KEY_POWER>;
++			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
++			wakeup-source;
++		};
++	};
++
++	reg_vdd_cpux: vdd-cpux-regulator {
++		compatible = "regulator-gpio";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-ramp-delay = <50>; /* 4ms */
++
++		gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
++		enable-active-high;
++		gpios-states = <0x1>;
++		states = <1100000 0>, <1300000 1>;
++	};
++
++	reg_vcc_dram: vcc-dram {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-dram";
++		regulator-min-microvolt = <1500000>;
++		regulator-max-microvolt = <1500000>;
++		regulator-always-on;
++		regulator-boot-on;
++		enable-active-high;
++		gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
++		vin-supply = <&reg_vcc5v0>;
++	};
++
++	reg_vcc1v2: vcc1v2 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc1v2";
++		regulator-min-microvolt = <1200000>;
++		regulator-max-microvolt = <1200000>;
++		regulator-always-on;
++		regulator-boot-on;
++		enable-active-high;
++		gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++		vin-supply = <&reg_vcc5v0>;
++	};
++
++	poweroff {
++		compatible = "regulator-poweroff";
++		cpu-supply = <&reg_vcc1v2>;
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
++		clocks = <&rtc CLK_OSC32K_FANOUT>;
++		clock-names = "ext_clock";
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpux>;
++};
++
++&de {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&emac {
++	phy-handle = <&int_mii_phy>;
++	phy-mode = "mii";
++	allwinner,leds-active-low;
++	status = "okay";
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <4>;
++	/*
++	 * On the production batch of this board the card detect GPIO is
++	 * high active (card inserted), although on the early samples it's
++	 * low active.
++	 */
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc3v3>;
++	vqmmc-supply = <&reg_vcc3v3>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++
++	brcmf: wifi@1 {
++		reg = <1>;
++		compatible = "brcm,bcm4329-fmac";
++		interrupt-parent = <&pio>;
++		interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
++		interrupt-names = "host-wake";
++	};
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_8bit_pins>;
++	vmmc-supply = <&reg_vcc3v3>;
++	vqmmc-supply = <&reg_vcc3v3>;
++	bus-width = <8>;
++	non-removable;
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pa_pins>;
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++	uart-has-rtscts;
++	status = "okay";
++
++	bluetooth {
++		compatible = "brcm,bcm43438-bt";
++		max-speed = <1500000>;
++		clocks = <&rtc CLK_OSC32K_FANOUT>;
++		clock-names = "lpo";
++		vbat-supply = <&reg_vcc3v3>;
++		vddio-supply = <&reg_vcc3v3>;
++		device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
++		host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
++		shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
++	};
++
++};
++
++&pio {
++	gpio-line-names =
++		/* PA */
++		"CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15",
++			"CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29",
++		"CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05",
++			"CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16",
++		"CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27",
++			"CON2-P40", "CON2-P38", "", "",
++		"", "", "", "", "", "", "", "",
++
++		/* PB */
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++
++		/* PC */
++		"CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24",
++			"CON2-P18", "", "", "CON2-P26",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++
++		/* PD */
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "CSI-PWR-EN", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++
++		/* PE */
++		"CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07",
++			"CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20",
++		"CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12",
++			"CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++
++		/* PF */
++		"SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
++			"SDC0-D2", "SDC0-DET", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++
++		/* PG */
++		"WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1",
++			"WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX",
++		"BT-UART-RTS", "BT-UART-CTS", "WL-WAKE-AP", "BT-WAKE-AP",
++			"BT-RST-N", "AP-WAKE-BT", "", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "";
++};
++
++&r_pio {
++	gpio-line-names =
++		/* PL */
++		"", "CPUX-SET", "CON2-P32", "POWER-KEY", "CON2-P36",
++			"VCC-IO-EN", "USB0-ID", "WL-PWR-EN",
++		"PWR-STB", "PWR-DRAM", "PWR-LED", "IR-RX", "", "", "", "",
++		"", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "";
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++	/*
++	 * There're two micro-USB connectors, one is power-only and another is
++	 * OTG. The Vbus of these two connectors are connected together, so
++	 * the external USB device will be powered just by the power input
++	 * from the power-only USB port.
++	 */
++	status = "okay";
++};
+--- /dev/null
++++ b/configs/bananapi_p2_zero_defconfig
+@@ -0,0 +1,10 @@
++CONFIG_ARM=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-bananapi-p2-zero"
++CONFIG_SPL=y
++CONFIG_MACH_SUN8I_H3=y
++CONFIG_DRAM_CLK=408
++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
++CONFIG_MMC_SUNXI_SLOT_EXTRA=2
++CONFIG_SUN8I_EMAC=y
++CONFIG_USB_EHCI_HCD=y

package/boot/uboot-sunxi/uEnv-a64.txt

@@ -0,0 +1,7 @@
+setenv mmc_rootpart 2
+part uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid
+setenv loadkernel fatload mmc \$mmc_bootdev \$kernel_addr_r uImage
+setenv loaddtb fatload mmc \$mmc_bootdev \$fdt_addr_r dtb
+setenv bootargs console=ttyS0,115200 earlyprintk root=PARTUUID=${uuid} rootwait earlycon=uart,mmio32,0x01c28000
+setenv uenvcmd run loadkernel \&\& run loaddtb \&\& booti \$kernel_addr_r - \$fdt_addr_r
+run uenvcmd

package/boot/uboot-sunxi/uEnv-default.txt

@@ -0,0 +1,8 @@
+setenv fdt_high ffffffff
+setenv mmc_rootpart 2
+part uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid
+setenv loadkernel fatload mmc \$mmc_bootdev \$kernel_addr_r uImage
+setenv loaddtb fatload mmc \$mmc_bootdev \$fdt_addr_r dtb
+setenv bootargs console=ttyS0,115200 earlyprintk root=PARTUUID=${uuid} rootwait
+setenv uenvcmd run loadkernel \&\& run loaddtb \&\& bootm \$kernel_addr_r - \$fdt_addr_r
+run uenvcmd

package/boot/uboot-sunxi/uEnv-h6.txt

@@ -0,0 +1,7 @@
+setenv mmc_rootpart 2
+part uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid
+setenv loadkernel fatload mmc \$mmc_bootdev \$kernel_addr_r uImage
+setenv loaddtb fatload mmc \$mmc_bootdev \$fdt_addr_r dtb
+setenv bootargs console=ttyS0,115200 earlyprintk root=PARTUUID=${uuid} rootwait
+setenv uenvcmd run loadkernel \&\& run loaddtb \&\& booti \$kernel_addr_r - \$fdt_addr_r
+run uenvcmd

package/boot/uboot-sunxi/uEnv-h616.txt

@@ -0,0 +1,7 @@
+setenv mmc_rootpart 2
+part uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid
+setenv loadkernel fatload mmc \$mmc_bootdev \$kernel_addr_r uImage
+setenv loaddtb fatload mmc \$mmc_bootdev \$fdt_addr_r dtb
+setenv bootargs console=ttyS0,115200 earlyprintk root=PARTUUID=${uuid} rootwait
+setenv uenvcmd run loadkernel \&\& run loaddtb \&\& booti \$kernel_addr_r - \$fdt_addr_r
+run uenvcmd

package/boot/uboot-sunxi/uEnv-pangolin.txt

@@ -0,0 +1,6 @@
+setenv fdt_high ffffffff
+setenv loadkernel fatload mmc 0 \$kernel_addr_r uImage
+setenv loaddtb fatload mmc 0 \$fdt_addr_r dtb
+setenv bootargs console=ttyS2,115200 earlyprintk root=/dev/mmcblk0p2 rootwait
+setenv uenvcmd run loadkernel \&\& run loaddtb \&\& bootm \$kernel_addr_r - \$fdt_addr_r
+run uenvcmd