Initial commit

target/linux/ath79/dts/qca9556_avm_fritzdvbc.dts

@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/leds/common.h>
+
+#include "qca9556_avm_fritz-repeater.dtsi"
+
+/ {
+	compatible = "avm,fritzdvbc", "qca,qca9556";
+	model = "AVM FRITZ!WLAN Repeater DVB-C";
+
+	aliases {
+		led-boot = &led_power;
+		led-failsafe = &led_power;
+		led-running = &led_power;
+		led-upgrade = &led_power;
+	};
+
+	led_spi {
+		compatible = "spi-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sck-gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+		mosi-gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+		num-chipselects = <0>;
+
+		spi_gpio: led_gpio@0 {
+			compatible = "fairchild,74hc595";
+			reg = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			registers-number = <2>;
+			spi-max-frequency = <10000000>;
+
+			gpio_latch_bit {
+				gpio-hog;
+				gpios = <16 GPIO_ACTIVE_HIGH>;
+				output-high;
+				line-name = "gpio-latch-bit";
+			};
+		};
+	};
+
+	/*
+	 * GPIO pins 100 or greater in the vendor GPL dump are redirected
+	 * to the shift register.
+	 * So OEM source pin 100 becomes 0 on the SR and so forth.
+	 */
+	leds {
+		compatible = "gpio-leds";
+
+		led_power: power {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&spi_gpio 6 GPIO_ACTIVE_LOW>;
+		};
+
+		wlan {
+			function = LED_FUNCTION_WLAN;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&spi_gpio 7 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy1tpt";
+		};
+
+		tv {
+			label = "green:tv";
+			gpios = <&spi_gpio 5 GPIO_ACTIVE_LOW>;
+		};
+
+		rssihigh {
+			label = "green:rssihigh";
+			gpios = <&spi_gpio 1 GPIO_ACTIVE_LOW>;
+		};
+
+		rssimediumhigh {
+			label = "green:rssimediumhigh";
+			gpios = <&spi_gpio 2 GPIO_ACTIVE_LOW>;
+		};
+
+		rssimedium {
+			label = "green:rssimedium";
+			gpios = <&spi_gpio 3 GPIO_ACTIVE_LOW>;
+		};
+
+		rssimediumlow {
+			label = "green:rssimediumlow";
+			gpios = <&spi_gpio 4 GPIO_ACTIVE_LOW>;
+		};
+
+		rssilow {
+			label = "green:rssilow";
+			gpios = <&spi_gpio 0 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&pcie0 {
+	status = "okay";
+
+	wifi@0,0 {
+		compatible = "qcom,ath10k";
+		reg = <0x0000 0 0 0 0>;
+		nvmem-cells = <&cal_urlader_198a>;
+		nvmem-cell-names = "calibration";
+	};
+};
+
+&gpio {
+	reset-pcie-ep {
+		gpio-hog;
+		gpios = <109 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "PCIE EP reset";
+	};
+
+	reset-pcie-bus {
+		gpio-hog;
+		gpios = <110 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "PCIE Bus reset";
+	};
+};