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domenico
@@ -0,0 +1,213 @@
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From a522ee0199d5d3ea114ca2e211f6ac398d3e8e0b Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Sat, 23 Jun 2018 15:07:37 +0200
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Subject: [PATCH 20/33] MIPS: pci-ar724x: convert to OF
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With the ath79 target getting converted to pure OF, we can drop all the
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platform data code and add the missing OF bits to the driver. We also add
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a irq domain for the PCI/e controllers cascade, thus making it usable from
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dts files.
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/mips/pci/pci-ar724x.c | 88 ++++++++++++++++++++++------------------------
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1 file changed, 42 insertions(+), 46 deletions(-)
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--- a/arch/mips/pci/pci-ar724x.c
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+++ b/arch/mips/pci/pci-ar724x.c
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@@ -11,8 +11,11 @@
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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+#include <linux/irqchip/chained_irq.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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+#include <linux/of_irq.h>
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+#include <linux/of_pci.h>
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#define AR724X_PCI_REG_APP 0x00
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#define AR724X_PCI_REG_RESET 0x18
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@@ -42,17 +45,20 @@ struct ar724x_pci_controller {
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void __iomem *crp_base;
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int irq;
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- int irq_base;
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bool link_up;
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bool bar0_is_cached;
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u32 bar0_value;
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+ struct device_node *np;
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struct pci_controller pci_controller;
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+ struct irq_domain *domain;
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struct resource io_res;
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struct resource mem_res;
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};
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+static struct irq_chip ar724x_pci_irq_chip;
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+
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static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
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{
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u32 reset;
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@@ -228,35 +234,31 @@ static struct pci_ops ar724x_pci_ops = {
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static void ar724x_pci_irq_handler(struct irq_desc *desc)
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{
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- struct ar724x_pci_controller *apc;
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- void __iomem *base;
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+ struct irq_chip *chip = irq_desc_get_chip(desc);
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+ struct ar724x_pci_controller *apc = irq_desc_get_handler_data(desc);
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u32 pending;
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- apc = irq_desc_get_handler_data(desc);
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- base = apc->ctrl_base;
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-
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- pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
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- __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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+ chained_irq_enter(chip, desc);
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+ pending = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_STATUS) &
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+ __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_MASK);
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if (pending & AR724X_PCI_INT_DEV0)
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- generic_handle_irq(apc->irq_base + 0);
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-
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+ generic_handle_irq(irq_linear_revmap(apc->domain, 1));
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else
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spurious_interrupt();
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+ chained_irq_exit(chip, desc);
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}
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static void ar724x_pci_irq_unmask(struct irq_data *d)
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{
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struct ar724x_pci_controller *apc;
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void __iomem *base;
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- int offset;
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u32 t;
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apc = irq_data_get_irq_chip_data(d);
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base = apc->ctrl_base;
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- offset = apc->irq_base - d->irq;
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- switch (offset) {
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+ switch (irq_linear_revmap(apc->domain, d->irq)) {
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case 0:
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t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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__raw_writel(t | AR724X_PCI_INT_DEV0,
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@@ -270,14 +272,12 @@ static void ar724x_pci_irq_mask(struct i
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{
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struct ar724x_pci_controller *apc;
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void __iomem *base;
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- int offset;
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u32 t;
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apc = irq_data_get_irq_chip_data(d);
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base = apc->ctrl_base;
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- offset = apc->irq_base - d->irq;
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- switch (offset) {
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+ switch (irq_linear_revmap(apc->domain, d->irq)) {
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case 0:
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t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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__raw_writel(t & ~AR724X_PCI_INT_DEV0,
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@@ -302,26 +302,34 @@ static struct irq_chip ar724x_pci_irq_ch
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.irq_mask_ack = ar724x_pci_irq_mask,
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};
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+static int ar724x_pci_irq_map(struct irq_domain *d,
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+ unsigned int irq, irq_hw_number_t hw)
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+{
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+ struct ar724x_pci_controller *apc = d->host_data;
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+
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+ irq_set_chip_and_handler(irq, &ar724x_pci_irq_chip, handle_level_irq);
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+ irq_set_chip_data(irq, apc);
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+
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+ return 0;
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+}
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+
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+static const struct irq_domain_ops ar724x_pci_domain_ops = {
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+ .xlate = irq_domain_xlate_onecell,
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+ .map = ar724x_pci_irq_map,
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+};
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+
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static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
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int id)
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{
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void __iomem *base;
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- int i;
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base = apc->ctrl_base;
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__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
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__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
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- apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
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-
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- for (i = apc->irq_base;
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- i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
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- irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
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- handle_level_irq);
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- irq_set_chip_data(i, apc);
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- }
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-
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+ apc->domain = irq_domain_add_linear(apc->np, 2,
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+ &ar724x_pci_domain_ops, apc);
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irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,
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apc);
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}
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@@ -360,7 +368,6 @@ static void ar724x_pci_hw_init(struct ar
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static int ar724x_pci_probe(struct platform_device *pdev)
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{
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struct ar724x_pci_controller *apc;
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- struct resource *res;
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int id;
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id = pdev->id;
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@@ -388,29 +395,11 @@ static int ar724x_pci_probe(struct platf
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if (apc->irq < 0)
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return -EINVAL;
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- res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
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- if (!res)
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- return -EINVAL;
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-
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- apc->io_res.parent = res;
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- apc->io_res.name = "PCI IO space";
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- apc->io_res.start = res->start;
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- apc->io_res.end = res->end;
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- apc->io_res.flags = IORESOURCE_IO;
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-
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- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
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- if (!res)
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- return -EINVAL;
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-
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- apc->mem_res.parent = res;
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- apc->mem_res.name = "PCI memory space";
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- apc->mem_res.start = res->start;
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- apc->mem_res.end = res->end;
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- apc->mem_res.flags = IORESOURCE_MEM;
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-
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+ apc->np = pdev->dev.of_node;
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apc->pci_controller.pci_ops = &ar724x_pci_ops;
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apc->pci_controller.io_resource = &apc->io_res;
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apc->pci_controller.mem_resource = &apc->mem_res;
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+ pci_load_of_ranges(&apc->pci_controller, pdev->dev.of_node);
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/*
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* Do the full PCIE Root Complex Initialization Sequence if the PCIe
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@@ -432,10 +421,16 @@ static int ar724x_pci_probe(struct platf
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return 0;
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}
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+static const struct of_device_id ar724x_pci_ids[] = {
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+ { .compatible = "qcom,ar7240-pci" },
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+ {},
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+};
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+
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static struct platform_driver ar724x_pci_driver = {
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.probe = ar724x_pci_probe,
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.driver = {
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.name = "ar724x-pci",
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+ .of_match_table = of_match_ptr(ar724x_pci_ids),
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},
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};
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