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domenico
2025-06-24 14:35:53 +02:00
commit c06fb25d1f
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228
target/linux/layerscape/patches-6.6/302-arm64-dts-ls1012a-update-with-ppfe-support.patch Normal file
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@@ -0,0 +1,228 @@
From 008465a02bf29b366ca7a56dba48ad3a85417ba2 Mon Sep 17 00:00:00 2001
From: Li Yang <leoyang.li@nxp.com>
Date: Thu, 18 Nov 2021 21:46:21 -0600
Subject: [PATCH] arm64: dts: ls1012a: add ppfe support to boards
Update ls1012a dtsi and platform dts files with
support for ppfe.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
.../boot/dts/freescale/fsl-ls1012a-frdm.dts | 44 +++++++++++++++++++
.../boot/dts/freescale/fsl-ls1012a-qds.dts | 43 ++++++++++++++++++
.../boot/dts/freescale/fsl-ls1012a-rdb.dts | 40 +++++++++++++++++
.../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 29 ++++++++++++
4 files changed, 156 insertions(+)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -14,6 +14,11 @@
model = "LS1012A Freedom Board";
compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+ aliases {
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
+ };
+
sys_mclk: clock-mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -110,6 +115,45 @@
};
};
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pfe_mac0: ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ phy-handle = <&sgmii_phy1>;
+ };
+
+ pfe_mac1: ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ phy-handle = <&sgmii_phy2>;
+ };
+
+ mdio@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sgmii_phy1: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ sgmii_phy2: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ };
+};
+
&sai2 {
status = "okay";
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -16,6 +16,8 @@
aliases {
mmc0 = &esdhc0;
mmc1 = &esdhc1;
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
};
sys_mclk: clock-mclk {
@@ -148,6 +150,47 @@
};
};
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pfe_mac0: ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,mdio-mux-val = <0x2>;
+ phy-mode = "sgmii-2500";
+ phy-handle = <&sgmii_phy1>;
+ };
+
+ pfe_mac1: ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,mdio-mux-val = <0x3>;
+ phy-mode = "sgmii-2500";
+ phy-handle = <&sgmii_phy2>;
+ };
+
+ mdio@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x1>;
+ };
+
+ sgmii_phy2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x2>;
+ };
+ };
+};
+
&sai2 {
status = "okay";
};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
@@ -18,6 +18,8 @@
serial0 = &duart0;
mmc0 = &esdhc0;
mmc1 = &esdhc1;
+ ethernet0 = &pfe_mac0;
+ ethernet1 = &pfe_mac1;
};
};
@@ -104,3 +106,41 @@
&sata {
status = "okay";
};
+
+&pfe {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pfe_mac0: ethernet@0 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>; /* GEM_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "sgmii";
+ phy-handle = <&sgmii_phy>;
+ };
+
+ pfe_mac1: ethernet@1 {
+ compatible = "fsl,pfe-gemac-port";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>; /* GEM_ID */
+ fsl,mdio-mux-val = <0x0>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&rgmii_phy>;
+ };
+ mdio@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sgmii_phy: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ rgmii_phy: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ };
+};
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -568,6 +568,35 @@
};
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ pfe_reserved: packetbuffer@83400000 {
+ reg = <0 0x83400000 0 0xc00000>;
+ };
+ };
+
+ pfe: pfe@4000000 {
+ compatible = "fsl,pfe";
+ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
+ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
+ reg-names = "pfe", "pfe-ddr";
+ fsl,pfe-num-interfaces = <0x2>;
+ interrupts = <0 172 0x4>, /* HIF interrupt */
+ <0 173 0x4>, /*HIF_NOCPY interrupt */
+ <0 174 0x4>; /* WoL interrupt */
+ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
+ memory-region = <&pfe_reserved>;
+ fsl,pfe-scfg = <&scfg 0>;
+ fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
+ clocks = <&clockgen 4 0>;
+ clock-names = "pfe";
+
+ status = "okay";
+ };
+
firmware {
optee {
compatible = "linaro,optee-tz";