Initial commit

target/linux/mpc85xx/files/arch/powerpc/boot/dts/br200-wp.dts

@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Aerohive BR200-WP Device Tree Source
+ *
+ * Based on: Aerohive HiveAP-330 Device Tree Source
+ *
+ * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
+ * Copyright (C) 2023 Pawel Dembicki <paweldembicki@gmail.com>
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+
+/ {
+	model = "Aerohive BR200-WP";
+	compatible = "aerohive,br200-wp";
+
+	chosen {
+		bootargs = "console=ttyS0,9600";
+		bootargs-override = "console=ttyS0,9600 noinitrd";
+	};
+
+	aliases {
+		led-boot = &led_attention;
+		led-failsafe = &led_attention;
+		led-running = &led_status;
+		led-upgrade = &led_status;
+		label-mac-device = &enet0;
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	cpus {
+		/delete-property/ PowerPC,P1020@1; /* P1011 have one core only */
+	};
+
+	board_lbc: lbc: localbus@ffe05000 {
+		reg = <0 0xffe05000 0 0x1000>;
+		ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
+
+		nor@0 {
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x4000000>;
+			bank-width = <2>;
+			device-width = <1>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					reg = <0x0 0x40000>;
+					label = "dtb";
+				};
+
+				partition@40000 {
+					reg = <0x40000 0x40000>;
+					label = "initramfs";
+				};
+
+				partition@80000 {
+					reg = <0x80000 0x27c0000>;
+					label = "rootfs";
+				};
+
+				partition@2840000 {
+					reg = <0x2840000 0x800000>;
+					label = "kernel";
+				};
+
+				partition@3040000 {
+					reg = <0x3040000 0xec0000>;
+					label = "stock-jffs2";
+					read-only;
+				};
+
+				partition@3f00000 {
+					reg = <0x3f00000 0x20000>;
+					label = "hw-info";
+					read-only;
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						macaddr_hwinfo_0: macaddr@0 {
+							compatible = "mac-base";
+							reg = <0x0 0x6>;
+							#nvmem-cell-cells = <1>;
+						};
+					};
+				};
+
+				partition@3f20000 {
+					reg = <0x3f20000 0x20000>;
+					label = "boot-info";
+					read-only;
+				};
+
+				partition@3f40000 {
+					reg = <0x3f40000 0x20000>;
+					label = "boot-info-backup";
+					read-only;
+				};
+
+				partition@3f60000 {
+					reg = <0x3f60000 0x20000>;
+					label = "u-boot-env";
+				};
+
+				partition@3f80000 {
+					reg = <0x3f80000 0x80000>;
+					label = "u-boot";
+					read-only;
+				};
+
+				firmware@0 {
+					reg = <0x0 0x3040000>;
+					label = "firmware";
+				};
+			};
+		};
+	};
+
+	board_soc: soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+		mdio@24000 {
+
+			phy_port1: phy@0 {
+				reg = <0>;
+			};
+
+			phy_port2: phy@1 {
+				reg = <1>;
+			};
+
+			phy_port3: phy@2 {
+				reg = <2>;
+			};
+
+			phy_port4: phy@3 {
+				reg = <3>;
+			};
+
+			phy_port5: phy@4 {
+				reg = <4>;
+			};
+
+			switch@10 {
+				compatible = "qca,qca8327";
+				reg = <0x10>;
+				reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@1 {
+						reg = <1>;
+						label = "lan1";
+						phy-handle = <&phy_port1>;
+						nvmem-cells = <&macaddr_hwinfo_0 2>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@2 {
+						reg = <2>;
+						label = "lan2";
+						phy-handle = <&phy_port2>;
+						nvmem-cells = <&macaddr_hwinfo_0 3>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@3 {
+						reg = <3>;
+						label = "lan3";
+						phy-handle = <&phy_port3>;
+						nvmem-cells = <&macaddr_hwinfo_0 4>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@4 {
+						reg = <4>;
+						label = "lan4";
+						phy-handle = <&phy_port4>;
+						nvmem-cells = <&macaddr_hwinfo_0 5>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@5 {
+						reg = <5>;
+						label = "wan";
+						phy-handle = <&phy_port5>;
+						nvmem-cells = <&macaddr_hwinfo_0 0>;
+						nvmem-cell-names = "mac-address";
+					};
+
+					port@6 {
+						reg = <6>;
+						ethernet = <&enet0>;
+						phy-mode = "rgmii-id";
+
+						fixed-link {
+							speed = <1000>;
+							full-duplex;
+						};
+					};
+				};
+			};
+		};
+
+		mdio@25000 {
+			status = "disabled";
+		};
+
+		mdio@26000 {
+			status = "disabled";
+		};
+
+		enet0: ethernet@b0000 {
+			status = "okay";
+			phy-connection-type = "rgmii-id";
+			nvmem-cells = <&macaddr_hwinfo_0 0>;
+			nvmem-cell-names = "mac-address";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
+		};
+
+		enet1: ethernet@b1000 {
+			status = "disabled";
+		};
+
+		enet2: ethernet@b2000 {
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller@fc00 {
+		};
+
+		usb@22000 {
+			phy_type = "ulpi";
+			dr_mode = "host";
+		};
+
+		usb@23000 {
+			status = "disabled";
+		};
+	};
+
+	pci0: pcie@ffe09000 {
+		status = "disabled";
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0x0 0xffe0a000 0x0 0x1000>;
+		ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
+				  0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
+
+		reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
+
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xc0000000
+				  0x2000000 0x0 0xc0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+
+			ath9k: wifi@0,0 {
+				reg = <0x0000 0 0 0 0>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				nvmem-cells = <&macaddr_hwinfo_0 16>;
+				nvmem-cell-names = "mac-address";
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_attention: led-0 {
+			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_AMBER>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led_status: led-1 {
+			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_WHITE>;
+			function = LED_FUNCTION_STATUS;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "Reset button";
+			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+};
+
+/include/ "fsl/p1020si-post.dtsi"
+
+/ {
+	chosen {
+		stdout-path = "/soc@ffe00000/serial@4500";
+	};
+
+	cpus {
+		PowerPC,P1020@0 {
+			i-cache-sets = <0x80>;
+			i-cache-size = <0x8000>;
+			i-cache-block-size = <0x20>;
+			d-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-block-size = <0x20>;
+			clock-frequency = <0x2756cd00>;
+			bus-frequency = <0x13ab6680>;
+			timebase-frequency = <0x2756cd0>;
+		};
+	};
+
+	memory {
+		reg = <0x00 0x00 0x00 0x10000000>;
+	};
+
+	localbus@ffe05000 {
+		bus-frequency = <0x13ab668>;
+	};
+
+	soc@ffe00000 {
+		bus-frequency = <0x13ab6680>;
+
+		serial@4500 {
+			clock-frequency = <0x13ab6680>;
+		};
+
+		serial@4600 {
+			clock-frequency = <0x13ab6680>;
+		};
+	};
+
+	pcie@ffe09000 {
+		clock-frequency = <0x1fca055>;
+	};
+
+	pcie@ffe0a000 {
+		clock-frequency = <0x1fca055>;
+	};
+};