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domenico
2025-06-24 14:35:53 +02:00
commit c06fb25d1f
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target/linux/ramips/files/drivers/dma/mediatek/hsdma-mt7621.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015, Michael Lee <igvtee@gmail.com>
* MTK HSDMA support
*/
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <linux/of_dma.h>
#include <linux/reset.h>
#include <linux/of_device.h>
#include "../virt-dma.h"
#define HSDMA_BASE_OFFSET 0x800
#define HSDMA_REG_TX_BASE 0x00
#define HSDMA_REG_TX_CNT 0x04
#define HSDMA_REG_TX_CTX 0x08
#define HSDMA_REG_TX_DTX 0x0c
#define HSDMA_REG_RX_BASE 0x100
#define HSDMA_REG_RX_CNT 0x104
#define HSDMA_REG_RX_CRX 0x108
#define HSDMA_REG_RX_DRX 0x10c
#define HSDMA_REG_INFO 0x200
#define HSDMA_REG_GLO_CFG 0x204
#define HSDMA_REG_RST_CFG 0x208
#define HSDMA_REG_DELAY_INT 0x20c
#define HSDMA_REG_FREEQ_THRES 0x210
#define HSDMA_REG_INT_STATUS 0x220
#define HSDMA_REG_INT_MASK 0x228
#define HSDMA_REG_SCH_Q01 0x280
#define HSDMA_REG_SCH_Q23 0x284
#define HSDMA_DESCS_MAX 0xfff
#define HSDMA_DESCS_NUM 8
#define HSDMA_DESCS_MASK (HSDMA_DESCS_NUM - 1)
#define HSDMA_NEXT_DESC(x) (((x) + 1) & HSDMA_DESCS_MASK)
/* HSDMA_REG_INFO */
#define HSDMA_INFO_INDEX_MASK 0xf
#define HSDMA_INFO_INDEX_SHIFT 24
#define HSDMA_INFO_BASE_MASK 0xff
#define HSDMA_INFO_BASE_SHIFT 16
#define HSDMA_INFO_RX_MASK 0xff
#define HSDMA_INFO_RX_SHIFT 8
#define HSDMA_INFO_TX_MASK 0xff
#define HSDMA_INFO_TX_SHIFT 0
/* HSDMA_REG_GLO_CFG */
#define HSDMA_GLO_TX_2B_OFFSET BIT(31)
#define HSDMA_GLO_CLK_GATE BIT(30)
#define HSDMA_GLO_BYTE_SWAP BIT(29)
#define HSDMA_GLO_MULTI_DMA BIT(10)
#define HSDMA_GLO_TWO_BUF BIT(9)
#define HSDMA_GLO_32B_DESC BIT(8)
#define HSDMA_GLO_BIG_ENDIAN BIT(7)
#define HSDMA_GLO_TX_DONE BIT(6)
#define HSDMA_GLO_BT_MASK 0x3
#define HSDMA_GLO_BT_SHIFT 4
#define HSDMA_GLO_RX_BUSY BIT(3)
#define HSDMA_GLO_RX_DMA BIT(2)
#define HSDMA_GLO_TX_BUSY BIT(1)
#define HSDMA_GLO_TX_DMA BIT(0)
#define HSDMA_BT_SIZE_16BYTES (0 << HSDMA_GLO_BT_SHIFT)
#define HSDMA_BT_SIZE_32BYTES (1 << HSDMA_GLO_BT_SHIFT)
#define HSDMA_BT_SIZE_64BYTES (2 << HSDMA_GLO_BT_SHIFT)
#define HSDMA_BT_SIZE_128BYTES (3 << HSDMA_GLO_BT_SHIFT)
#define HSDMA_GLO_DEFAULT (HSDMA_GLO_MULTI_DMA | \
HSDMA_GLO_RX_DMA | HSDMA_GLO_TX_DMA | HSDMA_BT_SIZE_32BYTES)
/* HSDMA_REG_RST_CFG */
#define HSDMA_RST_RX_SHIFT 16
#define HSDMA_RST_TX_SHIFT 0
/* HSDMA_REG_DELAY_INT */
#define HSDMA_DELAY_INT_EN BIT(15)
#define HSDMA_DELAY_PEND_OFFSET 8
#define HSDMA_DELAY_TIME_OFFSET 0
#define HSDMA_DELAY_TX_OFFSET 16
#define HSDMA_DELAY_RX_OFFSET 0
#define HSDMA_DELAY_INIT(x) (HSDMA_DELAY_INT_EN | \
((x) << HSDMA_DELAY_PEND_OFFSET))
#define HSDMA_DELAY(x) ((HSDMA_DELAY_INIT(x) << \
HSDMA_DELAY_TX_OFFSET) | HSDMA_DELAY_INIT(x))
/* HSDMA_REG_INT_STATUS */
#define HSDMA_INT_DELAY_RX_COH BIT(31)
#define HSDMA_INT_DELAY_RX_INT BIT(30)
#define HSDMA_INT_DELAY_TX_COH BIT(29)
#define HSDMA_INT_DELAY_TX_INT BIT(28)
#define HSDMA_INT_RX_MASK 0x3
#define HSDMA_INT_RX_SHIFT 16
#define HSDMA_INT_RX_Q0 BIT(16)
#define HSDMA_INT_TX_MASK 0xf
#define HSDMA_INT_TX_SHIFT 0
#define HSDMA_INT_TX_Q0 BIT(0)
/* tx/rx dma desc flags */
#define HSDMA_PLEN_MASK 0x3fff
#define HSDMA_DESC_DONE BIT(31)
#define HSDMA_DESC_LS0 BIT(30)
#define HSDMA_DESC_PLEN0(_x) (((_x) & HSDMA_PLEN_MASK) << 16)
#define HSDMA_DESC_TAG BIT(15)
#define HSDMA_DESC_LS1 BIT(14)
#define HSDMA_DESC_PLEN1(_x) ((_x) & HSDMA_PLEN_MASK)
/* align 4 bytes */
#define HSDMA_ALIGN_SIZE 3
/* align size 128bytes */
#define HSDMA_MAX_PLEN 0x3f80
struct hsdma_desc {
u32 addr0;
u32 flags;
u32 addr1;
u32 unused;
};
struct mtk_hsdma_sg {
dma_addr_t src_addr;
dma_addr_t dst_addr;
u32 len;
};
struct mtk_hsdma_desc {
struct virt_dma_desc vdesc;
unsigned int num_sgs;
struct mtk_hsdma_sg sg[1];
};
struct mtk_hsdma_chan {
struct virt_dma_chan vchan;
unsigned int id;
dma_addr_t desc_addr;
int tx_idx;
int rx_idx;
struct hsdma_desc *tx_ring;
struct hsdma_desc *rx_ring;
struct mtk_hsdma_desc *desc;
unsigned int next_sg;
};
struct mtk_hsdam_engine {
struct dma_device ddev;
struct device_dma_parameters dma_parms;
void __iomem *base;
struct tasklet_struct task;
volatile unsigned long chan_issued;
struct mtk_hsdma_chan chan[1];
};
static inline struct mtk_hsdam_engine *mtk_hsdma_chan_get_dev(struct mtk_hsdma_chan *chan)
{
return container_of(chan->vchan.chan.device, struct mtk_hsdam_engine,
ddev);
}
static inline struct mtk_hsdma_chan *to_mtk_hsdma_chan(struct dma_chan *c)
{
return container_of(c, struct mtk_hsdma_chan, vchan.chan);
}
static inline struct mtk_hsdma_desc *to_mtk_hsdma_desc(struct virt_dma_desc *vdesc)
{
return container_of(vdesc, struct mtk_hsdma_desc, vdesc);
}
static inline u32 mtk_hsdma_read(struct mtk_hsdam_engine *hsdma, u32 reg)
{
return readl(hsdma->base + reg);
}
static inline void mtk_hsdma_write(struct mtk_hsdam_engine *hsdma,
unsigned int reg, u32 val)
{
writel(val, hsdma->base + reg);
}
static void mtk_hsdma_reset_chan(struct mtk_hsdam_engine *hsdma,
struct mtk_hsdma_chan *chan)
{
chan->tx_idx = 0;
chan->rx_idx = HSDMA_DESCS_NUM - 1;
mtk_hsdma_write(hsdma, HSDMA_REG_TX_CTX, chan->tx_idx);
mtk_hsdma_write(hsdma, HSDMA_REG_RX_CRX, chan->rx_idx);
mtk_hsdma_write(hsdma, HSDMA_REG_RST_CFG,
0x1 << (chan->id + HSDMA_RST_TX_SHIFT));
mtk_hsdma_write(hsdma, HSDMA_REG_RST_CFG,
0x1 << (chan->id + HSDMA_RST_RX_SHIFT));
}
static void hsdma_dump_reg(struct mtk_hsdam_engine *hsdma)
{
dev_dbg(hsdma->ddev.dev,
"tbase %08x, tcnt %08x, tctx %08x, tdtx: %08x, rbase %08x, rcnt %08x, rctx %08x, rdtx %08x\n",
mtk_hsdma_read(hsdma, HSDMA_REG_TX_BASE),
mtk_hsdma_read(hsdma, HSDMA_REG_TX_CNT),
mtk_hsdma_read(hsdma, HSDMA_REG_TX_CTX),
mtk_hsdma_read(hsdma, HSDMA_REG_TX_DTX),
mtk_hsdma_read(hsdma, HSDMA_REG_RX_BASE),
mtk_hsdma_read(hsdma, HSDMA_REG_RX_CNT),
mtk_hsdma_read(hsdma, HSDMA_REG_RX_CRX),
mtk_hsdma_read(hsdma, HSDMA_REG_RX_DRX));
dev_dbg(hsdma->ddev.dev,
"info %08x, glo %08x, delay %08x, intr_stat %08x, intr_mask %08x\n",
mtk_hsdma_read(hsdma, HSDMA_REG_INFO),
mtk_hsdma_read(hsdma, HSDMA_REG_GLO_CFG),
mtk_hsdma_read(hsdma, HSDMA_REG_DELAY_INT),
mtk_hsdma_read(hsdma, HSDMA_REG_INT_STATUS),
mtk_hsdma_read(hsdma, HSDMA_REG_INT_MASK));
}
static void hsdma_dump_desc(struct mtk_hsdam_engine *hsdma,
struct mtk_hsdma_chan *chan)
{
struct hsdma_desc *tx_desc;
struct hsdma_desc *rx_desc;
int i;
dev_dbg(hsdma->ddev.dev, "tx idx: %d, rx idx: %d\n",
chan->tx_idx, chan->rx_idx);
for (i = 0; i < HSDMA_DESCS_NUM; i++) {
tx_desc = &chan->tx_ring[i];
rx_desc = &chan->rx_ring[i];
dev_dbg(hsdma->ddev.dev,
"%d tx addr0: %08x, flags %08x, tx addr1: %08x, rx addr0 %08x, flags %08x\n",
i, tx_desc->addr0, tx_desc->flags,
tx_desc->addr1, rx_desc->addr0, rx_desc->flags);
}
}
static void mtk_hsdma_reset(struct mtk_hsdam_engine *hsdma,
struct mtk_hsdma_chan *chan)
{
int i;
/* disable dma */
mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, 0);
/* disable intr */
mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, 0);
/* init desc value */
for (i = 0; i < HSDMA_DESCS_NUM; i++) {
chan->tx_ring[i].addr0 = 0;
chan->tx_ring[i].flags = HSDMA_DESC_LS0 | HSDMA_DESC_DONE;
}
for (i = 0; i < HSDMA_DESCS_NUM; i++) {
chan->rx_ring[i].addr0 = 0;
chan->rx_ring[i].flags = 0;
}
/* reset */
mtk_hsdma_reset_chan(hsdma, chan);
/* enable intr */
mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, HSDMA_INT_RX_Q0);
/* enable dma */
mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, HSDMA_GLO_DEFAULT);
}
static int mtk_hsdma_terminate_all(struct dma_chan *c)
{
struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
struct mtk_hsdam_engine *hsdma = mtk_hsdma_chan_get_dev(chan);
unsigned long timeout;
LIST_HEAD(head);
spin_lock_bh(&chan->vchan.lock);
chan->desc = NULL;
clear_bit(chan->id, &hsdma->chan_issued);
vchan_get_all_descriptors(&chan->vchan, &head);
spin_unlock_bh(&chan->vchan.lock);
vchan_dma_desc_free_list(&chan->vchan, &head);
/* wait dma transfer complete */
timeout = jiffies + msecs_to_jiffies(2000);
while (mtk_hsdma_read(hsdma, HSDMA_REG_GLO_CFG) &
(HSDMA_GLO_RX_BUSY | HSDMA_GLO_TX_BUSY)) {
if (time_after_eq(jiffies, timeout)) {
hsdma_dump_desc(hsdma, chan);
mtk_hsdma_reset(hsdma, chan);
dev_err(hsdma->ddev.dev, "timeout, reset it\n");
break;
}
cpu_relax();
}
return 0;
}
static int mtk_hsdma_start_transfer(struct mtk_hsdam_engine *hsdma,
struct mtk_hsdma_chan *chan)
{
dma_addr_t src, dst;
size_t len, tlen;
struct hsdma_desc *tx_desc, *rx_desc;
struct mtk_hsdma_sg *sg;
unsigned int i;
int rx_idx;
sg = &chan->desc->sg[0];
len = sg->len;
chan->desc->num_sgs = DIV_ROUND_UP(len, HSDMA_MAX_PLEN);
/* tx desc */
src = sg->src_addr;
for (i = 0; i < chan->desc->num_sgs; i++) {
tx_desc = &chan->tx_ring[chan->tx_idx];
if (len > HSDMA_MAX_PLEN)
tlen = HSDMA_MAX_PLEN;
else
tlen = len;
if (i & 0x1) {
tx_desc->addr1 = src;
tx_desc->flags |= HSDMA_DESC_PLEN1(tlen);
} else {
tx_desc->addr0 = src;
tx_desc->flags = HSDMA_DESC_PLEN0(tlen);
/* update index */
chan->tx_idx = HSDMA_NEXT_DESC(chan->tx_idx);
}
src += tlen;
len -= tlen;
}
if (i & 0x1)
tx_desc->flags |= HSDMA_DESC_LS0;
else
tx_desc->flags |= HSDMA_DESC_LS1;
/* rx desc */
rx_idx = HSDMA_NEXT_DESC(chan->rx_idx);
len = sg->len;
dst = sg->dst_addr;
for (i = 0; i < chan->desc->num_sgs; i++) {
rx_desc = &chan->rx_ring[rx_idx];
if (len > HSDMA_MAX_PLEN)
tlen = HSDMA_MAX_PLEN;
else
tlen = len;
rx_desc->addr0 = dst;
rx_desc->flags = HSDMA_DESC_PLEN0(tlen);
dst += tlen;
len -= tlen;
/* update index */
rx_idx = HSDMA_NEXT_DESC(rx_idx);
}
/* make sure desc and index all up to date */
wmb();
mtk_hsdma_write(hsdma, HSDMA_REG_TX_CTX, chan->tx_idx);
return 0;
}
static int gdma_next_desc(struct mtk_hsdma_chan *chan)
{
struct virt_dma_desc *vdesc;
vdesc = vchan_next_desc(&chan->vchan);
if (!vdesc) {
chan->desc = NULL;
return 0;
}
chan->desc = to_mtk_hsdma_desc(vdesc);
chan->next_sg = 0;
return 1;
}
static void mtk_hsdma_chan_done(struct mtk_hsdam_engine *hsdma,
struct mtk_hsdma_chan *chan)
{
struct mtk_hsdma_desc *desc;
int chan_issued;
chan_issued = 0;
spin_lock_bh(&chan->vchan.lock);
desc = chan->desc;
if (likely(desc)) {
if (chan->next_sg == desc->num_sgs) {
list_del(&desc->vdesc.node);
vchan_cookie_complete(&desc->vdesc);
chan_issued = gdma_next_desc(chan);
}
} else {
dev_dbg(hsdma->ddev.dev, "no desc to complete\n");
}
if (chan_issued)
set_bit(chan->id, &hsdma->chan_issued);
spin_unlock_bh(&chan->vchan.lock);
}
static irqreturn_t mtk_hsdma_irq(int irq, void *devid)
{
struct mtk_hsdam_engine *hsdma = devid;
u32 status;
status = mtk_hsdma_read(hsdma, HSDMA_REG_INT_STATUS);
if (unlikely(!status))
return IRQ_NONE;
if (likely(status & HSDMA_INT_RX_Q0))
tasklet_schedule(&hsdma->task);
else
dev_dbg(hsdma->ddev.dev, "unhandle irq status %08x\n", status);
/* clean intr bits */
mtk_hsdma_write(hsdma, HSDMA_REG_INT_STATUS, status);
return IRQ_HANDLED;
}
static void mtk_hsdma_issue_pending(struct dma_chan *c)
{
struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
struct mtk_hsdam_engine *hsdma = mtk_hsdma_chan_get_dev(chan);
spin_lock_bh(&chan->vchan.lock);
if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
if (gdma_next_desc(chan)) {
set_bit(chan->id, &hsdma->chan_issued);
tasklet_schedule(&hsdma->task);
} else {
dev_dbg(hsdma->ddev.dev, "no desc to issue\n");
}
}
spin_unlock_bh(&chan->vchan.lock);
}
static struct dma_async_tx_descriptor *mtk_hsdma_prep_dma_memcpy(
struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
size_t len, unsigned long flags)
{
struct mtk_hsdma_chan *chan = to_mtk_hsdma_chan(c);
struct mtk_hsdma_desc *desc;
if (len <= 0)
return NULL;
desc = kzalloc(sizeof(*desc), GFP_ATOMIC);
if (!desc) {
dev_err(c->device->dev, "alloc memcpy decs error\n");
return NULL;
}
desc->sg[0].src_addr = src;
desc->sg[0].dst_addr = dest;
desc->sg[0].len = len;
return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
}
static enum dma_status mtk_hsdma_tx_status(struct dma_chan *c,
dma_cookie_t cookie,
struct dma_tx_state *state)
{
return dma_cookie_status(c, cookie, state);
}
static void mtk_hsdma_free_chan_resources(struct dma_chan *c)
{
vchan_free_chan_resources(to_virt_chan(c));
}
static void mtk_hsdma_desc_free(struct virt_dma_desc *vdesc)
{
kfree(container_of(vdesc, struct mtk_hsdma_desc, vdesc));
}
static void mtk_hsdma_tx(struct mtk_hsdam_engine *hsdma)
{
struct mtk_hsdma_chan *chan;
if (test_and_clear_bit(0, &hsdma->chan_issued)) {
chan = &hsdma->chan[0];
if (chan->desc)
mtk_hsdma_start_transfer(hsdma, chan);
else
dev_dbg(hsdma->ddev.dev, "chan 0 no desc to issue\n");
}
}
static void mtk_hsdma_rx(struct mtk_hsdam_engine *hsdma)
{
struct mtk_hsdma_chan *chan;
int next_idx, drx_idx, cnt;
chan = &hsdma->chan[0];
next_idx = HSDMA_NEXT_DESC(chan->rx_idx);
drx_idx = mtk_hsdma_read(hsdma, HSDMA_REG_RX_DRX);
cnt = (drx_idx - next_idx) & HSDMA_DESCS_MASK;
if (!cnt)
return;
chan->next_sg += cnt;
chan->rx_idx = (chan->rx_idx + cnt) & HSDMA_DESCS_MASK;
/* update rx crx */
wmb();
mtk_hsdma_write(hsdma, HSDMA_REG_RX_CRX, chan->rx_idx);
mtk_hsdma_chan_done(hsdma, chan);
}
static void mtk_hsdma_tasklet(struct tasklet_struct *t)
{
struct mtk_hsdam_engine *hsdma = from_tasklet(hsdma, t, task);
mtk_hsdma_rx(hsdma);
mtk_hsdma_tx(hsdma);
}
static int mtk_hsdam_alloc_desc(struct mtk_hsdam_engine *hsdma,
struct mtk_hsdma_chan *chan)
{
int i;
chan->tx_ring = dma_alloc_coherent(hsdma->ddev.dev,
2 * HSDMA_DESCS_NUM *
sizeof(*chan->tx_ring),
&chan->desc_addr, GFP_ATOMIC | __GFP_ZERO);
if (!chan->tx_ring)
goto no_mem;
chan->rx_ring = &chan->tx_ring[HSDMA_DESCS_NUM];
/* init tx ring value */
for (i = 0; i < HSDMA_DESCS_NUM; i++)
chan->tx_ring[i].flags = HSDMA_DESC_LS0 | HSDMA_DESC_DONE;
return 0;
no_mem:
return -ENOMEM;
}
static void mtk_hsdam_free_desc(struct mtk_hsdam_engine *hsdma,
struct mtk_hsdma_chan *chan)
{
if (chan->tx_ring) {
dma_free_coherent(hsdma->ddev.dev,
2 * HSDMA_DESCS_NUM * sizeof(*chan->tx_ring),
chan->tx_ring, chan->desc_addr);
chan->tx_ring = NULL;
chan->rx_ring = NULL;
}
}
static int mtk_hsdma_init(struct mtk_hsdam_engine *hsdma)
{
struct mtk_hsdma_chan *chan;
int ret;
u32 reg;
/* init desc */
chan = &hsdma->chan[0];
ret = mtk_hsdam_alloc_desc(hsdma, chan);
if (ret)
return ret;
/* tx */
mtk_hsdma_write(hsdma, HSDMA_REG_TX_BASE, chan->desc_addr);
mtk_hsdma_write(hsdma, HSDMA_REG_TX_CNT, HSDMA_DESCS_NUM);
/* rx */
mtk_hsdma_write(hsdma, HSDMA_REG_RX_BASE, chan->desc_addr +
(sizeof(struct hsdma_desc) * HSDMA_DESCS_NUM));
mtk_hsdma_write(hsdma, HSDMA_REG_RX_CNT, HSDMA_DESCS_NUM);
/* reset */
mtk_hsdma_reset_chan(hsdma, chan);
/* enable rx intr */
mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, HSDMA_INT_RX_Q0);
/* enable dma */
mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, HSDMA_GLO_DEFAULT);
/* hardware info */
reg = mtk_hsdma_read(hsdma, HSDMA_REG_INFO);
dev_info(hsdma->ddev.dev, "rx: %d, tx: %d\n",
(reg >> HSDMA_INFO_RX_SHIFT) & HSDMA_INFO_RX_MASK,
(reg >> HSDMA_INFO_TX_SHIFT) & HSDMA_INFO_TX_MASK);
hsdma_dump_reg(hsdma);
return ret;
}
static void mtk_hsdma_uninit(struct mtk_hsdam_engine *hsdma)
{
struct mtk_hsdma_chan *chan;
/* disable dma */
mtk_hsdma_write(hsdma, HSDMA_REG_GLO_CFG, 0);
/* disable intr */
mtk_hsdma_write(hsdma, HSDMA_REG_INT_MASK, 0);
/* free desc */
chan = &hsdma->chan[0];
mtk_hsdam_free_desc(hsdma, chan);
/* tx */
mtk_hsdma_write(hsdma, HSDMA_REG_TX_BASE, 0);
mtk_hsdma_write(hsdma, HSDMA_REG_TX_CNT, 0);
/* rx */
mtk_hsdma_write(hsdma, HSDMA_REG_RX_BASE, 0);
mtk_hsdma_write(hsdma, HSDMA_REG_RX_CNT, 0);
/* reset */
mtk_hsdma_reset_chan(hsdma, chan);
}
static const struct of_device_id mtk_hsdma_of_match[] = {
{ .compatible = "mediatek,mt7621-hsdma" },
{ },
};
static int mtk_hsdma_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
struct mtk_hsdma_chan *chan;
struct mtk_hsdam_engine *hsdma;
struct dma_device *dd;
int ret;
int irq;
void __iomem *base;
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
if (ret)
return ret;
match = of_match_device(mtk_hsdma_of_match, &pdev->dev);
if (!match)
return -EINVAL;
hsdma = devm_kzalloc(&pdev->dev, sizeof(*hsdma), GFP_KERNEL);
if (!hsdma)
return -EINVAL;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
hsdma->base = base + HSDMA_BASE_OFFSET;
tasklet_setup(&hsdma->task, mtk_hsdma_tasklet);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return -EINVAL;
ret = devm_request_irq(&pdev->dev, irq, mtk_hsdma_irq,
0, dev_name(&pdev->dev), hsdma);
if (ret) {
dev_err(&pdev->dev, "failed to request irq\n");
return ret;
}
ret = device_reset(&pdev->dev);
if (ret)
dev_err(&pdev->dev, "failed to reset device\n");
dd = &hsdma->ddev;
dma_cap_set(DMA_MEMCPY, dd->cap_mask);
dd->copy_align = HSDMA_ALIGN_SIZE;
dd->device_free_chan_resources = mtk_hsdma_free_chan_resources;
dd->device_prep_dma_memcpy = mtk_hsdma_prep_dma_memcpy;
dd->device_terminate_all = mtk_hsdma_terminate_all;
dd->device_tx_status = mtk_hsdma_tx_status;
dd->device_issue_pending = mtk_hsdma_issue_pending;
dd->dev = &pdev->dev;
dd->dev->dma_parms = &hsdma->dma_parms;
dma_set_max_seg_size(dd->dev, HSDMA_MAX_PLEN);
INIT_LIST_HEAD(&dd->channels);
chan = &hsdma->chan[0];
chan->id = 0;
chan->vchan.desc_free = mtk_hsdma_desc_free;
vchan_init(&chan->vchan, dd);
/* init hardware */
ret = mtk_hsdma_init(hsdma);
if (ret) {
dev_err(&pdev->dev, "failed to alloc ring descs\n");
return ret;
}
ret = dma_async_device_register(dd);
if (ret) {
dev_err(&pdev->dev, "failed to register dma device\n");
goto err_uninit_hsdma;
}
ret = of_dma_controller_register(pdev->dev.of_node,
of_dma_xlate_by_chan_id, hsdma);
if (ret) {
dev_err(&pdev->dev, "failed to register of dma controller\n");
goto err_unregister;
}
platform_set_drvdata(pdev, hsdma);
return 0;
err_unregister:
dma_async_device_unregister(dd);
err_uninit_hsdma:
mtk_hsdma_uninit(hsdma);
return ret;
}
static int mtk_hsdma_remove(struct platform_device *pdev)
{
struct mtk_hsdam_engine *hsdma = platform_get_drvdata(pdev);
mtk_hsdma_uninit(hsdma);
of_dma_controller_free(pdev->dev.of_node);
dma_async_device_unregister(&hsdma->ddev);
return 0;
}
static struct platform_driver mtk_hsdma_driver = {
.probe = mtk_hsdma_probe,
.remove = mtk_hsdma_remove,
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = mtk_hsdma_of_match,
},
};
module_platform_driver(mtk_hsdma_driver);
MODULE_AUTHOR("Michael Lee <igvtee@gmail.com>");
MODULE_DESCRIPTION("MTK HSDMA driver");
MODULE_LICENSE("GPL v2");

915
target/linux/ramips/files/drivers/dma/ralink-gdma.c Normal file
View File

@@ -0,0 +1,915 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* GDMA4740 DMAC support
*/
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <linux/of_dma.h>
#include <linux/reset.h>
#include <linux/of_device.h>
#include "virt-dma.h"
#define GDMA_REG_SRC_ADDR(x) (0x00 + (x) * 0x10)
#define GDMA_REG_DST_ADDR(x) (0x04 + (x) * 0x10)
#define GDMA_REG_CTRL0(x) (0x08 + (x) * 0x10)
#define GDMA_REG_CTRL0_TX_MASK 0xffff
#define GDMA_REG_CTRL0_TX_SHIFT 16
#define GDMA_REG_CTRL0_CURR_MASK 0xff
#define GDMA_REG_CTRL0_CURR_SHIFT 8
#define GDMA_REG_CTRL0_SRC_ADDR_FIXED BIT(7)
#define GDMA_REG_CTRL0_DST_ADDR_FIXED BIT(6)
#define GDMA_REG_CTRL0_BURST_MASK 0x7
#define GDMA_REG_CTRL0_BURST_SHIFT 3
#define GDMA_REG_CTRL0_DONE_INT BIT(2)
#define GDMA_REG_CTRL0_ENABLE BIT(1)
#define GDMA_REG_CTRL0_SW_MODE BIT(0)
#define GDMA_REG_CTRL1(x) (0x0c + (x) * 0x10)
#define GDMA_REG_CTRL1_SEG_MASK 0xf
#define GDMA_REG_CTRL1_SEG_SHIFT 22
#define GDMA_REG_CTRL1_REQ_MASK 0x3f
#define GDMA_REG_CTRL1_SRC_REQ_SHIFT 16
#define GDMA_REG_CTRL1_DST_REQ_SHIFT 8
#define GDMA_REG_CTRL1_NEXT_MASK 0x1f
#define GDMA_REG_CTRL1_NEXT_SHIFT 3
#define GDMA_REG_CTRL1_COHERENT BIT(2)
#define GDMA_REG_CTRL1_FAIL BIT(1)
#define GDMA_REG_CTRL1_MASK BIT(0)
#define GDMA_REG_UNMASK_INT 0x200
#define GDMA_REG_DONE_INT 0x204
#define GDMA_REG_GCT 0x220
#define GDMA_REG_GCT_CHAN_MASK 0x3
#define GDMA_REG_GCT_CHAN_SHIFT 3
#define GDMA_REG_GCT_VER_MASK 0x3
#define GDMA_REG_GCT_VER_SHIFT 1
#define GDMA_REG_GCT_ARBIT_RR BIT(0)
#define GDMA_REG_REQSTS 0x2a0
#define GDMA_REG_ACKSTS 0x2a4
#define GDMA_REG_FINSTS 0x2a8
/* for RT305X gdma registers */
#define GDMA_RT305X_CTRL0_REQ_MASK 0xf
#define GDMA_RT305X_CTRL0_SRC_REQ_SHIFT 12
#define GDMA_RT305X_CTRL0_DST_REQ_SHIFT 8
#define GDMA_RT305X_CTRL1_FAIL BIT(4)
#define GDMA_RT305X_CTRL1_NEXT_MASK 0x7
#define GDMA_RT305X_CTRL1_NEXT_SHIFT 1
#define GDMA_RT305X_STATUS_INT 0x80
#define GDMA_RT305X_STATUS_SIGNAL 0x84
#define GDMA_RT305X_GCT 0x88
/* for MT7621 gdma registers */
#define GDMA_REG_PERF_START(x) (0x230 + (x) * 0x8)
#define GDMA_REG_PERF_END(x) (0x234 + (x) * 0x8)
enum gdma_dma_transfer_size {
GDMA_TRANSFER_SIZE_4BYTE = 0,
GDMA_TRANSFER_SIZE_8BYTE = 1,
GDMA_TRANSFER_SIZE_16BYTE = 2,
GDMA_TRANSFER_SIZE_32BYTE = 3,
GDMA_TRANSFER_SIZE_64BYTE = 4,
};
struct gdma_dma_sg {
dma_addr_t src_addr;
dma_addr_t dst_addr;
u32 len;
};
struct gdma_dma_desc {
struct virt_dma_desc vdesc;
enum dma_transfer_direction direction;
bool cyclic;
u32 residue;
unsigned int num_sgs;
struct gdma_dma_sg sg[];
};
struct gdma_dmaengine_chan {
struct virt_dma_chan vchan;
unsigned int id;
unsigned int slave_id;
dma_addr_t fifo_addr;
enum gdma_dma_transfer_size burst_size;
struct gdma_dma_desc *desc;
unsigned int next_sg;
};
struct gdma_dma_dev {
struct dma_device ddev;
struct device_dma_parameters dma_parms;
struct gdma_data *data;
void __iomem *base;
struct tasklet_struct task;
volatile unsigned long chan_issued;
atomic_t cnt;
struct gdma_dmaengine_chan chan[];
};
struct gdma_data {
int chancnt;
u32 done_int_reg;
void (*init)(struct gdma_dma_dev *dma_dev);
int (*start_transfer)(struct gdma_dmaengine_chan *chan);
};
static struct gdma_dma_dev *gdma_dma_chan_get_dev(
struct gdma_dmaengine_chan *chan)
{
return container_of(chan->vchan.chan.device, struct gdma_dma_dev,
ddev);
}
static struct gdma_dmaengine_chan *to_gdma_dma_chan(struct dma_chan *c)
{
return container_of(c, struct gdma_dmaengine_chan, vchan.chan);
}
static struct gdma_dma_desc *to_gdma_dma_desc(struct virt_dma_desc *vdesc)
{
return container_of(vdesc, struct gdma_dma_desc, vdesc);
}
static inline uint32_t gdma_dma_read(struct gdma_dma_dev *dma_dev,
unsigned int reg)
{
return readl(dma_dev->base + reg);
}
static inline void gdma_dma_write(struct gdma_dma_dev *dma_dev,
unsigned int reg, uint32_t val)
{
writel(val, dma_dev->base + reg);
}
static enum gdma_dma_transfer_size gdma_dma_maxburst(u32 maxburst)
{
if (maxburst < 2)
return GDMA_TRANSFER_SIZE_4BYTE;
else if (maxburst < 4)
return GDMA_TRANSFER_SIZE_8BYTE;
else if (maxburst < 8)
return GDMA_TRANSFER_SIZE_16BYTE;
else if (maxburst < 16)
return GDMA_TRANSFER_SIZE_32BYTE;
else
return GDMA_TRANSFER_SIZE_64BYTE;
}
static int gdma_dma_config(struct dma_chan *c,
struct dma_slave_config *config)
{
struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
if (config->device_fc) {
dev_err(dma_dev->ddev.dev, "not support flow controller\n");
return -EINVAL;
}
switch (config->direction) {
case DMA_MEM_TO_DEV:
if (config->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) {
dev_err(dma_dev->ddev.dev, "only support 4 byte buswidth\n");
return -EINVAL;
}
chan->fifo_addr = config->dst_addr;
chan->burst_size = gdma_dma_maxburst(config->dst_maxburst);
break;
case DMA_DEV_TO_MEM:
if (config->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) {
dev_err(dma_dev->ddev.dev, "only support 4 byte buswidth\n");
return -EINVAL;
}
chan->fifo_addr = config->src_addr;
chan->burst_size = gdma_dma_maxburst(config->src_maxburst);
break;
default:
dev_err(dma_dev->ddev.dev, "direction type %d error\n",
config->direction);
return -EINVAL;
}
return 0;
}
static int gdma_dma_terminate_all(struct dma_chan *c)
{
struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
unsigned long flags, timeout;
LIST_HEAD(head);
int i = 0;
spin_lock_irqsave(&chan->vchan.lock, flags);
chan->desc = NULL;
clear_bit(chan->id, &dma_dev->chan_issued);
vchan_get_all_descriptors(&chan->vchan, &head);
spin_unlock_irqrestore(&chan->vchan.lock, flags);
vchan_dma_desc_free_list(&chan->vchan, &head);
/* wait dma transfer complete */
timeout = jiffies + msecs_to_jiffies(5000);
while (gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id)) &
GDMA_REG_CTRL0_ENABLE) {
if (time_after_eq(jiffies, timeout)) {
dev_err(dma_dev->ddev.dev, "chan %d wait timeout\n",
chan->id);
/* restore to init value */
gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), 0);
break;
}
cpu_relax();
i++;
}
if (i)
dev_dbg(dma_dev->ddev.dev, "terminate chan %d loops %d\n",
chan->id, i);
return 0;
}
static void rt305x_dump_reg(struct gdma_dma_dev *dma_dev, int id)
{
dev_dbg(dma_dev->ddev.dev, "chan %d, src %08x, dst %08x, ctr0 %08x, ctr1 %08x, intr %08x, signal %08x\n",
id,
gdma_dma_read(dma_dev, GDMA_REG_SRC_ADDR(id)),
gdma_dma_read(dma_dev, GDMA_REG_DST_ADDR(id)),
gdma_dma_read(dma_dev, GDMA_REG_CTRL0(id)),
gdma_dma_read(dma_dev, GDMA_REG_CTRL1(id)),
gdma_dma_read(dma_dev, GDMA_RT305X_STATUS_INT),
gdma_dma_read(dma_dev, GDMA_RT305X_STATUS_SIGNAL));
}
static int rt305x_gdma_start_transfer(struct gdma_dmaengine_chan *chan)
{
struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
dma_addr_t src_addr, dst_addr;
struct gdma_dma_sg *sg;
u32 ctrl0, ctrl1;
/* verify chan is already stopped */
ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) {
dev_err(dma_dev->ddev.dev, "chan %d is start(%08x).\n",
chan->id, ctrl0);
rt305x_dump_reg(dma_dev, chan->id);
return -EINVAL;
}
sg = &chan->desc->sg[chan->next_sg];
if (chan->desc->direction == DMA_MEM_TO_DEV) {
src_addr = sg->src_addr;
dst_addr = chan->fifo_addr;
ctrl0 = GDMA_REG_CTRL0_DST_ADDR_FIXED |
(8 << GDMA_RT305X_CTRL0_SRC_REQ_SHIFT) |
(chan->slave_id << GDMA_RT305X_CTRL0_DST_REQ_SHIFT);
} else if (chan->desc->direction == DMA_DEV_TO_MEM) {
src_addr = chan->fifo_addr;
dst_addr = sg->dst_addr;
ctrl0 = GDMA_REG_CTRL0_SRC_ADDR_FIXED |
(chan->slave_id << GDMA_RT305X_CTRL0_SRC_REQ_SHIFT) |
(8 << GDMA_RT305X_CTRL0_DST_REQ_SHIFT);
} else if (chan->desc->direction == DMA_MEM_TO_MEM) {
/*
* TODO: memcpy function have bugs. sometime it will copy
* more 8 bytes data when using dmatest verify.
*/
src_addr = sg->src_addr;
dst_addr = sg->dst_addr;
ctrl0 = GDMA_REG_CTRL0_SW_MODE |
(8 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) |
(8 << GDMA_REG_CTRL1_DST_REQ_SHIFT);
} else {
dev_err(dma_dev->ddev.dev, "direction type %d error\n",
chan->desc->direction);
return -EINVAL;
}
ctrl0 |= (sg->len << GDMA_REG_CTRL0_TX_SHIFT) |
(chan->burst_size << GDMA_REG_CTRL0_BURST_SHIFT) |
GDMA_REG_CTRL0_DONE_INT | GDMA_REG_CTRL0_ENABLE;
ctrl1 = chan->id << GDMA_REG_CTRL1_NEXT_SHIFT;
chan->next_sg++;
gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr);
gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr);
gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1);
/* make sure next_sg is update */
wmb();
gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0);
return 0;
}
static void rt3883_dump_reg(struct gdma_dma_dev *dma_dev, int id)
{
dev_dbg(dma_dev->ddev.dev, "chan %d, src %08x, dst %08x, ctr0 %08x, ctr1 %08x, unmask %08x, done %08x, req %08x, ack %08x, fin %08x\n",
id,
gdma_dma_read(dma_dev, GDMA_REG_SRC_ADDR(id)),
gdma_dma_read(dma_dev, GDMA_REG_DST_ADDR(id)),
gdma_dma_read(dma_dev, GDMA_REG_CTRL0(id)),
gdma_dma_read(dma_dev, GDMA_REG_CTRL1(id)),
gdma_dma_read(dma_dev, GDMA_REG_UNMASK_INT),
gdma_dma_read(dma_dev, GDMA_REG_DONE_INT),
gdma_dma_read(dma_dev, GDMA_REG_REQSTS),
gdma_dma_read(dma_dev, GDMA_REG_ACKSTS),
gdma_dma_read(dma_dev, GDMA_REG_FINSTS));
}
static int rt3883_gdma_start_transfer(struct gdma_dmaengine_chan *chan)
{
struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
dma_addr_t src_addr, dst_addr;
struct gdma_dma_sg *sg;
u32 ctrl0, ctrl1;
/* verify chan is already stopped */
ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) {
dev_err(dma_dev->ddev.dev, "chan %d is start(%08x).\n",
chan->id, ctrl0);
rt3883_dump_reg(dma_dev, chan->id);
return -EINVAL;
}
sg = &chan->desc->sg[chan->next_sg];
if (chan->desc->direction == DMA_MEM_TO_DEV) {
src_addr = sg->src_addr;
dst_addr = chan->fifo_addr;
ctrl0 = GDMA_REG_CTRL0_DST_ADDR_FIXED;
ctrl1 = (32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) |
(chan->slave_id << GDMA_REG_CTRL1_DST_REQ_SHIFT);
} else if (chan->desc->direction == DMA_DEV_TO_MEM) {
src_addr = chan->fifo_addr;
dst_addr = sg->dst_addr;
ctrl0 = GDMA_REG_CTRL0_SRC_ADDR_FIXED;
ctrl1 = (chan->slave_id << GDMA_REG_CTRL1_SRC_REQ_SHIFT) |
(32 << GDMA_REG_CTRL1_DST_REQ_SHIFT) |
GDMA_REG_CTRL1_COHERENT;
} else if (chan->desc->direction == DMA_MEM_TO_MEM) {
src_addr = sg->src_addr;
dst_addr = sg->dst_addr;
ctrl0 = GDMA_REG_CTRL0_SW_MODE;
ctrl1 = (32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) |
(32 << GDMA_REG_CTRL1_DST_REQ_SHIFT) |
GDMA_REG_CTRL1_COHERENT;
} else {
dev_err(dma_dev->ddev.dev, "direction type %d error\n",
chan->desc->direction);
return -EINVAL;
}
ctrl0 |= (sg->len << GDMA_REG_CTRL0_TX_SHIFT) |
(chan->burst_size << GDMA_REG_CTRL0_BURST_SHIFT) |
GDMA_REG_CTRL0_DONE_INT | GDMA_REG_CTRL0_ENABLE;
ctrl1 |= chan->id << GDMA_REG_CTRL1_NEXT_SHIFT;
chan->next_sg++;
gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr);
gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr);
gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1);
/* make sure next_sg is update */
wmb();
gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0);
return 0;
}
static inline int gdma_start_transfer(struct gdma_dma_dev *dma_dev,
struct gdma_dmaengine_chan *chan)
{
return dma_dev->data->start_transfer(chan);
}
static int gdma_next_desc(struct gdma_dmaengine_chan *chan)
{
struct virt_dma_desc *vdesc;
vdesc = vchan_next_desc(&chan->vchan);
if (!vdesc) {
chan->desc = NULL;
return 0;
}
chan->desc = to_gdma_dma_desc(vdesc);
chan->next_sg = 0;
return 1;
}
static void gdma_dma_chan_irq(struct gdma_dma_dev *dma_dev,
struct gdma_dmaengine_chan *chan)
{
struct gdma_dma_desc *desc;
unsigned long flags;
int chan_issued;
chan_issued = 0;
spin_lock_irqsave(&chan->vchan.lock, flags);
desc = chan->desc;
if (desc) {
if (desc->cyclic) {
vchan_cyclic_callback(&desc->vdesc);
if (chan->next_sg == desc->num_sgs)
chan->next_sg = 0;
chan_issued = 1;
} else {
desc->residue -= desc->sg[chan->next_sg - 1].len;
if (chan->next_sg == desc->num_sgs) {
list_del(&desc->vdesc.node);
vchan_cookie_complete(&desc->vdesc);
chan_issued = gdma_next_desc(chan);
} else {
chan_issued = 1;
}
}
} else {
dev_dbg(dma_dev->ddev.dev, "chan %d no desc to complete\n",
chan->id);
}
if (chan_issued)
set_bit(chan->id, &dma_dev->chan_issued);
spin_unlock_irqrestore(&chan->vchan.lock, flags);
}
static irqreturn_t gdma_dma_irq(int irq, void *devid)
{
struct gdma_dma_dev *dma_dev = devid;
u32 done, done_reg;
unsigned int i;
done_reg = dma_dev->data->done_int_reg;
done = gdma_dma_read(dma_dev, done_reg);
if (unlikely(!done))
return IRQ_NONE;
/* clean done bits */
gdma_dma_write(dma_dev, done_reg, done);
i = 0;
while (done) {
if (done & 0x1) {
gdma_dma_chan_irq(dma_dev, &dma_dev->chan[i]);
atomic_dec(&dma_dev->cnt);
}
done >>= 1;
i++;
}
/* start only have work to do */
if (dma_dev->chan_issued)
tasklet_schedule(&dma_dev->task);
return IRQ_HANDLED;
}
static void gdma_dma_issue_pending(struct dma_chan *c)
{
struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
unsigned long flags;
spin_lock_irqsave(&chan->vchan.lock, flags);
if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
if (gdma_next_desc(chan)) {
set_bit(chan->id, &dma_dev->chan_issued);
tasklet_schedule(&dma_dev->task);
} else {
dev_dbg(dma_dev->ddev.dev, "chan %d no desc to issue\n",
chan->id);
}
}
spin_unlock_irqrestore(&chan->vchan.lock, flags);
}
static struct dma_async_tx_descriptor *gdma_dma_prep_slave_sg(
struct dma_chan *c, struct scatterlist *sgl,
unsigned int sg_len, enum dma_transfer_direction direction,
unsigned long flags, void *context)
{
struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
struct gdma_dma_desc *desc;
struct scatterlist *sg;
unsigned int i;
desc = kzalloc(struct_size(desc, sg, sg_len), GFP_ATOMIC);
if (!desc) {
dev_err(c->device->dev, "alloc sg decs error\n");
return NULL;
}
desc->residue = 0;
for_each_sg(sgl, sg, sg_len, i) {
if (direction == DMA_MEM_TO_DEV) {
desc->sg[i].src_addr = sg_dma_address(sg);
} else if (direction == DMA_DEV_TO_MEM) {
desc->sg[i].dst_addr = sg_dma_address(sg);
} else {
dev_err(c->device->dev, "direction type %d error\n",
direction);
goto free_desc;
}
if (unlikely(sg_dma_len(sg) > GDMA_REG_CTRL0_TX_MASK)) {
dev_err(c->device->dev, "sg len too large %d\n",
sg_dma_len(sg));
goto free_desc;
}
desc->sg[i].len = sg_dma_len(sg);
desc->residue += sg_dma_len(sg);
}
desc->num_sgs = sg_len;
desc->direction = direction;
desc->cyclic = false;
return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
free_desc:
kfree(desc);
return NULL;
}
static struct dma_async_tx_descriptor *gdma_dma_prep_dma_memcpy(
struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
size_t len, unsigned long flags)
{
struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
struct gdma_dma_desc *desc;
unsigned int num_periods, i;
size_t xfer_count;
if (len <= 0)
return NULL;
chan->burst_size = gdma_dma_maxburst(len >> 2);
xfer_count = GDMA_REG_CTRL0_TX_MASK;
num_periods = DIV_ROUND_UP(len, xfer_count);
desc = kzalloc(struct_size(desc, sg, num_periods), GFP_ATOMIC);
if (!desc) {
dev_err(c->device->dev, "alloc memcpy decs error\n");
return NULL;
}
desc->residue = len;
for (i = 0; i < num_periods; i++) {
desc->sg[i].src_addr = src;
desc->sg[i].dst_addr = dest;
if (len > xfer_count)
desc->sg[i].len = xfer_count;
else
desc->sg[i].len = len;
src += desc->sg[i].len;
dest += desc->sg[i].len;
len -= desc->sg[i].len;
}
desc->num_sgs = num_periods;
desc->direction = DMA_MEM_TO_MEM;
desc->cyclic = false;
return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
}
static struct dma_async_tx_descriptor *gdma_dma_prep_dma_cyclic(
struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
size_t period_len, enum dma_transfer_direction direction,
unsigned long flags)
{
struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
struct gdma_dma_desc *desc;
unsigned int num_periods, i;
if (buf_len % period_len)
return NULL;
if (period_len > GDMA_REG_CTRL0_TX_MASK) {
dev_err(c->device->dev, "cyclic len too large %d\n",
period_len);
return NULL;
}
num_periods = buf_len / period_len;
desc = kzalloc(struct_size(desc, sg, num_periods), GFP_ATOMIC);
if (!desc) {
dev_err(c->device->dev, "alloc cyclic decs error\n");
return NULL;
}
desc->residue = buf_len;
for (i = 0; i < num_periods; i++) {
if (direction == DMA_MEM_TO_DEV) {
desc->sg[i].src_addr = buf_addr;
} else if (direction == DMA_DEV_TO_MEM) {
desc->sg[i].dst_addr = buf_addr;
} else {
dev_err(c->device->dev, "direction type %d error\n",
direction);
goto free_desc;
}
desc->sg[i].len = period_len;
buf_addr += period_len;
}
desc->num_sgs = num_periods;
desc->direction = direction;
desc->cyclic = true;
return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
free_desc:
kfree(desc);
return NULL;
}
static enum dma_status gdma_dma_tx_status(struct dma_chan *c,
dma_cookie_t cookie,
struct dma_tx_state *state)
{
struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
struct virt_dma_desc *vdesc;
enum dma_status status;
unsigned long flags;
struct gdma_dma_desc *desc;
status = dma_cookie_status(c, cookie, state);
if (status == DMA_COMPLETE || !state)
return status;
spin_lock_irqsave(&chan->vchan.lock, flags);
desc = chan->desc;
if (desc && (cookie == desc->vdesc.tx.cookie)) {
/*
* We never update edesc->residue in the cyclic case, so we
* can tell the remaining room to the end of the circular
* buffer.
*/
if (desc->cyclic)
state->residue = desc->residue -
((chan->next_sg - 1) * desc->sg[0].len);
else
state->residue = desc->residue;
} else {
vdesc = vchan_find_desc(&chan->vchan, cookie);
if (vdesc)
state->residue = to_gdma_dma_desc(vdesc)->residue;
}
spin_unlock_irqrestore(&chan->vchan.lock, flags);
dev_dbg(c->device->dev, "tx residue %d bytes\n", state->residue);
return status;
}
static void gdma_dma_free_chan_resources(struct dma_chan *c)
{
vchan_free_chan_resources(to_virt_chan(c));
}
static void gdma_dma_desc_free(struct virt_dma_desc *vdesc)
{
kfree(container_of(vdesc, struct gdma_dma_desc, vdesc));
}
static void gdma_dma_tasklet(struct tasklet_struct *t)
{
struct gdma_dma_dev *dma_dev = from_tasklet(dma_dev, t, task);
struct gdma_dmaengine_chan *chan;
static unsigned int last_chan;
unsigned int i, chan_mask;
/* record last chan to round robin all chans */
i = last_chan;
chan_mask = dma_dev->data->chancnt - 1;
do {
/*
* on mt7621. when verify with dmatest with all
* channel is enable. we need to limit only two
* channel is working at the same time. otherwise the
* data will have problem.
*/
if (atomic_read(&dma_dev->cnt) >= 2) {
last_chan = i;
break;
}
if (test_and_clear_bit(i, &dma_dev->chan_issued)) {
chan = &dma_dev->chan[i];
if (chan->desc) {
atomic_inc(&dma_dev->cnt);
gdma_start_transfer(dma_dev, chan);
} else {
dev_dbg(dma_dev->ddev.dev,
"chan %d no desc to issue\n",
chan->id);
}
if (!dma_dev->chan_issued)
break;
}
i = (i + 1) & chan_mask;
} while (i != last_chan);
}
static void rt305x_gdma_init(struct gdma_dma_dev *dma_dev)
{
u32 gct;
/* all chans round robin */
gdma_dma_write(dma_dev, GDMA_RT305X_GCT, GDMA_REG_GCT_ARBIT_RR);
gct = gdma_dma_read(dma_dev, GDMA_RT305X_GCT);
dev_info(dma_dev->ddev.dev, "revision: %d, channels: %d\n",
(gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) &
GDMA_REG_GCT_CHAN_MASK));
}
static void rt3883_gdma_init(struct gdma_dma_dev *dma_dev)
{
u32 gct;
/* all chans round robin */
gdma_dma_write(dma_dev, GDMA_REG_GCT, GDMA_REG_GCT_ARBIT_RR);
gct = gdma_dma_read(dma_dev, GDMA_REG_GCT);
dev_info(dma_dev->ddev.dev, "revision: %d, channels: %d\n",
(gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) &
GDMA_REG_GCT_CHAN_MASK));
}
static struct gdma_data rt305x_gdma_data = {
.chancnt = 8,
.done_int_reg = GDMA_RT305X_STATUS_INT,
.init = rt305x_gdma_init,
.start_transfer = rt305x_gdma_start_transfer,
};
static struct gdma_data rt3883_gdma_data = {
.chancnt = 16,
.done_int_reg = GDMA_REG_DONE_INT,
.init = rt3883_gdma_init,
.start_transfer = rt3883_gdma_start_transfer,
};
static const struct of_device_id gdma_of_match_table[] = {
{ .compatible = "ralink,rt305x-gdma", .data = &rt305x_gdma_data },
{ .compatible = "ralink,rt3883-gdma", .data = &rt3883_gdma_data },
{ },
};
MODULE_DEVICE_TABLE(of, gdma_of_match_table);
static int gdma_dma_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
struct gdma_dmaengine_chan *chan;
struct gdma_dma_dev *dma_dev;
struct dma_device *dd;
unsigned int i;
int ret;
int irq;
void __iomem *base;
struct gdma_data *data;
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
if (ret)
return ret;
match = of_match_device(gdma_of_match_table, &pdev->dev);
if (!match)
return -EINVAL;
data = (struct gdma_data *)match->data;
dma_dev = devm_kzalloc(&pdev->dev,
struct_size(dma_dev, chan, data->chancnt),
GFP_KERNEL);
if (!dma_dev)
return -EINVAL;
dma_dev->data = data;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
dma_dev->base = base;
tasklet_setup(&dma_dev->task, gdma_dma_tasklet);
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return -EINVAL;
ret = devm_request_irq(&pdev->dev, irq, gdma_dma_irq,
0, dev_name(&pdev->dev), dma_dev);
if (ret) {
dev_err(&pdev->dev, "failed to request irq\n");
return ret;
}
ret = device_reset(&pdev->dev);
if (ret)
dev_err(&pdev->dev, "failed to reset: %d\n", ret);
dd = &dma_dev->ddev;
dma_cap_set(DMA_MEMCPY, dd->cap_mask);
dma_cap_set(DMA_SLAVE, dd->cap_mask);
dma_cap_set(DMA_CYCLIC, dd->cap_mask);
dd->device_free_chan_resources = gdma_dma_free_chan_resources;
dd->device_prep_dma_memcpy = gdma_dma_prep_dma_memcpy;
dd->device_prep_slave_sg = gdma_dma_prep_slave_sg;
dd->device_prep_dma_cyclic = gdma_dma_prep_dma_cyclic;
dd->device_config = gdma_dma_config;
dd->device_terminate_all = gdma_dma_terminate_all;
dd->device_tx_status = gdma_dma_tx_status;
dd->device_issue_pending = gdma_dma_issue_pending;
dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
dd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
dd->dev = &pdev->dev;
dd->dev->dma_parms = &dma_dev->dma_parms;
dma_set_max_seg_size(dd->dev, GDMA_REG_CTRL0_TX_MASK);
INIT_LIST_HEAD(&dd->channels);
for (i = 0; i < data->chancnt; i++) {
chan = &dma_dev->chan[i];
chan->id = i;
chan->vchan.desc_free = gdma_dma_desc_free;
vchan_init(&chan->vchan, dd);
}
/* init hardware */
data->init(dma_dev);
ret = dma_async_device_register(dd);
if (ret) {
dev_err(&pdev->dev, "failed to register dma device\n");
return ret;
}
ret = of_dma_controller_register(pdev->dev.of_node,
of_dma_xlate_by_chan_id, dma_dev);
if (ret) {
dev_err(&pdev->dev, "failed to register of dma controller\n");
goto err_unregister;
}
platform_set_drvdata(pdev, dma_dev);
return 0;
err_unregister:
dma_async_device_unregister(dd);
return ret;
}
static int gdma_dma_remove(struct platform_device *pdev)
{
struct gdma_dma_dev *dma_dev = platform_get_drvdata(pdev);
tasklet_kill(&dma_dev->task);
of_dma_controller_free(pdev->dev.of_node);
dma_async_device_unregister(&dma_dev->ddev);
return 0;
}
static struct platform_driver gdma_dma_driver = {
.probe = gdma_dma_probe,
.remove = gdma_dma_remove,
.driver = {
.name = "gdma-rt2880",
.of_match_table = gdma_of_match_table,
},
};
module_platform_driver(gdma_dma_driver);
MODULE_DESCRIPTION("Ralink/MTK DMA driver");
MODULE_LICENSE("GPL v2");

12
target/linux/ramips/files/drivers/mmc/host/mtk-mmc/Kconfig Normal file
View File

@@ -0,0 +1,12 @@
config MTK_MMC
tristate "MTK SD/MMC"
depends on !MTD_NAND_RALINK
config MTK_AEE_KDUMP
bool "MTK AEE KDUMP"
depends on MTK_MMC
config MTK_MMC_CD_POLL
bool "Card Detect with Polling"
depends on MTK_MMC

42
target/linux/ramips/files/drivers/mmc/host/mtk-mmc/Makefile Normal file
View File

@@ -0,0 +1,42 @@
# Copyright Statement:
#
# This software/firmware and related documentation ("MediaTek Software") are
# protected under relevant copyright laws. The information contained herein
# is confidential and proprietary to MediaTek Inc. and/or its licensors.
# Without the prior written permission of MediaTek inc. and/or its licensors,
# any reproduction, modification, use or disclosure of MediaTek Software,
# and information contained herein, in whole or in part, shall be strictly prohibited.
#
# MediaTek Inc. (C) 2010. All rights reserved.
#
# BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
# THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
# CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
# SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
# STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
# CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
#
# The following software/firmware and/or related documentation ("MediaTek Software")
# have been modified by MediaTek Inc. All revisions are subject to any receiver's
# applicable license agreements with MediaTek Inc.
obj-$(CONFIG_MTK_MMC) += mtk_sd.o
mtk_sd-objs := sd.o dbg.o
ifeq ($(CONFIG_MTK_AEE_KDUMP),y)
EXTRA_CFLAGS += -DMT6575_SD_DEBUG
endif
clean:
@rm -f *.o modules.order .*.cmd

63
target/linux/ramips/files/drivers/mmc/host/mtk-mmc/board.h Normal file
View File

@@ -0,0 +1,63 @@
/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*/
/* MediaTek Inc. (C) 2010. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* The following software/firmware and/or related documentation ("MediaTek Software")
* have been modified by MediaTek Inc. All revisions are subject to any receiver's
* applicable license agreements with MediaTek Inc.
*/
#ifndef __ARCH_ARM_MACH_BOARD_H
#define __ARCH_ARM_MACH_BOARD_H
#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
#define MSDC_RST_PIN_EN (1 << 2) /* emmc reset pin is wired */
#define MSDC_REMOVABLE (1 << 5) /* removable slot */
#define MSDC_SMPL_RISING (0)
#define MSDC_SMPL_FALLING (1)
#define MSDC_CMD_PIN (0)
#define MSDC_DAT_PIN (1)
#define MSDC_CD_PIN (2)
#define MSDC_WP_PIN (3)
#define MSDC_RST_PIN (4)
struct msdc_hw {
unsigned char clk_src; /* host clock source */
unsigned long flags; /* hardware capability flags */
/* config gpio pull mode */
void (*config_gpio_pin)(int type, int pull);
};
extern struct msdc_hw msdc0_hw;
#endif /* __ARCH_ARM_MACH_BOARD_H */

307
target/linux/ramips/files/drivers/mmc/host/mtk-mmc/dbg.c Normal file
View File

@@ -0,0 +1,307 @@
/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*
* MediaTek Inc. (C) 2010. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* The following software/firmware and/or related documentation ("MediaTek Software")
* have been modified by MediaTek Inc. All revisions are subject to any receiver's
* applicable license agreements with MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/kthread.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/proc_fs.h>
#include <linux/string.h>
#include <linux/uaccess.h>
// #include <mach/mt6575_gpt.h> /* --- by chhung */
#include "dbg.h"
#include "mt6575_sd.h"
#include <linux/seq_file.h>
/* for debug zone */
unsigned int sd_debug_zone[4] = {
0,
0,
0,
0
};
#if defined(MT6575_SD_DEBUG)
static char cmd_buf[256];
/* for driver profile */
#define TICKS_ONE_MS (13000)
u32 gpt_enable;
u32 sdio_pro_enable; /* make sure gpt is enabled */
u32 sdio_pro_time; /* no more than 30s */
struct sdio_profile sdio_perfomance = {0};
#if 0 /* --- chhung */
void msdc_init_gpt(void)
{
GPT_CONFIG config;
config.num = GPT6;
config.mode = GPT_FREE_RUN;
config.clkSrc = GPT_CLK_SRC_SYS;
config.clkDiv = GPT_CLK_DIV_1; /* 13MHz GPT6 */
if (GPT_Config(config) == FALSE)
return;
GPT_Start(GPT6);
}
#endif /* end of --- */
u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32)
{
u32 ret = 0;
if (new_H32 == old_H32) {
ret = new_L32 - old_L32;
} else if (new_H32 == (old_H32 + 1)) {
if (new_L32 > old_L32)
printk("msdc old_L<0x%x> new_L<0x%x>\n", old_L32, new_L32);
ret = (0xffffffff - old_L32);
ret += new_L32;
} else {
printk("msdc old_H<0x%x> new_H<0x%x>\n", old_H32, new_H32);
}
return ret;
}
void msdc_sdio_profile(struct sdio_profile *result)
{
struct cmd_profile *cmd;
u32 i;
printk("sdio === performance dump ===\n");
printk("sdio === total execute tick<%d> time<%dms> Tx<%dB> Rx<%dB>\n",
result->total_tc, result->total_tc / TICKS_ONE_MS,
result->total_tx_bytes, result->total_rx_bytes);
/* CMD52 Dump */
cmd = &result->cmd52_rx;
printk("sdio === CMD52 Rx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count);
cmd = &result->cmd52_tx;
printk("sdio === CMD52 Tx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count);
/* CMD53 Rx bytes + block mode */
for (i = 0; i < 512; i++) {
cmd = &result->cmd53_rx_byte[i];
if (cmd->count) {
printk("sdio<%6d><%3dB>_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
}
}
for (i = 0; i < 100; i++) {
cmd = &result->cmd53_rx_blk[i];
if (cmd->count) {
printk("sdio<%6d><%3d>B_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
}
}
/* CMD53 Tx bytes + block mode */
for (i = 0; i < 512; i++) {
cmd = &result->cmd53_tx_byte[i];
if (cmd->count) {
printk("sdio<%6d><%3dB>_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
}
}
for (i = 0; i < 100; i++) {
cmd = &result->cmd53_tx_blk[i];
if (cmd->count) {
printk("sdio<%6d><%3d>B_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
}
}
printk("sdio === performance dump done ===\n");
}
//========= sdio command table ===========
void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)
{
struct sdio_profile *result = &sdio_perfomance;
struct cmd_profile *cmd;
u32 block;
if (sdio_pro_enable == 0)
return;
if (opcode == 52) {
cmd = bRx ? &result->cmd52_rx : &result->cmd52_tx;
} else if (opcode == 53) {
if (sizes < 512) {
cmd = bRx ? &result->cmd53_rx_byte[sizes] : &result->cmd53_tx_byte[sizes];
} else {
block = sizes / 512;
if (block >= 99) {
printk("cmd53 error blocks\n");
while (1)
;
}
cmd = bRx ? &result->cmd53_rx_blk[block] : &result->cmd53_tx_blk[block];
}
} else {
return;
}
/* update the members */
if (ticks > cmd->max_tc)
cmd->max_tc = ticks;
if (cmd->min_tc == 0 || ticks < cmd->min_tc)
cmd->min_tc = ticks;
cmd->tot_tc += ticks;
cmd->tot_bytes += sizes;
cmd->count++;
if (bRx)
result->total_rx_bytes += sizes;
else
result->total_tx_bytes += sizes;
result->total_tc += ticks;
/* dump when total_tc > 30s */
if (result->total_tc >= sdio_pro_time * TICKS_ONE_MS * 1000) {
msdc_sdio_profile(result);
memset(result, 0, sizeof(struct sdio_profile));
}
}
//========== driver proc interface ===========
static int msdc_debug_proc_read(struct seq_file *s, void *p)
{
seq_puts(s, "\n=========================================\n");
seq_puts(s, "Index<0> + Id + Zone\n");
seq_puts(s, "-> PWR<9> WRN<8> | FIO<7> OPS<6> FUN<5> CFG<4> | INT<3> RSP<2> CMD<1> DMA<0>\n");
seq_puts(s, "-> echo 0 3 0x3ff >msdc_bebug -> host[3] debug zone set to 0x3ff\n");
seq_printf(s, "-> MSDC[0] Zone: 0x%.8x\n", sd_debug_zone[0]);
seq_printf(s, "-> MSDC[1] Zone: 0x%.8x\n", sd_debug_zone[1]);
seq_printf(s, "-> MSDC[2] Zone: 0x%.8x\n", sd_debug_zone[2]);
seq_printf(s, "-> MSDC[3] Zone: 0x%.8x\n", sd_debug_zone[3]);
seq_puts(s, "Index<3> + SDIO_PROFILE + TIME\n");
seq_puts(s, "-> echo 3 1 0x1E >msdc_bebug -> enable sdio_profile, 30s\n");
seq_printf(s, "-> SDIO_PROFILE<%d> TIME<%ds>\n", sdio_pro_enable, sdio_pro_time);
seq_puts(s, "=========================================\n\n");
return 0;
}
static ssize_t msdc_debug_proc_write(struct file *file,
const char __user *buf, size_t count, loff_t *data)
{
int ret;
int cmd, p1, p2;
int id, zone;
int mode, size;
if (count == 0)
return -1;
if (count > 255)
count = 255;
if (copy_from_user(cmd_buf, buf, count))
return -EFAULT;
cmd_buf[count] = '\0';
printk("msdc Write %s\n", cmd_buf);
sscanf(cmd_buf, "%x %x %x", &cmd, &p1, &p2);
if (cmd == SD_TOOL_ZONE) {
id = p1;
zone = p2;
zone &= 0x3ff;
printk("msdc host_id<%d> zone<0x%.8x>\n", id, zone);
if (id >= 0 && id <= 3) {
sd_debug_zone[id] = zone;
} else if (id == 4) {
sd_debug_zone[0] = sd_debug_zone[1] = zone;
sd_debug_zone[2] = sd_debug_zone[3] = zone;
} else {
printk("msdc host_id error when set debug zone\n");
}
} else if (cmd == SD_TOOL_SDIO_PROFILE) {
if (p1 == 1) { /* enable profile */
if (gpt_enable == 0) {
// msdc_init_gpt(); /* --- by chhung */
gpt_enable = 1;
}
sdio_pro_enable = 1;
if (p2 == 0)
p2 = 1;
if (p2 >= 30)
p2 = 30;
sdio_pro_time = p2;
} else if (p1 == 0) {
/* todo */
sdio_pro_enable = 0;
}
}
return count;
}
static int msdc_debug_show(struct inode *inode, struct file *file)
{
return single_open(file, msdc_debug_proc_read, NULL);
}
static const struct file_operations msdc_debug_fops = {
.owner = THIS_MODULE,
.open = msdc_debug_show,
.read = seq_read,
.write = msdc_debug_proc_write,
.llseek = seq_lseek,
.release = single_release,
};
void msdc_debug_proc_init(void)
{
proc_create("msdc_debug", 0660, NULL, &msdc_debug_fops);
}
EXPORT_SYMBOL_GPL(msdc_debug_proc_init);
#endif

155
target/linux/ramips/files/drivers/mmc/host/mtk-mmc/dbg.h Normal file
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@@ -0,0 +1,155 @@
/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*
* MediaTek Inc. (C) 2010. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* The following software/firmware and/or related documentation ("MediaTek Software")
* have been modified by MediaTek Inc. All revisions are subject to any receiver's
* applicable license agreements with MediaTek Inc.
*/
#ifndef __MT_MSDC_DEUBG__
#define __MT_MSDC_DEUBG__
//==========================
extern u32 sdio_pro_enable;
/* for a type command, e.g. CMD53, 2 blocks */
struct cmd_profile {
u32 max_tc; /* Max tick count */
u32 min_tc;
u32 tot_tc; /* total tick count */
u32 tot_bytes;
u32 count; /* the counts of the command */
};
/* dump when total_tc and total_bytes */
struct sdio_profile {
u32 total_tc; /* total tick count of CMD52 and CMD53 */
u32 total_tx_bytes; /* total bytes of CMD53 Tx */
u32 total_rx_bytes; /* total bytes of CMD53 Rx */
/*CMD52*/
struct cmd_profile cmd52_tx;
struct cmd_profile cmd52_rx;
/*CMD53 in byte unit */
struct cmd_profile cmd53_tx_byte[512];
struct cmd_profile cmd53_rx_byte[512];
/*CMD53 in block unit */
struct cmd_profile cmd53_tx_blk[100];
struct cmd_profile cmd53_rx_blk[100];
};
//==========================
enum msdc_dbg {
SD_TOOL_ZONE = 0,
SD_TOOL_DMA_SIZE = 1,
SD_TOOL_PM_ENABLE = 2,
SD_TOOL_SDIO_PROFILE = 3,
};
enum msdc_mode {
MODE_PIO = 0,
MODE_DMA = 1,
MODE_SIZE_DEP = 2,
};
/* Debug message event */
#define DBG_EVT_NONE (0) /* No event */
#define DBG_EVT_DMA (1 << 0) /* DMA related event */
#define DBG_EVT_CMD (1 << 1) /* MSDC CMD related event */
#define DBG_EVT_RSP (1 << 2) /* MSDC CMD RSP related event */
#define DBG_EVT_INT (1 << 3) /* MSDC INT event */
#define DBG_EVT_CFG (1 << 4) /* MSDC CFG event */
#define DBG_EVT_FUC (1 << 5) /* Function event */
#define DBG_EVT_OPS (1 << 6) /* Read/Write operation event */
#define DBG_EVT_FIO (1 << 7) /* FIFO operation event */
#define DBG_EVT_WRN (1 << 8) /* Warning event */
#define DBG_EVT_PWR (1 << 9) /* Power event */
#define DBG_EVT_ALL (0xffffffff)
#define DBG_EVT_MASK (DBG_EVT_ALL)
extern unsigned int sd_debug_zone[4];
#define TAG "msdc"
#if 0 /* +++ chhung */
#define BUG_ON(x) \
do { \
if (x) { \
printk("[BUG] %s LINE:%d FILE:%s\n", #x, __LINE__, __FILE__); \
while (1) \
; \
} \
} while (0)
#endif /* end of +++ */
#define N_MSG(evt, fmt, args...)
/*
do { \
if ((DBG_EVT_##evt) & sd_debug_zone[host->id]) { \
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
} \
} while(0)
*/
#define ERR_MSG(fmt, args...) \
do { \
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
host->id, ##args, __FUNCTION__, __LINE__, current->comm, current->pid); \
} while (0);
#if 1
//defined CONFIG_MTK_MMC_CD_POLL
#define INIT_MSG(fmt, args...)
#define IRQ_MSG(fmt, args...)
#else
#define INIT_MSG(fmt, args...) \
do { \
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
host->id, ##args, __FUNCTION__, __LINE__, current->comm, current->pid); \
} while (0);
/* PID in ISR in not corrent */
#define IRQ_MSG(fmt, args...) \
do { \
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d>\n", \
host->id, ##args, __FUNCTION__, __LINE__); \
} while (0);
#endif
void msdc_debug_proc_init(void);
#if 0 /* --- chhung */
void msdc_init_gpt(void);
extern void GPT_GetCounter64(UINT32 *cntL32, UINT32 *cntH32);
#endif /* end of --- */
u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32);
void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks);
#endif

986
target/linux/ramips/files/drivers/mmc/host/mtk-mmc/mt6575_sd.h Normal file
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@@ -0,0 +1,986 @@
/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*/
/* MediaTek Inc. (C) 2010. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* The following software/firmware and/or related documentation ("MediaTek Software")
* have been modified by MediaTek Inc. All revisions are subject to any receiver's
* applicable license agreements with MediaTek Inc.
*/
#ifndef MT6575_SD_H
#define MT6575_SD_H
#include <linux/bitops.h>
#include <linux/mmc/host.h>
// #include <mach/mt6575_reg_base.h> /* --- by chhung */
/*--------------------------------------------------------------------------*/
/* Common Macro */
/*--------------------------------------------------------------------------*/
#define REG_ADDR(x) (base + OFFSET_##x)
/*--------------------------------------------------------------------------*/
/* Common Definition */
/*--------------------------------------------------------------------------*/
#define MSDC_FIFO_SZ (128)
#define MSDC_FIFO_THD (64) // (128)
#define MSDC_NUM (4)
#define MSDC_MS (0)
#define MSDC_SDMMC (1)
#define MSDC_MODE_UNKNOWN (0)
#define MSDC_MODE_PIO (1)
#define MSDC_MODE_DMA_BASIC (2)
#define MSDC_MODE_DMA_DESC (3)
#define MSDC_MODE_DMA_ENHANCED (4)
#define MSDC_MODE_MMC_STREAM (5)
#define MSDC_BUS_1BITS (0)
#define MSDC_BUS_4BITS (1)
#define MSDC_BUS_8BITS (2)
#define MSDC_BRUST_8B (3)
#define MSDC_BRUST_16B (4)
#define MSDC_BRUST_32B (5)
#define MSDC_BRUST_64B (6)
#define MSDC_PIN_PULL_NONE (0)
#define MSDC_PIN_PULL_DOWN (1)
#define MSDC_PIN_PULL_UP (2)
#define MSDC_PIN_KEEP (3)
#define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
#define MSDC_MIN_SCLK (260000)
#define MSDC_AUTOCMD12 (0x0001)
#define MSDC_AUTOCMD23 (0x0002)
#define MSDC_AUTOCMD19 (0x0003)
#define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
#define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
enum {
RESP_NONE = 0,
RESP_R1,
RESP_R2,
RESP_R3,
RESP_R4,
RESP_R5,
RESP_R6,
RESP_R7,
RESP_R1B
};
/*--------------------------------------------------------------------------*/
/* Register Offset */
/*--------------------------------------------------------------------------*/
#define OFFSET_MSDC_CFG (0x0)
#define OFFSET_MSDC_IOCON (0x04)
#define OFFSET_MSDC_PS (0x08)
#define OFFSET_MSDC_INT (0x0c)
#define OFFSET_MSDC_INTEN (0x10)
#define OFFSET_MSDC_FIFOCS (0x14)
#define OFFSET_MSDC_TXDATA (0x18)
#define OFFSET_MSDC_RXDATA (0x1c)
#define OFFSET_SDC_CFG (0x30)
#define OFFSET_SDC_CMD (0x34)
#define OFFSET_SDC_ARG (0x38)
#define OFFSET_SDC_STS (0x3c)
#define OFFSET_SDC_RESP0 (0x40)
#define OFFSET_SDC_RESP1 (0x44)
#define OFFSET_SDC_RESP2 (0x48)
#define OFFSET_SDC_RESP3 (0x4c)
#define OFFSET_SDC_BLK_NUM (0x50)
#define OFFSET_SDC_CSTS (0x58)
#define OFFSET_SDC_CSTS_EN (0x5c)
#define OFFSET_SDC_DCRC_STS (0x60)
#define OFFSET_EMMC_CFG0 (0x70)
#define OFFSET_EMMC_CFG1 (0x74)
#define OFFSET_EMMC_STS (0x78)
#define OFFSET_EMMC_IOCON (0x7c)
#define OFFSET_SDC_ACMD_RESP (0x80)
#define OFFSET_SDC_ACMD19_TRG (0x84)
#define OFFSET_SDC_ACMD19_STS (0x88)
#define OFFSET_MSDC_DMA_SA (0x90)
#define OFFSET_MSDC_DMA_CA (0x94)
#define OFFSET_MSDC_DMA_CTRL (0x98)
#define OFFSET_MSDC_DMA_CFG (0x9c)
#define OFFSET_MSDC_DBG_SEL (0xa0)
#define OFFSET_MSDC_DBG_OUT (0xa4)
#define OFFSET_MSDC_PATCH_BIT (0xb0)
#define OFFSET_MSDC_PATCH_BIT1 (0xb4)
#define OFFSET_MSDC_PAD_CTL0 (0xe0)
#define OFFSET_MSDC_PAD_CTL1 (0xe4)
#define OFFSET_MSDC_PAD_CTL2 (0xe8)
#define OFFSET_MSDC_PAD_TUNE (0xec)
#define OFFSET_MSDC_DAT_RDDLY0 (0xf0)
#define OFFSET_MSDC_DAT_RDDLY1 (0xf4)
#define OFFSET_MSDC_HW_DBG (0xf8)
#define OFFSET_MSDC_VERSION (0x100)
#define OFFSET_MSDC_ECO_VER (0x104)
/*--------------------------------------------------------------------------*/
/* Register Address */
/*--------------------------------------------------------------------------*/
/* common register */
#define MSDC_CFG REG_ADDR(MSDC_CFG)
#define MSDC_IOCON REG_ADDR(MSDC_IOCON)
#define MSDC_PS REG_ADDR(MSDC_PS)
#define MSDC_INT REG_ADDR(MSDC_INT)
#define MSDC_INTEN REG_ADDR(MSDC_INTEN)
#define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
#define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
#define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
#define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT)
/* sdmmc register */
#define SDC_CFG REG_ADDR(SDC_CFG)
#define SDC_CMD REG_ADDR(SDC_CMD)
#define SDC_ARG REG_ADDR(SDC_ARG)
#define SDC_STS REG_ADDR(SDC_STS)
#define SDC_RESP0 REG_ADDR(SDC_RESP0)
#define SDC_RESP1 REG_ADDR(SDC_RESP1)
#define SDC_RESP2 REG_ADDR(SDC_RESP2)
#define SDC_RESP3 REG_ADDR(SDC_RESP3)
#define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
#define SDC_CSTS REG_ADDR(SDC_CSTS)
#define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
#define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
/* emmc register*/
#define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
#define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
#define EMMC_STS REG_ADDR(EMMC_STS)
#define EMMC_IOCON REG_ADDR(EMMC_IOCON)
/* auto command register */
#define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
#define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
#define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
/* dma register */
#define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
#define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
#define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
#define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
/* pad ctrl register */
#define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0)
#define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1)
#define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2)
/* data read delay */
#define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
#define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
/* debug register */
#define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
#define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
/* misc register */
#define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT)
#define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
#define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE)
#define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
#define MSDC_VERSION REG_ADDR(MSDC_VERSION)
#define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */
/*--------------------------------------------------------------------------*/
/* Register Mask */
/*--------------------------------------------------------------------------*/
/* MSDC_CFG mask */
#define MSDC_CFG_MODE (0x1 << 0) /* RW */
#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
#define MSDC_CFG_RST (0x1 << 2) /* RW */
#define MSDC_CFG_PIO (0x1 << 3) /* RW */
#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
/* MSDC_IOCON mask */
#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
/* MSDC_PS mask */
#define MSDC_PS_CDEN (0x1 << 0) /* RW */
#define MSDC_PS_CDSTS (0x1 << 1) /* R */
#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
#define MSDC_PS_DAT (0xff << 16) /* R */
#define MSDC_PS_CMD (0x1 << 24) /* R */
#define MSDC_PS_WP (0x1UL << 31) /* R */
/* MSDC_INT mask */
#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
#define MSDC_INT_CSTA (0x1 << 11) /* R */
#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
/* MSDC_INTEN mask */
#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
/* MSDC_FIFOCS mask */
#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
#define MSDC_FIFOCS_CLR (0x1UL << 31) /* RW */
/* SDC_CFG mask */
#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
#define SDC_CFG_SDIO (0x1 << 19) /* RW */
#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
#define SDC_CFG_DTOC (0xffUL << 24) /* RW */
/* SDC_CMD mask */
#define SDC_CMD_OPC (0x3f << 0) /* RW */
#define SDC_CMD_BRK (0x1 << 6) /* RW */
#define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
#define SDC_CMD_DTYP (0x3 << 11) /* RW */
#define SDC_CMD_DTYP (0x3 << 11) /* RW */
#define SDC_CMD_RW (0x1 << 13) /* RW */
#define SDC_CMD_STOP (0x1 << 14) /* RW */
#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
#define SDC_CMD_BLKLEN (0xfff << 16) /* RW */
#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
/* SDC_STS mask */
#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
/* SDC_DCRC_STS mask */
#define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
#define SDC_DCRC_STS_POS (0xff << 0) /* RO */
/* EMMC_CFG0 mask */
#define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
#define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
#define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
#define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
#define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
#define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
/* EMMC_CFG1 mask */
#define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
#define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
/* EMMC_STS mask */
#define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
#define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
#define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
#define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
#define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
#define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
#define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
/* EMMC_IOCON mask */
#define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
/* SDC_ACMD19_TRG mask */
#define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
/* MSDC_DMA_CTRL mask */
#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
#define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
/* MSDC_DMA_CFG mask */
#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
#define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
#define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
/* MSDC_PATCH_BIT mask */
#define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
#define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
/* MSDC_PATCH_BIT1 mask */
#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
/* MSDC_PAD_CTL0 mask */
#define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
#define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
#define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
#define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
#define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL << 24) /* RW */
/* MSDC_PAD_CTL1 mask */
#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
#define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
#define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
#define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
#define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL << 24) /* RW */
/* MSDC_PAD_CTL2 mask */
#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
#define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
#define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
#define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
#define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
#define MSDC_PAD_CTL2_DATRDSEL (0xffUL << 24) /* RW */
/* MSDC_PAD_TUNE mask */
#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
#define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
#define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
#define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
#define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
/* MSDC_DAT_RDDLY0/1 mask */
#define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
#define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
#define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
#define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
#define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
#define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F << 10)
#define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
#define MSDC_CKGEN_MSDC_CK_SEL (0x1 << 6)
#define CARD_READY_FOR_DATA (1 << 8)
#define CARD_CURRENT_STATE(x) ((x & 0x00001E00) >> 9)
/*--------------------------------------------------------------------------*/
/* Descriptor Structure */
/*--------------------------------------------------------------------------*/
struct gpd {
u32 hwo:1; /* could be changed by hw */
u32 bdp:1;
u32 rsv0:6;
u32 chksum:8;
u32 intr:1;
u32 rsv1:15;
void *next;
void *ptr;
u32 buflen:16;
u32 extlen:8;
u32 rsv2:8;
u32 arg;
u32 blknum;
u32 cmd;
};
struct bd {
u32 eol:1;
u32 rsv0:7;
u32 chksum:8;
u32 rsv1:1;
u32 blkpad:1;
u32 dwpad:1;
u32 rsv2:13;
void *next;
void *ptr;
u32 buflen:16;
u32 rsv3:16;
};
/*--------------------------------------------------------------------------*/
/* Register Debugging Structure */
/*--------------------------------------------------------------------------*/
struct msdc_cfg_reg {
u32 msdc:1;
u32 ckpwn:1;
u32 rst:1;
u32 pio:1;
u32 ckdrven:1;
u32 start18v:1;
u32 pass18v:1;
u32 ckstb:1;
u32 ckdiv:8;
u32 ckmod:2;
u32 pad:14;
};
struct msdc_iocon_reg {
u32 sdr104cksel:1;
u32 rsmpl:1;
u32 dsmpl:1;
u32 ddlysel:1;
u32 ddr50ckd:1;
u32 dsplsel:1;
u32 pad1:10;
u32 d0spl:1;
u32 d1spl:1;
u32 d2spl:1;
u32 d3spl:1;
u32 d4spl:1;
u32 d5spl:1;
u32 d6spl:1;
u32 d7spl:1;
u32 riscsz:1;
u32 pad2:7;
};
struct msdc_ps_reg {
u32 cden:1;
u32 cdsts:1;
u32 pad1:10;
u32 cddebounce:4;
u32 dat:8;
u32 cmd:1;
u32 pad2:6;
u32 wp:1;
};
struct msdc_int_reg {
u32 mmcirq:1;
u32 cdsc:1;
u32 pad1:1;
u32 atocmdrdy:1;
u32 atocmdtmo:1;
u32 atocmdcrc:1;
u32 dmaqempty:1;
u32 sdioirq:1;
u32 cmdrdy:1;
u32 cmdtmo:1;
u32 rspcrc:1;
u32 csta:1;
u32 xfercomp:1;
u32 dxferdone:1;
u32 dattmo:1;
u32 datcrc:1;
u32 atocmd19done:1;
u32 pad2:15;
};
struct msdc_inten_reg {
u32 mmcirq:1;
u32 cdsc:1;
u32 pad1:1;
u32 atocmdrdy:1;
u32 atocmdtmo:1;
u32 atocmdcrc:1;
u32 dmaqempty:1;
u32 sdioirq:1;
u32 cmdrdy:1;
u32 cmdtmo:1;
u32 rspcrc:1;
u32 csta:1;
u32 xfercomp:1;
u32 dxferdone:1;
u32 dattmo:1;
u32 datcrc:1;
u32 atocmd19done:1;
u32 pad2:15;
};
struct msdc_fifocs_reg {
u32 rxcnt:8;
u32 pad1:8;
u32 txcnt:8;
u32 pad2:7;
u32 clr:1;
};
struct msdc_txdat_reg {
u32 val;
};
struct msdc_rxdat_reg {
u32 val;
};
struct sdc_cfg_reg {
u32 sdiowkup:1;
u32 inswkup:1;
u32 pad1:14;
u32 buswidth:2;
u32 pad2:1;
u32 sdio:1;
u32 sdioide:1;
u32 intblkgap:1;
u32 pad4:2;
u32 dtoc:8;
};
struct sdc_cmd_reg {
u32 cmd:6;
u32 brk:1;
u32 rsptyp:3;
u32 pad1:1;
u32 dtype:2;
u32 rw:1;
u32 stop:1;
u32 goirq:1;
u32 blklen:12;
u32 atocmd:2;
u32 volswth:1;
u32 pad2:1;
};
struct sdc_arg_reg {
u32 arg;
};
struct sdc_sts_reg {
u32 sdcbusy:1;
u32 cmdbusy:1;
u32 pad:29;
u32 swrcmpl:1;
};
struct sdc_resp0_reg {
u32 val;
};
struct sdc_resp1_reg {
u32 val;
};
struct sdc_resp2_reg {
u32 val;
};
struct sdc_resp3_reg {
u32 val;
};
struct sdc_blknum_reg {
u32 num;
};
struct sdc_csts_reg {
u32 sts;
};
struct sdc_cstsen_reg {
u32 sts;
};
struct sdc_datcrcsts_reg {
u32 datcrcsts:8;
u32 ddrcrcsts:4;
u32 pad:20;
};
struct emmc_cfg0_reg {
u32 bootstart:1;
u32 bootstop:1;
u32 bootmode:1;
u32 pad1:9;
u32 bootwaidly:3;
u32 bootsupp:1;
u32 pad2:16;
};
struct emmc_cfg1_reg {
u32 bootcrctmc:16;
u32 pad:4;
u32 bootacktmc:12;
};
struct emmc_sts_reg {
u32 bootcrcerr:1;
u32 bootackerr:1;
u32 bootdattmo:1;
u32 bootacktmo:1;
u32 bootupstate:1;
u32 bootackrcv:1;
u32 bootdatrcv:1;
u32 pad:25;
};
struct emmc_iocon_reg {
u32 bootrst:1;
u32 pad:31;
};
struct msdc_acmd_resp_reg {
u32 val;
};
struct msdc_acmd19_trg_reg {
u32 tunesel:4;
u32 pad:28;
};
struct msdc_acmd19_sts_reg {
u32 val;
};
struct msdc_dma_sa_reg {
u32 addr;
};
struct msdc_dma_ca_reg {
u32 addr;
};
struct msdc_dma_ctrl_reg {
u32 start:1;
u32 stop:1;
u32 resume:1;
u32 pad1:5;
u32 mode:1;
u32 pad2:1;
u32 lastbuf:1;
u32 pad3:1;
u32 brustsz:3;
u32 pad4:1;
u32 xfersz:16;
};
struct msdc_dma_cfg_reg {
u32 status:1;
u32 decsen:1;
u32 pad1:2;
u32 bdcsen:1;
u32 gpdcsen:1;
u32 pad2:26;
};
struct msdc_dbg_sel_reg {
u32 sel:16;
u32 pad2:16;
};
struct msdc_dbg_out_reg {
u32 val;
};
struct msdc_pad_ctl0_reg {
u32 clkdrvn:3;
u32 rsv0:1;
u32 clkdrvp:3;
u32 rsv1:1;
u32 clksr:1;
u32 rsv2:7;
u32 clkpd:1;
u32 clkpu:1;
u32 clksmt:1;
u32 clkies:1;
u32 clktdsel:4;
u32 clkrdsel:8;
};
struct msdc_pad_ctl1_reg {
u32 cmddrvn:3;
u32 rsv0:1;
u32 cmddrvp:3;
u32 rsv1:1;
u32 cmdsr:1;
u32 rsv2:7;
u32 cmdpd:1;
u32 cmdpu:1;
u32 cmdsmt:1;
u32 cmdies:1;
u32 cmdtdsel:4;
u32 cmdrdsel:8;
};
struct msdc_pad_ctl2_reg {
u32 datdrvn:3;
u32 rsv0:1;
u32 datdrvp:3;
u32 rsv1:1;
u32 datsr:1;
u32 rsv2:7;
u32 datpd:1;
u32 datpu:1;
u32 datsmt:1;
u32 daties:1;
u32 dattdsel:4;
u32 datrdsel:8;
};
struct msdc_pad_tune_reg {
u32 wrrxdly:3;
u32 pad1:5;
u32 rdrxdly:8;
u32 pad2:16;
};
struct msdc_dat_rddly0 {
u32 dat0:5;
u32 rsv0:3;
u32 dat1:5;
u32 rsv1:3;
u32 dat2:5;
u32 rsv2:3;
u32 dat3:5;
u32 rsv3:3;
};
struct msdc_dat_rddly1 {
u32 dat4:5;
u32 rsv4:3;
u32 dat5:5;
u32 rsv5:3;
u32 dat6:5;
u32 rsv6:3;
u32 dat7:5;
u32 rsv7:3;
};
struct msdc_hw_dbg_reg {
u32 dbg0sel:8;
u32 dbg1sel:6;
u32 pad1:2;
u32 dbg2sel:6;
u32 pad2:2;
u32 dbg3sel:6;
u32 pad3:2;
};
struct msdc_version_reg {
u32 val;
};
struct msdc_eco_ver_reg {
u32 val;
};
struct msdc_regs {
struct msdc_cfg_reg msdc_cfg; /* base+0x00h */
struct msdc_iocon_reg msdc_iocon; /* base+0x04h */
struct msdc_ps_reg msdc_ps; /* base+0x08h */
struct msdc_int_reg msdc_int; /* base+0x0ch */
struct msdc_inten_reg msdc_inten; /* base+0x10h */
struct msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
struct msdc_txdat_reg msdc_txdat; /* base+0x18h */
struct msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
u32 rsv1[4];
struct sdc_cfg_reg sdc_cfg; /* base+0x30h */
struct sdc_cmd_reg sdc_cmd; /* base+0x34h */
struct sdc_arg_reg sdc_arg; /* base+0x38h */
struct sdc_sts_reg sdc_sts; /* base+0x3ch */
struct sdc_resp0_reg sdc_resp0; /* base+0x40h */
struct sdc_resp1_reg sdc_resp1; /* base+0x44h */
struct sdc_resp2_reg sdc_resp2; /* base+0x48h */
struct sdc_resp3_reg sdc_resp3; /* base+0x4ch */
struct sdc_blknum_reg sdc_blknum; /* base+0x50h */
u32 rsv2[1];
struct sdc_csts_reg sdc_csts; /* base+0x58h */
struct sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
struct sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
u32 rsv3[3];
struct emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
struct emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
struct emmc_sts_reg emmc_sts; /* base+0x78h */
struct emmc_iocon_reg emmc_iocon; /* base+0x7ch */
struct msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
struct msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
struct msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
u32 rsv4[1];
struct msdc_dma_sa_reg dma_sa; /* base+0x90h */
struct msdc_dma_ca_reg dma_ca; /* base+0x94h */
struct msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
struct msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
struct msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
struct msdc_dbg_out_reg dbg_out; /* base+0xa4h */
u32 rsv5[2];
u32 patch0; /* base+0xb0h */
u32 patch1; /* base+0xb4h */
u32 rsv6[10];
struct msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
struct msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
struct msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
struct msdc_pad_tune_reg pad_tune; /* base+0xech */
struct msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
struct msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
struct msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
u32 rsv7[1];
struct msdc_version_reg version; /* base+0x100h */
struct msdc_eco_ver_reg eco_ver; /* base+0x104h */
};
struct msdc_dma {
u32 sglen; /* size of scatter list */
struct scatterlist *sg; /* I/O scatter list */
u8 mode; /* dma mode */
struct gpd *gpd; /* pointer to gpd array */
struct bd *bd; /* pointer to bd array */
dma_addr_t gpd_addr; /* the physical address of gpd array */
dma_addr_t bd_addr; /* the physical address of bd array */
};
struct msdc_host {
struct msdc_hw *hw;
struct mmc_host *mmc; /* mmc structure */
struct mmc_command *cmd;
struct mmc_data *data;
struct mmc_request *mrq;
int cmd_rsp;
int error;
spinlock_t lock; /* mutex */
struct semaphore sem;
u32 blksz; /* host block size */
void __iomem *base; /* host base address */
int id; /* host id */
int pwr_ref; /* core power reference count */
u32 xfer_size; /* total transferred size */
struct msdc_dma dma; /* dma channel */
u32 dma_xfer_size; /* dma transfer size in bytes */
u32 timeout_ns; /* data timeout ns */
u32 timeout_clks; /* data timeout clks */
int irq; /* host interrupt */
struct delayed_work card_delaywork;
struct completion cmd_done;
struct completion xfer_done;
struct pm_message pm_state;
u32 mclk; /* mmc subsystem clock */
u32 hclk; /* host clock speed */
u32 sclk; /* SD/MS clock speed */
u8 core_clkon; /* Host core clock on ? */
u8 card_clkon; /* Card clock on ? */
u8 core_power; /* core power */
u8 power_mode; /* host power mode */
u8 card_inserted; /* card inserted ? */
u8 suspend; /* host suspended ? */
u8 app_cmd; /* for app command */
u32 app_cmd_arg;
};
#define sdr_read8(reg) readb(reg)
#define sdr_read32(reg) readl(reg)
#define sdr_write8(reg, val) writeb(val, reg)
#define sdr_write32(reg, val) writel(val, reg)
static inline void sdr_set_bits(void __iomem *reg, u32 bs)
{
u32 val = readl(reg);
val |= bs;
writel(val, reg);
}
static inline void sdr_clr_bits(void __iomem *reg, u32 bs)
{
u32 val = readl(reg);
val &= ~bs;
writel(val, reg);
}
static inline void sdr_set_field(void __iomem *reg, u32 field, u32 val)
{
unsigned int tv = readl(reg);
tv &= ~field;
tv |= ((val) << (ffs((unsigned int)field) - 1));
writel(tv, reg);
}
static inline void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
{
unsigned int tv = readl(reg);
*val = ((tv & field) >> (ffs((unsigned int)field) - 1));
}
#endif

2460
target/linux/ramips/files/drivers/mmc/host/mtk-mmc/sd.c Normal file
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File diff suppressed because it is too large Load Diff

1346
target/linux/ramips/files/drivers/mtd/nand/raw/mt7621_nand.c Normal file
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File diff suppressed because it is too large Load Diff

58
target/linux/ramips/files/drivers/net/ethernet/ralink/Kconfig Normal file
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@@ -0,0 +1,58 @@
config NET_VENDOR_RALINK
tristate "Ralink ethernet driver"
depends on RALINK
help
This driver supports the ethernet mac inside Ralink WiSoCs
config NET_RALINK_SOC
def_tristate NET_VENDOR_RALINK
if NET_RALINK_SOC
choice
prompt "MAC type"
config NET_RALINK_RT2880
bool "RT2882"
depends on MIPS && SOC_RT288X
config NET_RALINK_RT3050
bool "RT3050/MT7628"
depends on MIPS && (SOC_RT305X || SOC_MT7620)
config NET_RALINK_RT3883
bool "RT3883"
depends on MIPS && SOC_RT3883
config NET_RALINK_MT7620
bool "MT7620"
depends on MIPS && SOC_MT7620
endchoice
config NET_RALINK_HW_QOS
def_bool NET_RALINK_SOC
depends on NET_RALINK_MT7623
config NET_RALINK_MDIO
def_bool NET_RALINK_SOC
depends on (NET_RALINK_RT2880 || NET_RALINK_RT3883 || NET_RALINK_MT7620)
select PHYLIB
config NET_RALINK_MDIO_RT2880
def_bool NET_RALINK_SOC
depends on (NET_RALINK_RT2880 || NET_RALINK_RT3883)
select NET_RALINK_MDIO
config NET_RALINK_MDIO_MT7620
def_bool NET_RALINK_SOC
depends on NET_RALINK_MT7620
select NET_RALINK_MDIO
config NET_RALINK_ESW_RT3050
def_tristate NET_RALINK_SOC
depends on NET_RALINK_RT3050
config NET_RALINK_GSW_MT7620
def_tristate NET_RALINK_SOC
depends on NET_RALINK_MT7620
endif

18
target/linux/ramips/files/drivers/net/ethernet/ralink/Makefile Normal file
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@@ -0,0 +1,18 @@
#
# Makefile for the Ralink SoCs built-in ethernet macs
#
ralink-eth-y += mtk_eth_soc.o ethtool.o
ralink-eth-$(CONFIG_NET_RALINK_MDIO) += mdio.o
ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880) += mdio_rt2880.o
ralink-eth-$(CONFIG_NET_RALINK_MDIO_MT7620) += mdio_mt7620.o
ralink-eth-$(CONFIG_NET_RALINK_RT2880) += soc_rt2880.o
ralink-eth-$(CONFIG_NET_RALINK_RT3050) += soc_rt3050.o
ralink-eth-$(CONFIG_NET_RALINK_RT3883) += soc_rt3883.o
ralink-eth-$(CONFIG_NET_RALINK_MT7620) += soc_mt7620.o
obj-$(CONFIG_NET_RALINK_ESW_RT3050) += esw_rt3050.o
obj-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620.o mt7530.o
obj-$(CONFIG_NET_RALINK_SOC) += ralink-eth.o

1537
target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c Normal file
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32
target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.h Normal file
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@@ -0,0 +1,32 @@
/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#ifndef _RALINK_ESW_RT3052_H__
#define _RALINK_ESW_RT3052_H__
#ifdef CONFIG_NET_RALINK_ESW_RT3052
int __init mtk_switch_init(void);
void mtk_switch_exit(void);
#else
static inline int __init mtk_switch_init(void) { return 0; }
static inline void mtk_switch_exit(void) { }
#endif
int rt3050_esw_init(struct fe_priv *priv);
int rt3050_esw_has_carrier(struct fe_priv *priv);
#endif

234
target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.c Normal file
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@@ -0,0 +1,234 @@
/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include "mtk_eth_soc.h"
static const char fe_gdma_str[][ETH_GSTRING_LEN] = {
#define _FE(x...) # x,
FE_STAT_REG_DECLARE
#undef _FE
};
static int fe_get_link_ksettings(struct net_device *ndev,
struct ethtool_link_ksettings *cmd)
{
struct fe_priv *priv = netdev_priv(ndev);
if (!priv->phy_dev)
return -ENODEV;
if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
if (phy_read_status(priv->phy_dev))
return -ENODEV;
}
phy_ethtool_ksettings_get(ndev->phydev, cmd);
return 0;
}
static int fe_set_link_ksettings(struct net_device *ndev,
const struct ethtool_link_ksettings *cmd)
{
struct fe_priv *priv = netdev_priv(ndev);
if (!priv->phy_dev)
goto out_sset;
if (cmd->base.phy_address != priv->phy_dev->mdio.addr) {
if (priv->phy->phy_node[cmd->base.phy_address]) {
priv->phy_dev = priv->phy->phy[cmd->base.phy_address];
priv->phy_flags = FE_PHY_FLAG_PORT;
} else if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, cmd->base.phy_address)) {
priv->phy_dev = mdiobus_get_phy(priv->mii_bus, cmd->base.phy_address);
priv->phy_flags = FE_PHY_FLAG_ATTACH;
} else {
goto out_sset;
}
}
return phy_ethtool_ksettings_set(ndev->phydev, cmd);
out_sset:
return -ENODEV;
}
static void fe_get_drvinfo(struct net_device *dev,
struct ethtool_drvinfo *info)
{
struct fe_priv *priv = netdev_priv(dev);
struct fe_soc_data *soc = priv->soc;
strlcpy(info->driver, priv->dev->driver->name, sizeof(info->driver));
strlcpy(info->version, MTK_FE_DRV_VERSION, sizeof(info->version));
strlcpy(info->bus_info, dev_name(priv->dev), sizeof(info->bus_info));
if (soc->reg_table[FE_REG_FE_COUNTER_BASE])
info->n_stats = ARRAY_SIZE(fe_gdma_str);
}
static u32 fe_get_msglevel(struct net_device *dev)
{
struct fe_priv *priv = netdev_priv(dev);
return priv->msg_enable;
}
static void fe_set_msglevel(struct net_device *dev, u32 value)
{
struct fe_priv *priv = netdev_priv(dev);
priv->msg_enable = value;
}
static int fe_nway_reset(struct net_device *dev)
{
struct fe_priv *priv = netdev_priv(dev);
if (!priv->phy_dev)
goto out_nway_reset;
return genphy_restart_aneg(priv->phy_dev);
out_nway_reset:
return -EOPNOTSUPP;
}
static u32 fe_get_link(struct net_device *dev)
{
struct fe_priv *priv = netdev_priv(dev);
int err;
if (!priv->phy_dev)
goto out_get_link;
if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
err = genphy_update_link(priv->phy_dev);
if (err)
goto out_get_link;
}
return priv->phy_dev->link;
out_get_link:
return ethtool_op_get_link(dev);
}
static int fe_set_ringparam(struct net_device *dev,
struct ethtool_ringparam *ring,
struct kernel_ethtool_ringparam *kernel_rp,
struct netlink_ext_ack *extack)
{
struct fe_priv *priv = netdev_priv(dev);
if ((ring->tx_pending < 2) ||
(ring->rx_pending < 2) ||
(ring->rx_pending > MAX_DMA_DESC) ||
(ring->tx_pending > MAX_DMA_DESC))
return -EINVAL;
dev->netdev_ops->ndo_stop(dev);
priv->tx_ring.tx_ring_size = BIT(fls(ring->tx_pending) - 1);
priv->rx_ring.rx_ring_size = BIT(fls(ring->rx_pending) - 1);
dev->netdev_ops->ndo_open(dev);
return 0;
}
static void fe_get_ringparam(struct net_device *dev,
struct ethtool_ringparam *ring,
struct kernel_ethtool_ringparam *kernel_rp,
struct netlink_ext_ack *extack)
{
struct fe_priv *priv = netdev_priv(dev);
ring->rx_max_pending = MAX_DMA_DESC;
ring->tx_max_pending = MAX_DMA_DESC;
ring->rx_pending = priv->rx_ring.rx_ring_size;
ring->tx_pending = priv->tx_ring.tx_ring_size;
}
static void fe_get_strings(struct net_device *dev, u32 stringset, u8 *data)
{
switch (stringset) {
case ETH_SS_STATS:
ethtool_puts(&data, *fe_gdma_str);
break;
}
}
static int fe_get_sset_count(struct net_device *dev, int sset)
{
switch (sset) {
case ETH_SS_STATS:
return ARRAY_SIZE(fe_gdma_str);
default:
return -EOPNOTSUPP;
}
}
static void fe_get_ethtool_stats(struct net_device *dev,
struct ethtool_stats *stats, u64 *data)
{
struct fe_priv *priv = netdev_priv(dev);
struct fe_hw_stats *hwstats = priv->hw_stats;
u64 *data_src, *data_dst;
unsigned int start;
int i;
if (netif_running(dev) && netif_device_present(dev)) {
if (spin_trylock(&hwstats->stats_lock)) {
fe_stats_update(priv);
spin_unlock(&hwstats->stats_lock);
}
}
do {
data_src = &hwstats->tx_bytes;
data_dst = data;
start = u64_stats_fetch_begin(&hwstats->syncp);
for (i = 0; i < ARRAY_SIZE(fe_gdma_str); i++)
*data_dst++ = *data_src++;
} while (u64_stats_fetch_retry(&hwstats->syncp, start));
}
static struct ethtool_ops fe_ethtool_ops = {
.get_link_ksettings = fe_get_link_ksettings,
.set_link_ksettings = fe_set_link_ksettings,
.get_drvinfo = fe_get_drvinfo,
.get_msglevel = fe_get_msglevel,
.set_msglevel = fe_set_msglevel,
.nway_reset = fe_nway_reset,
.get_link = fe_get_link,
.set_ringparam = fe_set_ringparam,
.get_ringparam = fe_get_ringparam,
};
void fe_set_ethtool_ops(struct net_device *netdev)
{
struct fe_priv *priv = netdev_priv(netdev);
struct fe_soc_data *soc = priv->soc;
if (soc->reg_table[FE_REG_FE_COUNTER_BASE]) {
fe_ethtool_ops.get_strings = fe_get_strings;
fe_ethtool_ops.get_sset_count = fe_get_sset_count;
fe_ethtool_ops.get_ethtool_stats = fe_get_ethtool_stats;
}
netdev->ethtool_ops = &fe_ethtool_ops;
}

22
target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.h Normal file
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@@ -0,0 +1,22 @@
/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#ifndef FE_ETHTOOL_H
#define FE_ETHTOOL_H
#include <linux/ethtool.h>
void fe_set_ethtool_ops(struct net_device *netdev);
#endif /* FE_ETHTOOL_H */

308
target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c Normal file
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@@ -0,0 +1,308 @@
/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <linux/mii.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <ralink_regs.h>
#include "mtk_eth_soc.h"
#include "gsw_mt7620.h"
void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
{
iowrite32(val, gsw->base + reg);
}
u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
{
return ioread32(gsw->base + reg);
}
static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
{
struct fe_priv *priv = (struct fe_priv *)_priv;
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
u32 status;
int i, max = (gsw->port4_ephy) ? (4) : (3);
status = mtk_switch_r32(gsw, GSW_REG_ISR);
if (status & PORT_IRQ_ST_CHG)
for (i = 0; i <= max; i++) {
u32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i));
int link = status & 0x1;
if (link != priv->link[i])
mt7620_print_link_state(priv, i, link,
(status >> 2) & 3,
(status & 0x2));
priv->link[i] = link;
}
mt7620_handle_carrier(priv);
mtk_switch_w32(gsw, status, GSW_REG_ISR);
return IRQ_HANDLED;
}
static void gsw_reset_ephy(struct mt7620_gsw *gsw)
{
if (!gsw->rst_ephy)
return;
reset_control_assert(gsw->rst_ephy);
usleep_range(10, 20);
reset_control_deassert(gsw->rst_ephy);
usleep_range(10, 20);
}
static void mt7620_ephy_init(struct mt7620_gsw *gsw)
{
u32 i;
u32 val;
u32 is_BGA = (rt_sysc_r32(SYSC_REG_CHIP_REV_ID) >> 16) & 1;
if (gsw->ephy_disable) {
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(gsw->ephy_base << 16) | (0x1f << 24),
GSW_REG_GPC1);
pr_info("gsw: internal ephy disabled\n");
return;
} else if (gsw->ephy_base) {
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(gsw->ephy_base << 16),
GSW_REG_GPC1);
gsw_reset_ephy(gsw);
pr_info("gsw: ephy base address: %d\n", gsw->ephy_base);
}
/* global page 4 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x4000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x7444);
if (is_BGA)
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0114);
else
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0117);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x10cf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x6212);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0777);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 29, 0x4000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 28, 0xc077);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0000);
/* global page 3 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x3000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x4838);
/* global page 2 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x2000);
if (is_BGA) {
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0515);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0053);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aaf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x0fad);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fc1);
} else {
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0517);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0fd2);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aab);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x00ae);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fff);
}
/* global page 1 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x1000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0xe7f8);
/* turn on all PHYs */
for (i = 0; i <= 4; i++) {
val = _mt7620_mii_read(gsw, gsw->ephy_base + i, MII_BMCR);
val &= ~BMCR_PDOWN;
val |= BMCR_ANRESTART | BMCR_ANENABLE | BMCR_SPEED100;
_mt7620_mii_write(gsw, gsw->ephy_base + i, MII_BMCR, val);
}
/* global page 0 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x8000);
_mt7620_mii_write(gsw, gsw->ephy_base + 0, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 2, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 3, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 0, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 2, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 3, 4, 0x05e1);
/* global page 2 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 0, 16, 0x1111);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 16, 0x1010);
_mt7620_mii_write(gsw, gsw->ephy_base + 2, 16, 0x1515);
_mt7620_mii_write(gsw, gsw->ephy_base + 3, 16, 0x0f0f);
/* setup port 4 */
if (gsw->port4_ephy) {
val = rt_sysc_r32(SYSC_REG_CFG1);
val |= 3 << 14;
rt_sysc_w32(val, SYSC_REG_CFG1);
_mt7620_mii_write(gsw, gsw->ephy_base + 4, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 4, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 4, 16, 0x1313);
pr_info("gsw: setting port4 to ephy mode\n");
}
}
static void mt7620_mac_init(struct mt7620_gsw *gsw)
{
/* Internal ethernet requires PCIe RC mode */
rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | PCIE_RC_MODE, SYSC_REG_CFG1);
/* Keep Global Clocks on Idle traffic */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
/* Set Port 6 to Force Link 1G, Flow Control ON */
mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
/* Set Port 6 as CPU Port */
mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
/* Enable MIB stats */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
}
static const struct of_device_id mediatek_gsw_match[] = {
{ .compatible = "mediatek,mt7620-gsw" },
{},
};
MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
int mtk_gsw_init(struct fe_priv *priv)
{
struct device_node *eth_node = priv->dev->of_node;
struct device_node *phy_node, *mdiobus_node;
struct device_node *np = priv->switch_np;
struct platform_device *pdev = of_find_device_by_node(np);
struct mt7620_gsw *gsw;
const __be32 *id;
int ret;
u8 val;
if (!pdev)
return -ENODEV;
if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
return -EINVAL;
gsw = platform_get_drvdata(pdev);
priv->soc->swpriv = gsw;
gsw->ephy_disable = of_property_read_bool(np, "mediatek,ephy-disable");
mdiobus_node = of_get_child_by_name(eth_node, "mdio-bus");
if (mdiobus_node) {
for_each_child_of_node(mdiobus_node, phy_node) {
id = of_get_property(phy_node, "reg", NULL);
if (id && (be32_to_cpu(*id) == 0x1f))
gsw->ephy_disable = true;
}
of_node_put(mdiobus_node);
}
gsw->port4_ephy = !of_property_read_bool(np, "mediatek,port4-gmac");
if (of_property_read_u8(np, "mediatek,ephy-base", &val) == 0)
gsw->ephy_base = val;
else
gsw->ephy_base = 0;
mt7620_mac_init(gsw);
mt7620_ephy_init(gsw);
if (gsw->irq) {
ret = devm_request_irq(&pdev->dev, gsw->irq, gsw_interrupt_mt7620, 0,
"gsw", priv);
if (ret) {
dev_err(&pdev->dev, "Failed to request irq");
return ret;
}
mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
}
return 0;
}
static int mt7620_gsw_probe(struct platform_device *pdev)
{
struct mt7620_gsw *gsw;
gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
if (!gsw)
return -ENOMEM;
gsw->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(gsw->base))
return PTR_ERR(gsw->base);
gsw->dev = &pdev->dev;
gsw->irq = platform_get_irq(pdev, 0);
gsw->rst_ephy = devm_reset_control_get_exclusive(&pdev->dev, "ephy");
if (IS_ERR(gsw->rst_ephy)) {
dev_err(gsw->dev, "failed to get EPHY reset: %pe\n", gsw->rst_ephy);
gsw->rst_ephy = NULL;
}
platform_set_drvdata(pdev, gsw);
return 0;
}
static int mt7620_gsw_remove(struct platform_device *pdev)
{
platform_set_drvdata(pdev, NULL);
return 0;
}
static struct platform_driver gsw_driver = {
.probe = mt7620_gsw_probe,
.remove = mt7620_gsw_remove,
.driver = {
.name = "mt7620-gsw",
.of_match_table = mediatek_gsw_match,
},
};
module_platform_driver(gsw_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
MODULE_VERSION(MTK_FE_DRV_VERSION);

123
target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.h Normal file
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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/reset.h>
#ifndef _RALINK_GSW_MT7620_H__
#define _RALINK_GSW_MT7620_H__
#define GSW_REG_PHY_TIMEOUT (5 * HZ)
#define MT7620A_GSW_REG_PIAC 0x7004
#define GSW_NUM_VLANS 16
#define GSW_NUM_VIDS 4096
#define GSW_NUM_PORTS 7
#define GSW_PORT6 6
#define GSW_MDIO_ACCESS BIT(31)
#define GSW_MDIO_READ BIT(19)
#define GSW_MDIO_WRITE BIT(18)
#define GSW_MDIO_START BIT(16)
#define GSW_MDIO_ADDR_SHIFT 20
#define GSW_MDIO_REG_SHIFT 25
#define GSW_REG_MIB_CNT_EN 0x4000
#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
#define GSW_REG_SMACCR0 0x3fE4
#define GSW_REG_SMACCR1 0x3fE8
#define GSW_REG_CKGCR 0x3ff0
#define GSW_REG_IMR 0x7008
#define GSW_REG_ISR 0x700c
#define GSW_REG_GPC1 0x7014
#define GSW_REG_GPC2 0x701c
#define GSW_REG_GPCx_TXDELAY BIT(3)
#define GSW_REG_GPCx_RXDELAY BIT(2)
#define GSW_REG_MAC_P0_MCR 0x100
#define GSW_REG_MAC_P1_MCR 0x200
// Global MAC control register
#define GSW_REG_GMACCR 0x30E0
#define SYSC_REG_CHIP_REV_ID 0x0c
#define SYSC_REG_CFG1 0x14
#define PCIE_RC_MODE BIT(8)
#define SYSC_PAD_RGMII2_MDIO 0x58
#define SYSC_GPIO_MODE 0x60
#define PORT_IRQ_ST_CHG 0x7f
#define ESW_PHY_POLLING 0x7000
#define PMCR_IPG BIT(18)
#define PMCR_MAC_MODE BIT(16)
#define PMCR_FORCE BIT(15)
#define PMCR_TX_EN BIT(14)
#define PMCR_RX_EN BIT(13)
#define PMCR_BACKOFF BIT(9)
#define PMCR_BACKPRES BIT(8)
#define PMCR_RX_FC BIT(5)
#define PMCR_TX_FC BIT(4)
#define PMCR_SPEED(_x) (_x << 2)
#define PMCR_DUPLEX BIT(1)
#define PMCR_LINK BIT(0)
#define PHY_AN_EN BIT(31)
#define PHY_PRE_EN BIT(30)
#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
enum {
/* Global attributes. */
GSW_ATTR_ENABLE_VLAN,
/* Port attributes. */
GSW_ATTR_PORT_UNTAG,
};
struct mt7620_gsw {
struct device *dev;
struct reset_control *rst_ephy;
void __iomem *base;
int irq;
bool ephy_disable;
bool port4_ephy;
unsigned long int autopoll;
u16 ephy_base;
};
void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);
int mtk_gsw_init(struct fe_priv *priv);
int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
int mt7620_has_carrier(struct fe_priv *priv);
void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
int speed, int duplex);
void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
u32 phy_register, u32 write_data);
u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);
void mt7620_handle_carrier(struct fe_priv *priv);
#endif

273
target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c Normal file
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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/phy.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include "mtk_eth_soc.h"
#include "mdio.h"
static int fe_mdio_reset(struct mii_bus *bus)
{
/* TODO */
return 0;
}
static void fe_phy_link_adjust(struct net_device *dev)
{
struct fe_priv *priv = netdev_priv(dev);
unsigned long flags;
int i;
spin_lock_irqsave(&priv->phy->lock, flags);
for (i = 0; i < 8; i++) {
if (priv->phy->phy_node[i]) {
struct phy_device *phydev = priv->phy->phy[i];
int status_change = 0;
if (phydev->link)
if (priv->phy->duplex[i] != phydev->duplex ||
priv->phy->speed[i] != phydev->speed)
status_change = 1;
if (phydev->link != priv->link[i])
status_change = 1;
switch (phydev->speed) {
case SPEED_1000:
case SPEED_100:
case SPEED_10:
priv->link[i] = phydev->link;
priv->phy->duplex[i] = phydev->duplex;
priv->phy->speed[i] = phydev->speed;
if (status_change &&
priv->soc->mdio_adjust_link)
priv->soc->mdio_adjust_link(priv, i);
break;
}
}
}
spin_unlock_irqrestore(&priv->phy->lock, flags);
}
int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node, int port)
{
const __be32 *_phy_addr = NULL;
struct phy_device *phydev;
phy_interface_t phy_mode = PHY_INTERFACE_MODE_NA;
_phy_addr = of_get_property(phy_node, "reg", NULL);
if (!_phy_addr || (be32_to_cpu(*_phy_addr) >= 0x20)) {
pr_err("%s: invalid phy id\n", phy_node->name);
return -EINVAL;
}
of_get_phy_mode(phy_node, &phy_mode);
if (phy_mode == PHY_INTERFACE_MODE_NA) {
dev_err(priv->dev, "incorrect phy-mode %d\n", phy_mode);
priv->phy->phy_node[port] = NULL;
return -EINVAL;
}
phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
0, phy_mode);
if (!phydev) {
dev_err(priv->dev, "could not connect to PHY\n");
priv->phy->phy_node[port] = NULL;
return -ENODEV;
}
phy_set_max_speed(phydev, SPEED_1000);
linkmode_copy(phydev->advertising, phydev->supported);
phydev->no_auto_carrier_off = 1;
dev_info(priv->dev,
"connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
port, dev_name(&phydev->mdio.dev), phydev->phy_id,
phydev->drv->name);
priv->phy->phy[port] = phydev;
priv->link[port] = 0;
return 0;
}
static void phy_init(struct fe_priv *priv, struct phy_device *phy)
{
phy_attach(priv->netdev, dev_name(&phy->mdio.dev), PHY_INTERFACE_MODE_MII);
phy->autoneg = AUTONEG_ENABLE;
phy->speed = 0;
phy->duplex = 0;
phy_set_max_speed(phy, IS_ENABLED(CONFIG_NET_RALINK_MDIO_MT7620) ?
SPEED_1000 :
SPEED_100);
linkmode_copy(phy->advertising, phy->supported);
linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phy->advertising);
phy_start_aneg(phy);
}
static int fe_phy_connect(struct fe_priv *priv)
{
int i;
for (i = 0; i < 8; i++) {
if (priv->phy->phy_node[i]) {
if (!priv->phy_dev) {
priv->phy_dev = priv->phy->phy[i];
priv->phy_flags = FE_PHY_FLAG_PORT;
}
} else if (priv->mii_bus) {
struct phy_device *phydev;
phydev = mdiobus_get_phy(priv->mii_bus, i);
if (!phydev || phydev->attached_dev)
continue;
phy_init(priv, phydev);
if (!priv->phy_dev) {
priv->phy_dev = mdiobus_get_phy(priv->mii_bus, i);
priv->phy_flags = FE_PHY_FLAG_ATTACH;
}
}
}
return 0;
}
static void fe_phy_disconnect(struct fe_priv *priv)
{
unsigned long flags;
int i;
for (i = 0; i < 8; i++)
if (priv->phy->phy_fixed[i]) {
spin_lock_irqsave(&priv->phy->lock, flags);
priv->link[i] = 0;
if (priv->soc->mdio_adjust_link)
priv->soc->mdio_adjust_link(priv, i);
spin_unlock_irqrestore(&priv->phy->lock, flags);
} else if (priv->phy->phy[i]) {
phy_disconnect(priv->phy->phy[i]);
} else if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, i)) {
phy_detach(mdiobus_get_phy(priv->mii_bus, i));
}
}
static void fe_phy_start(struct fe_priv *priv)
{
unsigned long flags;
int i;
for (i = 0; i < 8; i++) {
if (priv->phy->phy_fixed[i]) {
spin_lock_irqsave(&priv->phy->lock, flags);
priv->link[i] = 1;
if (priv->soc->mdio_adjust_link)
priv->soc->mdio_adjust_link(priv, i);
spin_unlock_irqrestore(&priv->phy->lock, flags);
} else if (priv->phy->phy[i]) {
phy_start(priv->phy->phy[i]);
}
}
}
static void fe_phy_stop(struct fe_priv *priv)
{
unsigned long flags;
int i;
for (i = 0; i < 8; i++)
if (priv->phy->phy_fixed[i]) {
spin_lock_irqsave(&priv->phy->lock, flags);
priv->link[i] = 0;
if (priv->soc->mdio_adjust_link)
priv->soc->mdio_adjust_link(priv, i);
spin_unlock_irqrestore(&priv->phy->lock, flags);
} else if (priv->phy->phy[i]) {
phy_stop(priv->phy->phy[i]);
}
}
static struct fe_phy phy_ralink = {
.connect = fe_phy_connect,
.disconnect = fe_phy_disconnect,
.start = fe_phy_start,
.stop = fe_phy_stop,
};
int fe_mdio_init(struct fe_priv *priv)
{
struct device_node *mii_np;
int err;
if (!priv->soc->mdio_read || !priv->soc->mdio_write)
return 0;
spin_lock_init(&phy_ralink.lock);
priv->phy = &phy_ralink;
mii_np = of_get_child_by_name(priv->dev->of_node, "mdio-bus");
if (!mii_np) {
dev_err(priv->dev, "no %s child node found", "mdio-bus");
err = 0;
goto err_no_bus;
}
if (!of_device_is_available(mii_np)) {
err = 0;
goto err_put_node;
}
priv->mii_bus = mdiobus_alloc();
if (!priv->mii_bus) {
err = -ENOMEM;
goto err_put_node;
}
priv->mii_bus->name = "mdio";
priv->mii_bus->read = priv->soc->mdio_read;
priv->mii_bus->write = priv->soc->mdio_write;
priv->mii_bus->reset = fe_mdio_reset;
priv->mii_bus->priv = priv;
priv->mii_bus->parent = priv->dev;
snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
err = of_mdiobus_register(priv->mii_bus, mii_np);
if (err)
goto err_free_bus;
return 0;
err_free_bus:
kfree(priv->mii_bus);
err_put_node:
of_node_put(mii_np);
err_no_bus:
dev_info(priv->dev, "%s disabled", "mdio-bus");
priv->mii_bus = NULL;
return err;
}
void fe_mdio_cleanup(struct fe_priv *priv)
{
if (!priv->mii_bus)
return;
mdiobus_unregister(priv->mii_bus);
of_node_put(priv->mii_bus->dev.of_node);
kfree(priv->mii_bus);
}

28
target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.h Normal file
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@@ -0,0 +1,28 @@
/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#ifndef _RALINK_MDIO_H__
#define _RALINK_MDIO_H__
#ifdef CONFIG_NET_RALINK_MDIO
int fe_mdio_init(struct fe_priv *priv);
void fe_mdio_cleanup(struct fe_priv *priv);
int fe_connect_phy_node(struct fe_priv *priv,
struct device_node *phy_node,
int port);
#else
static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
#endif
#endif

168
target/linux/ramips/files/drivers/net/ethernet/ralink/mdio_mt7620.c Normal file
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@@ -0,0 +1,168 @@
/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include "mtk_eth_soc.h"
#include "gsw_mt7620.h"
#include "mdio.h"
static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
{
unsigned long t_start = jiffies;
while (1) {
if (!(mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
return 0;
if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT))
break;
}
dev_err(gsw->dev, "mdio: MDIO timeout\n");
return -1;
}
u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
u32 phy_register, u32 write_data)
{
if (mt7620_mii_busy_wait(gsw))
return -1;
write_data &= 0xffff;
mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
(phy_register << GSW_MDIO_REG_SHIFT) |
(phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
MT7620A_GSW_REG_PIAC);
if (mt7620_mii_busy_wait(gsw))
return -1;
return 0;
}
u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
{
u32 d;
if (mt7620_mii_busy_wait(gsw))
return 0xffff;
mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
(phy_reg << GSW_MDIO_REG_SHIFT) |
(phy_addr << GSW_MDIO_ADDR_SHIFT),
MT7620A_GSW_REG_PIAC);
if (mt7620_mii_busy_wait(gsw))
return 0xffff;
d = mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
return d;
}
int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
{
struct fe_priv *priv = bus->priv;
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
}
int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
{
struct fe_priv *priv = bus->priv;
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
return _mt7620_mii_read(gsw, phy_addr, phy_reg);
}
void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
{
_mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
_mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
_mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16);
}
u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
{
u16 high, low;
_mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
low = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf);
high = _mt7620_mii_read(gsw, 0x1f, 0x10);
return (high << 16) | (low & 0xffff);
}
static unsigned char *fe_speed_str(int speed)
{
switch (speed) {
case 2:
case SPEED_1000:
return "1000";
case 1:
case SPEED_100:
return "100";
case 0:
case SPEED_10:
return "10";
}
return "? ";
}
int mt7620_has_carrier(struct fe_priv *priv)
{
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
int i;
for (i = 0; i < GSW_PORT6; i++)
if (mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
return 1;
return 0;
}
void mt7620_handle_carrier(struct fe_priv *priv)
{
if (!priv->phy)
return;
if (mt7620_has_carrier(priv))
netif_carrier_on(priv->netdev);
else
netif_carrier_off(priv->netdev);
}
void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
int speed, int duplex)
{
if (link)
netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
port, fe_speed_str(speed),
(duplex) ? "Full" : "Half");
else
netdev_info(priv->netdev, "port %d link down\n", port);
}
void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
{
mt7620_print_link_state(priv, port, priv->link[port],
priv->phy->speed[port],
(priv->phy->duplex[port] == DUPLEX_FULL));
mt7620_handle_carrier(priv);
}

222
target/linux/ramips/files/drivers/net/ethernet/ralink/mdio_rt2880.c Normal file
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@@ -0,0 +1,222 @@
/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include "mtk_eth_soc.h"
#include "mdio_rt2880.h"
#include "mdio.h"
#define FE_MDIO_RETRY 1000
static unsigned char *rt2880_speed_str(struct fe_priv *priv)
{
switch (priv->phy->speed[0]) {
case SPEED_1000:
return "1000";
case SPEED_100:
return "100";
case SPEED_10:
return "10";
}
return "?";
}
void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
{
u32 mdio_cfg;
if (!priv->link[0]) {
netif_carrier_off(priv->netdev);
netdev_info(priv->netdev, "link down\n");
return;
}
mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
FE_MDIO_CFG_RX_CLK_SKEW_200 |
FE_MDIO_CFG_GP1_FRC_EN;
if (priv->phy->duplex[0] == DUPLEX_FULL)
mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
if (priv->phy->tx_fc[0])
mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
if (priv->phy->rx_fc[0])
mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
switch (priv->phy->speed[0]) {
case SPEED_10:
mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
break;
case SPEED_100:
mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
break;
case SPEED_1000:
mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
break;
default:
BUG();
}
fe_w32(mdio_cfg, FE_MDIO_CFG);
netif_carrier_on(priv->netdev);
netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
rt2880_speed_str(priv),
(priv->phy->duplex[0] == DUPLEX_FULL) ? "Full" : "Half");
}
static int rt2880_mdio_wait_ready(struct fe_priv *priv)
{
int retries;
retries = FE_MDIO_RETRY;
while (1) {
u32 t;
t = fe_r32(FE_MDIO_ACCESS);
if ((t & BIT(31)) == 0)
return 0;
if (retries-- == 0)
break;
udelay(1);
}
dev_err(priv->dev, "MDIO operation timed out\n");
return -ETIMEDOUT;
}
int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
{
struct fe_priv *priv = bus->priv;
int err;
u32 t;
err = rt2880_mdio_wait_ready(priv);
if (err)
return 0xffff;
t = (phy_addr << 24) | (phy_reg << 16);
fe_w32(t, FE_MDIO_ACCESS);
t |= BIT(31);
fe_w32(t, FE_MDIO_ACCESS);
err = rt2880_mdio_wait_ready(priv);
if (err)
return 0xffff;
pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
return fe_r32(FE_MDIO_ACCESS) & 0xffff;
}
int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
{
struct fe_priv *priv = bus->priv;
int err;
u32 t;
pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
err = rt2880_mdio_wait_ready(priv);
if (err)
return err;
t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
fe_w32(t, FE_MDIO_ACCESS);
t |= BIT(31);
fe_w32(t, FE_MDIO_ACCESS);
return rt2880_mdio_wait_ready(priv);
}
void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
{
const __be32 *id = of_get_property(np, "reg", NULL);
const __be32 *link;
int size;
phy_interface_t phy_mode = PHY_INTERFACE_MODE_NA;
if (!id || (be32_to_cpu(*id) != 0)) {
pr_err("%s: invalid port id\n", np->name);
return;
}
priv->phy->phy_fixed[0] = of_get_property(np,
"mediatek,fixed-link", &size);
if (priv->phy->phy_fixed[0] &&
(size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
pr_err("%s: invalid fixed link property\n", np->name);
priv->phy->phy_fixed[0] = NULL;
return;
}
of_get_phy_mode(np, &phy_mode);
switch (phy_mode) {
case PHY_INTERFACE_MODE_RGMII:
break;
case PHY_INTERFACE_MODE_MII:
break;
case PHY_INTERFACE_MODE_RMII:
break;
default:
if (!priv->phy->phy_fixed[0])
dev_err(priv->dev, "port %d - invalid phy mode\n",
priv->phy->speed[0]);
break;
}
priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
return;
if (priv->phy->phy_fixed[0]) {
link = priv->phy->phy_fixed[0];
priv->phy->speed[0] = be32_to_cpup(link++);
priv->phy->duplex[0] = be32_to_cpup(link++);
priv->phy->tx_fc[0] = be32_to_cpup(link++);
priv->phy->rx_fc[0] = be32_to_cpup(link++);
priv->link[0] = 1;
switch (priv->phy->speed[0]) {
case SPEED_10:
break;
case SPEED_100:
break;
case SPEED_1000:
break;
default:
dev_err(priv->dev, "invalid link speed: %d\n",
priv->phy->speed[0]);
priv->phy->phy_fixed[0] = 0;
return;
}
dev_info(priv->dev, "using fixed link parameters\n");
rt2880_mdio_link_adjust(priv, 0);
return;
}
if (priv->phy->phy_node[0] && mdiobus_get_phy(priv->mii_bus, 0))
fe_connect_phy_node(priv, priv->phy->phy_node[0], 0);
}

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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#ifndef _RALINK_MDIO_RT2880_H__
#define _RALINK_MDIO_RT2880_H__
void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
#endif

1053
target/linux/ramips/files/drivers/net/ethernet/ralink/mt7530.c Normal file
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target/linux/ramips/files/drivers/net/ethernet/ralink/mt7530.h Normal file
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/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
* Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
*/
#ifndef _MT7530_H__
#define _MT7530_H__
#define MT7620_MIB_COUNTER_BASE_PORT 0x4000
#define MT7620_MIB_COUNTER_PORT_OFFSET 0x100
#define MT7620_MIB_COUNTER_BASE 0x1010
/* PPE Accounting Group #0 Byte Counter */
#define MT7620_MIB_STATS_PPE_AC_BCNT0 0x000
/* PPE Accounting Group #0 Packet Counter */
#define MT7620_MIB_STATS_PPE_AC_PCNT0 0x004
/* PPE Accounting Group #63 Byte Counter */
#define MT7620_MIB_STATS_PPE_AC_BCNT63 0x1F8
/* PPE Accounting Group #63 Packet Counter */
#define MT7620_MIB_STATS_PPE_AC_PCNT63 0x1FC
/* PPE Meter Group #0 */
#define MT7620_MIB_STATS_PPE_MTR_CNT0 0x200
/* PPE Meter Group #63 */
#define MT7620_MIB_STATS_PPE_MTR_CNT63 0x2FC
/* Transmit good byte count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_TX_GBCNT 0x300
/* Transmit good packet count for CPU GDM (exclude flow control frames) */
#define MT7620_MIB_STATS_GDM1_TX_GPCNT 0x304
/* Transmit abort count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_TX_SKIPCNT 0x308
/* Transmit collision count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_TX_COLCNT 0x30C
/* Received good byte count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_RX_GBCNT1 0x320
/* Received good packet count for CPU GDM (exclude flow control frame) */
#define MT7620_MIB_STATS_GDM1_RX_GPCNT1 0x324
/* Received overflow error packet count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_RX_OERCNT 0x328
/* Received FCS error packet count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_RX_FERCNT 0x32C
/* Received too short error packet count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_RX_SERCNT 0x330
/* Received too long error packet count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_RX_LERCNT 0x334
/* Received IP/TCP/UDP checksum error packet count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_RX_CERCNT 0x338
/* Received flow control pkt count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_RX_FCCNT 0x33C
/* Transmit good byte count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_TX_GBCNT 0x340
/* Transmit good packet count for PPE GDM (exclude flow control frames) */
#define MT7620_MIB_STATS_GDM2_TX_GPCNT 0x344
/* Transmit abort count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_TX_SKIPCNT 0x348
/* Transmit collision count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_TX_COLCNT 0x34C
/* Received good byte count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_RX_GBCNT 0x360
/* Received good packet count for PPE GDM (exclude flow control frame) */
#define MT7620_MIB_STATS_GDM2_RX_GPCNT 0x364
/* Received overflow error packet count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_RX_OERCNT 0x368
/* Received FCS error packet count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_RX_FERCNT 0x36C
/* Received too short error packet count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_RX_SERCNT 0x370
/* Received too long error packet count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_RX_LERCNT 0x374
/* Received IP/TCP/UDP checksum error packet count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_RX_CERCNT 0x378
/* Received flow control pkt count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_RX_FCCNT 0x37C
/* Tx Packet Counter of Port n */
#define MT7620_MIB_STATS_PORT_TGPCN 0x10
/* Tx Bad Octet Counter of Port n */
#define MT7620_MIB_STATS_PORT_TBOCN 0x14
/* Tx Good Octet Counter of Port n */
#define MT7620_MIB_STATS_PORT_TGOCN 0x18
/* Tx Event Packet Counter of Port n */
#define MT7620_MIB_STATS_PORT_TEPCN 0x1C
/* Rx Packet Counter of Port n */
#define MT7620_MIB_STATS_PORT_RGPCN 0x20
/* Rx Bad Octet Counter of Port n */
#define MT7620_MIB_STATS_PORT_RBOCN 0x24
/* Rx Good Octet Counter of Port n */
#define MT7620_MIB_STATS_PORT_RGOCN 0x28
/* Rx Event Packet Counter of Port n */
#define MT7620_MIB_STATS_PORT_REPC1N 0x2C
/* Rx Event Packet Counter of Port n */
#define MT7620_MIB_STATS_PORT_REPC2N 0x30
int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan);
#endif

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target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h Normal file
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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#ifndef FE_ETH_H
#define FE_ETH_H
#include <linux/mii.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/dma-mapping.h>
#include <linux/phy.h>
#include <linux/ethtool.h>
enum fe_reg {
FE_REG_PDMA_GLO_CFG = 0,
FE_REG_PDMA_RST_CFG,
FE_REG_DLY_INT_CFG,
FE_REG_TX_BASE_PTR0,
FE_REG_TX_MAX_CNT0,
FE_REG_TX_CTX_IDX0,
FE_REG_TX_DTX_IDX0,
FE_REG_RX_BASE_PTR0,
FE_REG_RX_MAX_CNT0,
FE_REG_RX_CALC_IDX0,
FE_REG_RX_DRX_IDX0,
FE_REG_FE_INT_ENABLE,
FE_REG_FE_INT_STATUS,
FE_REG_FE_DMA_VID_BASE,
FE_REG_FE_COUNTER_BASE,
FE_REG_FE_RST_GL,
FE_REG_FE_INT_STATUS2,
FE_REG_COUNT
};
enum fe_work_flag {
FE_FLAG_RESET_PENDING,
FE_FLAG_MAX
};
#define MTK_FE_DRV_VERSION "0.2"
/* power of 2 to let NEXT_TX_DESP_IDX work */
#define NUM_DMA_DESC BIT(10)
#define MAX_DMA_DESC 0xfff
#define FE_DELAY_EN_INT 0x80
#define FE_DELAY_MAX_INT 0x04
#define FE_DELAY_MAX_TOUT 0x04
#define FE_DELAY_TIME 20
#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | \
FE_DELAY_MAX_TOUT)
#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
#define FE_PSE_FQFC_CFG_INIT 0x80504000
#define FE_PSE_FQFC_CFG_256Q 0xff908000
/* interrupt bits */
#define FE_CNT_PPE_AF BIT(31)
#define FE_CNT_GDM_AF BIT(29)
#define FE_PSE_P2_FC BIT(26)
#define FE_PSE_BUF_DROP BIT(24)
#define FE_GDM_OTHER_DROP BIT(23)
#define FE_PSE_P1_FC BIT(22)
#define FE_PSE_P0_FC BIT(21)
#define FE_PSE_FQ_EMPTY BIT(20)
#define FE_GE1_STA_CHG BIT(18)
#define FE_TX_COHERENT BIT(17)
#define FE_RX_COHERENT BIT(16)
#define FE_TX_DONE_INT3 BIT(11)
#define FE_TX_DONE_INT2 BIT(10)
#define FE_TX_DONE_INT1 BIT(9)
#define FE_TX_DONE_INT0 BIT(8)
#define FE_RX_DONE_INT0 BIT(2)
#define FE_TX_DLY_INT BIT(1)
#define FE_RX_DLY_INT BIT(0)
#define FE_RX_DONE_INT FE_RX_DONE_INT0
#define FE_TX_DONE_INT (FE_TX_DONE_INT0 | FE_TX_DONE_INT1 | \
FE_TX_DONE_INT2 | FE_TX_DONE_INT3)
#define RT5350_RX_DLY_INT BIT(30)
#define RT5350_TX_DLY_INT BIT(28)
#define RT5350_RX_DONE_INT1 BIT(17)
#define RT5350_RX_DONE_INT0 BIT(16)
#define RT5350_TX_DONE_INT3 BIT(3)
#define RT5350_TX_DONE_INT2 BIT(2)
#define RT5350_TX_DONE_INT1 BIT(1)
#define RT5350_TX_DONE_INT0 BIT(0)
#define RT5350_RX_DONE_INT (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)
#define RT5350_TX_DONE_INT (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \
RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)
/* registers */
#define FE_FE_OFFSET 0x0000
#define FE_GDMA_OFFSET 0x0020
#define FE_PSE_OFFSET 0x0040
#define FE_GDMA2_OFFSET 0x0060
#define FE_CDMA_OFFSET 0x0080
#define FE_DMA_VID0 0x00a8
#define FE_PDMA_OFFSET 0x0100
#define FE_PPE_OFFSET 0x0200
#define FE_CMTABLE_OFFSET 0x0400
#define FE_POLICYTABLE_OFFSET 0x1000
#define RT5350_PDMA_OFFSET 0x0800
#define RT5350_SDM_OFFSET 0x0c00
#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
#ifdef CONFIG_SOC_MT7621
#define MT7620A_GDMA_OFFSET 0x0500
#else
#define MT7620A_GDMA_OFFSET 0x0600
#endif
#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
/* Switch DMA configuration */
#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00)
#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04)
#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08)
#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C)
#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10)
#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100)
#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104)
#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108)
#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C)
#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110)
#define RT5350_SDM_ICS_EN BIT(16)
#define RT5350_SDM_TCS_EN BIT(17)
#define RT5350_SDM_UCS_EN BIT(18)
/* MDIO_CFG register bits */
#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
/* uni-cast port */
#define FE_GDM1_JMB_LEN_MASK 0xf
#define FE_GDM1_JMB_LEN_SHIFT 28
#define FE_GDM1_ICS_EN BIT(22)
#define FE_GDM1_TCS_EN BIT(21)
#define FE_GDM1_UCS_EN BIT(20)
#define FE_GDM1_JMB_EN BIT(19)
#define FE_GDM1_STRPCRC BIT(16)
#define FE_GDM1_UFRC_P_CPU (0 << 12)
#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
#define FE_GDM1_UFRC_P_PPE (6 << 12)
/* checksums */
#define FE_ICS_GEN_EN BIT(2)
#define FE_UCS_GEN_EN BIT(1)
#define FE_TCS_GEN_EN BIT(0)
/* dma ring */
#define FE_PST_DRX_IDX0 BIT(16)
#define FE_PST_DTX_IDX3 BIT(3)
#define FE_PST_DTX_IDX2 BIT(2)
#define FE_PST_DTX_IDX1 BIT(1)
#define FE_PST_DTX_IDX0 BIT(0)
#define FE_RX_2B_OFFSET BIT(31)
#define FE_TX_WB_DDONE BIT(6)
#define FE_RX_DMA_BUSY BIT(3)
#define FE_TX_DMA_BUSY BIT(1)
#define FE_RX_DMA_EN BIT(2)
#define FE_TX_DMA_EN BIT(0)
#define FE_PDMA_SIZE_4DWORDS (0 << 4)
#define FE_PDMA_SIZE_8DWORDS (1 << 4)
#define FE_PDMA_SIZE_16DWORDS (2 << 4)
#define FE_US_CYC_CNT_MASK 0xff
#define FE_US_CYC_CNT_SHIFT 0x8
#define FE_US_CYC_CNT_DIVISOR 1000000
/* rxd2 */
#define RX_DMA_DONE BIT(31)
#define RX_DMA_LSO BIT(30)
#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
#define RX_DMA_TAG BIT(15)
/* rxd3 */
#define RX_DMA_TPID(_x) (((_x) >> 16) & 0xffff)
#define RX_DMA_VID(_x) ((_x) & 0xffff)
/* rxd4 */
#define RX_DMA_L4VALID BIT(30)
struct fe_rx_dma {
unsigned int rxd1;
unsigned int rxd2;
unsigned int rxd3;
unsigned int rxd4;
} __packed __aligned(4);
#define TX_DMA_BUF_LEN 0x3fff
#define TX_DMA_PLEN0_MASK (TX_DMA_BUF_LEN << 16)
#define TX_DMA_PLEN0(_x) (((_x) & TX_DMA_BUF_LEN) << 16)
#define TX_DMA_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
#define TX_DMA_GET_PLEN0(_x) (((_x) >> 16) & TX_DMA_BUF_LEN)
#define TX_DMA_GET_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
#define TX_DMA_LS1 BIT(14)
#define TX_DMA_LS0 BIT(30)
#define TX_DMA_DONE BIT(31)
#define TX_DMA_INS_VLAN_MT7621 BIT(16)
#define TX_DMA_INS_VLAN BIT(7)
#define TX_DMA_INS_PPPOE BIT(12)
#define TX_DMA_QN(_x) ((_x) << 16)
#define TX_DMA_PN(_x) ((_x) << 24)
#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
#define TX_DMA_UDF BIT(20)
#define TX_DMA_CHKSUM (0x7 << 29)
#define TX_DMA_TSO BIT(28)
/* frame engine counters */
#define FE_PPE_AC_BCNT0 (FE_CMTABLE_OFFSET + 0x00)
#define FE_GDMA1_TX_GBCNT (FE_CMTABLE_OFFSET + 0x300)
#define FE_GDMA2_TX_GBCNT (FE_GDMA1_TX_GBCNT + 0x40)
/* phy device flags */
#define FE_PHY_FLAG_PORT BIT(0)
#define FE_PHY_FLAG_ATTACH BIT(1)
struct fe_tx_dma {
unsigned int txd1;
unsigned int txd2;
unsigned int txd3;
unsigned int txd4;
} __packed __aligned(4);
struct fe_priv;
struct fe_phy {
/* make sure that phy operations are atomic */
spinlock_t lock;
struct phy_device *phy[8];
struct device_node *phy_node[8];
const __be32 *phy_fixed[8];
int duplex[8];
int speed[8];
int tx_fc[8];
int rx_fc[8];
int (*connect)(struct fe_priv *priv);
void (*disconnect)(struct fe_priv *priv);
void (*start)(struct fe_priv *priv);
void (*stop)(struct fe_priv *priv);
};
struct fe_soc_data {
const u16 *reg_table;
void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
void (*set_mac)(struct fe_priv *priv, const unsigned char *mac);
int (*fwd_config)(struct fe_priv *priv);
void (*tx_dma)(struct fe_tx_dma *txd);
int (*switch_init)(struct fe_priv *priv);
int (*switch_config)(struct fe_priv *priv);
void (*port_init)(struct fe_priv *priv, struct device_node *port);
int (*has_carrier)(struct fe_priv *priv);
int (*mdio_init)(struct fe_priv *priv);
void (*mdio_cleanup)(struct fe_priv *priv);
int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg,
u16 val);
int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
void (*mdio_adjust_link)(struct fe_priv *priv, int port);
void *swpriv;
u32 pdma_glo_cfg;
u32 rx_int;
u32 tx_int;
u32 status_int;
u32 checksum_bit;
};
#define FE_FLAG_PADDING_64B BIT(0)
#define FE_FLAG_PADDING_BUG BIT(1)
#define FE_FLAG_JUMBO_FRAME BIT(2)
#define FE_FLAG_RX_2B_OFFSET BIT(3)
#define FE_FLAG_RX_SG_DMA BIT(4)
#define FE_FLAG_NAPI_WEIGHT BIT(6)
#define FE_FLAG_CALIBRATE_CLK BIT(7)
#define FE_FLAG_HAS_SWITCH BIT(8)
#define FE_STAT_REG_DECLARE \
_FE(tx_bytes) \
_FE(tx_packets) \
_FE(tx_skip) \
_FE(tx_collisions) \
_FE(rx_bytes) \
_FE(rx_packets) \
_FE(rx_overflow) \
_FE(rx_fcs_errors) \
_FE(rx_short_errors) \
_FE(rx_long_errors) \
_FE(rx_checksum_errors) \
_FE(rx_flow_control_packets)
struct fe_hw_stats {
/* make sure that stats operations are atomic */
spinlock_t stats_lock;
struct u64_stats_sync syncp;
#define _FE(x) u64 x;
FE_STAT_REG_DECLARE
#undef _FE
};
struct fe_tx_buf {
struct sk_buff *skb;
DEFINE_DMA_UNMAP_ADDR(dma_addr0);
DEFINE_DMA_UNMAP_ADDR(dma_addr1);
u16 dma_len0;
u16 dma_len1;
};
struct fe_tx_ring {
struct fe_tx_dma *tx_dma;
struct fe_tx_buf *tx_buf;
dma_addr_t tx_phys;
u16 tx_ring_size;
u16 tx_free_idx;
u16 tx_next_idx;
u16 tx_thresh;
};
struct fe_rx_ring {
struct page_frag_cache frag_cache;
struct fe_rx_dma *rx_dma;
u8 **rx_data;
dma_addr_t rx_phys;
u16 rx_ring_size;
u16 frag_size;
u16 rx_buf_size;
u16 rx_calc_idx;
};
struct fe_priv {
/* make sure that register operations are atomic */
spinlock_t page_lock;
struct fe_soc_data *soc;
struct net_device *netdev;
struct device_node *switch_np;
u32 msg_enable;
u32 flags;
struct device *dev;
unsigned long sysclk;
struct fe_rx_ring rx_ring;
struct napi_struct rx_napi;
struct fe_tx_ring tx_ring;
struct fe_phy *phy;
struct mii_bus *mii_bus;
struct phy_device *phy_dev;
u32 phy_flags;
int link[8];
struct fe_hw_stats *hw_stats;
unsigned long vlan_map;
struct work_struct pending_work;
DECLARE_BITMAP(pending_flags, FE_FLAG_MAX);
struct reset_control *resets;
struct mtk_foe_entry *foe_table;
dma_addr_t foe_table_phys;
struct flow_offload __rcu **foe_flow_table;
};
extern const struct of_device_id of_fe_match[];
void fe_w32(u32 val, unsigned reg);
void fe_m32(struct fe_priv *priv, u32 clear, u32 set, unsigned reg);
u32 fe_r32(unsigned reg);
int fe_set_clock_cycle(struct fe_priv *priv);
void fe_csum_config(struct fe_priv *priv);
void fe_stats_update(struct fe_priv *priv);
void fe_fwd_config(struct fe_priv *priv);
void fe_reg_w32(u32 val, enum fe_reg reg);
u32 fe_reg_r32(enum fe_reg reg);
static inline void *priv_netdev(struct fe_priv *priv)
{
return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
}
#endif /* FE_ETH_H */

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target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c Normal file
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@@ -0,0 +1,369 @@
/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/if_vlan.h>
#include <linux/of_net.h>
#include <asm/mach-ralink/ralink_regs.h>
#include <mt7620.h>
#include "mtk_eth_soc.h"
#include "gsw_mt7620.h"
#include "mt7530.h"
#include "mdio.h"
#define MT7620A_CDMA_CSG_CFG 0x400
#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
#define MT7620_L4_VALID BIT(23)
#define MT7620_TX_DMA_UDF BIT(15)
#define TX_DMA_FP_BMAP ((0xff) << 19)
#define CDMA_ICS_EN BIT(2)
#define CDMA_UCS_EN BIT(1)
#define CDMA_TCS_EN BIT(0)
#define GDMA_ICS_EN BIT(22)
#define GDMA_TCS_EN BIT(21)
#define GDMA_UCS_EN BIT(20)
/* frame engine counters */
#define MT7620_REG_MIB_OFFSET 0x1000
#define MT7620_PPE_AC_BCNT0 (MT7620_REG_MIB_OFFSET + 0x00)
#define MT7620_GDM1_TX_GBCNT (MT7620_REG_MIB_OFFSET + 0x300)
#define MT7620_GDM2_TX_GBCNT (MT7620_GDM1_TX_GBCNT + 0x40)
#define GSW_REG_GDMA1_MAC_ADRL 0x508
#define GSW_REG_GDMA1_MAC_ADRH 0x50C
#define MT7621_FE_RST_GL (FE_FE_OFFSET + 0x04)
#define MT7620_FE_INT_STATUS2 (FE_FE_OFFSET + 0x08)
/* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
* but after test it should be BIT(13).
*/
#define MT7620_FE_GDM1_AF BIT(13)
static const u16 mt7620_reg_table[FE_REG_COUNT] = {
[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
[FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
[FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
[FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
[FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
[FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
};
static int mt7620_gsw_config(struct fe_priv *priv)
{
struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
u32 val;
/* is the mt7530 internal or external */
if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, 0x1f)) {
mt7530_probe(priv->dev, gsw->base, NULL, 0);
mt7530_probe(priv->dev, NULL, priv->mii_bus, 1);
/* magic values from original SDK */
val = mt7530_mdio_r32(gsw, 0x7830);
val &= ~BIT(0);
val |= BIT(1);
mt7530_mdio_w32(gsw, 0x7830, val);
val = mt7530_mdio_r32(gsw, 0x7a40);
val &= ~BIT(30);
mt7530_mdio_w32(gsw, 0x7a40, val);
mt7530_mdio_w32(gsw, 0x7a78, 0x855);
pr_info("mt7530: mdio central align\n");
} else {
mt7530_probe(priv->dev, gsw->base, NULL, 1);
}
return 0;
}
static void mt7620_set_mac(struct fe_priv *priv, const unsigned char *mac)
{
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
unsigned long flags;
spin_lock_irqsave(&priv->page_lock, flags);
mtk_switch_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
mtk_switch_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
GSW_REG_SMACCR0);
spin_unlock_irqrestore(&priv->page_lock, flags);
}
static void mt7620_auto_poll(struct mt7620_gsw *gsw, int port)
{
int phy;
int lsb = -1, msb = 0;
for_each_set_bit(phy, &gsw->autopoll, 32) {
if (lsb < 0)
lsb = phy;
msb = phy;
}
if (lsb == msb && port == 4)
msb++;
else if (lsb == msb && port == 5)
lsb--;
mtk_switch_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) |
(msb << 8) | lsb, ESW_PHY_POLLING);
}
static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
{
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
const __be32 *_id = of_get_property(np, "reg", NULL);
const __be32 *phy_addr;
phy_interface_t phy_mode = PHY_INTERFACE_MODE_NA;
int size, id;
int shift = 12;
u32 val, mask = 0;
u32 val_delay = 0;
u32 mask_delay = GSW_REG_GPCx_TXDELAY | GSW_REG_GPCx_RXDELAY;
int min = (gsw->port4_ephy) ? (5) : (4);
if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
if (_id)
pr_err("%s: invalid port id %d\n", np->name,
be32_to_cpu(*_id));
else
pr_err("%s: invalid port id\n", np->name);
return;
}
id = be32_to_cpu(*_id);
if (id == 4)
shift = 14;
priv->phy->phy_fixed[id] = of_get_property(np, "mediatek,fixed-link",
&size);
if (priv->phy->phy_fixed[id] &&
(size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
pr_err("%s: invalid fixed link property\n", np->name);
priv->phy->phy_fixed[id] = NULL;
}
of_get_phy_mode(np, &phy_mode);
switch (phy_mode) {
case PHY_INTERFACE_MODE_RGMII:
mask = 0;
/* Do not touch rx/tx delay in this state to avoid problems with
* backward compability.
*/
mask_delay = 0;
break;
case PHY_INTERFACE_MODE_RGMII_ID:
mask = 0;
val_delay |= GSW_REG_GPCx_TXDELAY;
val_delay &= ~GSW_REG_GPCx_RXDELAY;
break;
case PHY_INTERFACE_MODE_RGMII_RXID:
mask = 0;
val_delay &= ~GSW_REG_GPCx_TXDELAY;
val_delay &= ~GSW_REG_GPCx_RXDELAY;
break;
case PHY_INTERFACE_MODE_RGMII_TXID:
mask = 0;
val_delay |= GSW_REG_GPCx_TXDELAY;
val_delay |= GSW_REG_GPCx_RXDELAY;
break;
case PHY_INTERFACE_MODE_MII:
mask = 1;
break;
case PHY_INTERFACE_MODE_RMII:
mask = 2;
break;
default:
dev_err(priv->dev, "port %d - invalid phy mode\n", id);
return;
}
val = rt_sysc_r32(SYSC_REG_CFG1);
val &= ~(3 << shift);
val |= mask << shift;
rt_sysc_w32(val, SYSC_REG_CFG1);
if (id == 4) {
val = mtk_switch_r32(gsw, GSW_REG_GPC2);
val &= ~(mask_delay);
val |= val_delay & mask_delay;
mtk_switch_w32(gsw, val, GSW_REG_GPC2);
}
else if (id == 5) {
val = mtk_switch_r32(gsw, GSW_REG_GPC1);
val &= ~(mask_delay);
val |= val_delay & mask_delay;
mtk_switch_w32(gsw, val, GSW_REG_GPC1);
}
if (priv->phy->phy_fixed[id]) {
const __be32 *link = priv->phy->phy_fixed[id];
int tx_fc, rx_fc;
u32 val = 0;
priv->phy->speed[id] = be32_to_cpup(link++);
tx_fc = be32_to_cpup(link++);
rx_fc = be32_to_cpup(link++);
priv->phy->duplex[id] = be32_to_cpup(link++);
priv->link[id] = 1;
switch (priv->phy->speed[id]) {
case SPEED_10:
val = 0;
break;
case SPEED_100:
val = 1;
break;
case SPEED_1000:
val = 2;
break;
default:
dev_err(priv->dev, "port %d - invalid link speed: %d\n",
id, priv->phy->speed[id]);
priv->phy->phy_fixed[id] = 0;
return;
}
val = PMCR_SPEED(val);
val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
if (tx_fc)
val |= PMCR_TX_FC;
if (rx_fc)
val |= PMCR_RX_FC;
if (priv->phy->duplex[id])
val |= PMCR_DUPLEX;
mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
dev_info(priv->dev, "port %d - using fixed link parameters\n", id);
return;
}
priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
if (!priv->phy->phy_node[id]) {
dev_err(priv->dev, "port %d - missing phy handle\n", id);
return;
}
phy_addr = of_get_property(priv->phy->phy_node[id], "reg", NULL);
if (phy_addr && mdiobus_get_phy(priv->mii_bus, be32_to_cpup(phy_addr))) {
u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
fe_connect_phy_node(priv, priv->phy->phy_node[id], id);
gsw->autopoll |= BIT(be32_to_cpup(phy_addr));
mt7620_auto_poll(gsw,id);
}
}
static void mt7620_rxcsum_config(bool enable)
{
if (enable)
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
GDMA_TCS_EN | GDMA_UCS_EN),
MT7620A_GDMA1_FWD_CFG);
else
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
GDMA_TCS_EN | GDMA_UCS_EN),
MT7620A_GDMA1_FWD_CFG);
}
static void mt7620_txcsum_config(bool enable)
{
if (enable)
fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
CDMA_UCS_EN | CDMA_TCS_EN),
MT7620A_CDMA_CSG_CFG);
else
fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
CDMA_UCS_EN | CDMA_TCS_EN),
MT7620A_CDMA_CSG_CFG);
}
static int mt7620_fwd_config(struct fe_priv *priv)
{
struct net_device *dev = priv_netdev(priv);
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
return 0;
}
static void mt7620_tx_dma(struct fe_tx_dma *txd)
{
}
static void mt7620_init_data(struct fe_soc_data *data,
struct net_device *netdev)
{
struct fe_priv *priv = netdev_priv(netdev);
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
FE_FLAG_RX_SG_DMA | FE_FLAG_HAS_SWITCH;
netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
NETIF_F_HW_VLAN_CTAG_TX;
if (mt7620_get_eco() >= 5)
netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
NETIF_F_IPV6_CSUM;
}
static struct fe_soc_data mt7620_data = {
.init_data = mt7620_init_data,
.set_mac = mt7620_set_mac,
.fwd_config = mt7620_fwd_config,
.tx_dma = mt7620_tx_dma,
.switch_init = mtk_gsw_init,
.switch_config = mt7620_gsw_config,
.port_init = mt7620_port_init,
.reg_table = mt7620_reg_table,
.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
.rx_int = RT5350_RX_DONE_INT,
.tx_int = RT5350_TX_DONE_INT,
.status_int = MT7620_FE_GDM1_AF,
.checksum_bit = MT7620_L4_VALID,
.has_carrier = mt7620_has_carrier,
.mdio_read = mt7620_mdio_read,
.mdio_write = mt7620_mdio_write,
.mdio_adjust_link = mt7620_mdio_link_adjust,
};
const struct of_device_id of_fe_match[] = {
{ .compatible = "mediatek,mt7620-eth", .data = &mt7620_data },
{},
};
MODULE_DEVICE_TABLE(of, of_fe_match);

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target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c Normal file
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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <asm/mach-ralink/ralink_regs.h>
#include "mtk_eth_soc.h"
#include "mdio_rt2880.h"
static void rt2880_init_data(struct fe_soc_data *data,
struct net_device *netdev)
{
struct fe_priv *priv = netdev_priv(netdev);
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;
netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX;
/* this should work according to the datasheet but actually does not*/
/* netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM; */
}
static int rt2880_fwd_config(struct fe_priv *priv)
{
int ret;
ret = fe_set_clock_cycle(priv);
if (ret)
return ret;
fe_fwd_config(priv);
fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
fe_csum_config(priv);
return ret;
}
struct fe_soc_data rt2880_data = {
.init_data = rt2880_init_data,
.fwd_config = rt2880_fwd_config,
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.checksum_bit = RX_DMA_L4VALID,
.rx_int = FE_RX_DONE_INT,
.tx_int = FE_TX_DONE_INT,
.status_int = FE_CNT_GDM_AF,
.mdio_read = rt2880_mdio_read,
.mdio_write = rt2880_mdio_write,
.mdio_adjust_link = rt2880_mdio_link_adjust,
.port_init = rt2880_port_init,
};
const struct of_device_id of_fe_match[] = {
{ .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
{},
};
MODULE_DEVICE_TABLE(of, of_fe_match);

146
target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt3050.c Normal file
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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <asm/mach-ralink/ralink_regs.h>
#include "mtk_eth_soc.h"
#include "esw_rt3050.h"
#include "mdio_rt2880.h"
static const u16 rt5350_reg_table[FE_REG_COUNT] = {
[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
[FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
[FE_REG_FE_RST_GL] = 0,
[FE_REG_FE_DMA_VID_BASE] = 0,
};
static void rt305x_init_data(struct fe_soc_data *data,
struct net_device *netdev)
{
struct fe_priv *priv = netdev_priv(netdev);
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
FE_FLAG_CALIBRATE_CLK | FE_FLAG_HAS_SWITCH;
netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
}
static int rt3050_fwd_config(struct fe_priv *priv)
{
int ret;
if (ralink_soc != RT305X_SOC_RT3052) {
ret = fe_set_clock_cycle(priv);
if (ret)
return ret;
}
fe_fwd_config(priv);
if (ralink_soc != RT305X_SOC_RT3352)
fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
fe_csum_config(priv);
return 0;
}
static void rt5350_init_data(struct fe_soc_data *data,
struct net_device *netdev)
{
struct fe_priv *priv = netdev_priv(netdev);
priv->flags = FE_FLAG_HAS_SWITCH;
netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM;
}
static void rt5350_set_mac(struct fe_priv *priv, const unsigned char *mac)
{
unsigned long flags;
spin_lock_irqsave(&priv->page_lock, flags);
fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
RT5350_SDM_MAC_ADRL);
spin_unlock_irqrestore(&priv->page_lock, flags);
}
static void rt5350_rxcsum_config(bool enable)
{
if (enable)
fe_w32(fe_r32(RT5350_SDM_CFG) | (RT5350_SDM_ICS_EN |
RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
RT5350_SDM_CFG);
else
fe_w32(fe_r32(RT5350_SDM_CFG) & ~(RT5350_SDM_ICS_EN |
RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
RT5350_SDM_CFG);
}
static int rt5350_fwd_config(struct fe_priv *priv)
{
struct net_device *dev = priv_netdev(priv);
rt5350_rxcsum_config((dev->features & NETIF_F_RXCSUM));
return 0;
}
static void rt5350_tx_dma(struct fe_tx_dma *txd)
{
txd->txd4 = 0;
}
static struct fe_soc_data rt3050_data = {
.init_data = rt305x_init_data,
.fwd_config = rt3050_fwd_config,
.switch_init = rt3050_esw_init,
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.checksum_bit = RX_DMA_L4VALID,
.rx_int = FE_RX_DONE_INT,
.tx_int = FE_TX_DONE_INT,
.status_int = FE_CNT_GDM_AF,
};
static struct fe_soc_data rt5350_data = {
.init_data = rt5350_init_data,
.reg_table = rt5350_reg_table,
.set_mac = rt5350_set_mac,
.fwd_config = rt5350_fwd_config,
.switch_init = rt3050_esw_init,
.tx_dma = rt5350_tx_dma,
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.checksum_bit = RX_DMA_L4VALID,
.rx_int = RT5350_RX_DONE_INT,
.tx_int = RT5350_TX_DONE_INT,
};
const struct of_device_id of_fe_match[] = {
{ .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
{},
};
MODULE_DEVICE_TABLE(of, of_fe_match);

67
target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt3883.c Normal file
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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <asm/mach-ralink/ralink_regs.h>
#include "mtk_eth_soc.h"
#include "mdio_rt2880.h"
static int rt3883_fwd_config(struct fe_priv *priv)
{
int ret;
ret = fe_set_clock_cycle(priv);
if (ret)
return ret;
fe_fwd_config(priv);
fe_w32(FE_PSE_FQFC_CFG_256Q, FE_PSE_FQ_CFG);
fe_csum_config(priv);
return ret;
}
static void rt3883_init_data(struct fe_soc_data *data,
struct net_device *netdev)
{
struct fe_priv *priv = netdev_priv(netdev);
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;
netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
}
static struct fe_soc_data rt3883_data = {
.init_data = rt3883_init_data,
.fwd_config = rt3883_fwd_config,
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.rx_int = FE_RX_DONE_INT,
.tx_int = FE_TX_DONE_INT,
.status_int = FE_CNT_GDM_AF,
.checksum_bit = RX_DMA_L4VALID,
.mdio_read = rt2880_mdio_read,
.mdio_write = rt2880_mdio_write,
.mdio_adjust_link = rt2880_mdio_link_adjust,
.port_init = rt2880_port_init,
};
const struct of_device_id of_fe_match[] = {
{ .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
{},
};
MODULE_DEVICE_TABLE(of, of_fe_match);