Initial commit

target/linux/starfive/patches-6.6/0042-pmdomain-starfive-Add-JH7110-AON-PMU-support.patch

@@ -0,0 +1,122 @@
+From 1bf849b606d0b4cae643f96685d3d3981643683d Mon Sep 17 00:00:00 2001
+From: Changhuang Liang <changhuang.liang@starfivetech.com>
+Date: Wed, 13 Sep 2023 14:54:28 +0100
+Subject: [PATCH 042/116] pmdomain: starfive: Add JH7110 AON PMU support
+
+Add AON PMU for StarFive JH7110 SoC. It can be used to turn on/off the
+dphy rx/tx power switch.
+
+Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
+Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
+Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
+Link: https://lore.kernel.org/r/20230913-dude-imprecise-fc32622bc947@spud
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/pmdomain/starfive/jh71xx-pmu.c | 57 +++++++++++++++++++++++---
+ 1 file changed, 52 insertions(+), 5 deletions(-)
+
+--- a/drivers/pmdomain/starfive/jh71xx-pmu.c
++++ b/drivers/pmdomain/starfive/jh71xx-pmu.c
+@@ -2,7 +2,7 @@
+ /*
+  * StarFive JH71XX PMU (Power Management Unit) Controller Driver
+  *
+- * Copyright (C) 2022 StarFive Technology Co., Ltd.
++ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
+  */
+ 
+ #include <linux/interrupt.h>
+@@ -24,6 +24,9 @@
+ #define JH71XX_PMU_EVENT_STATUS		0x88
+ #define JH71XX_PMU_INT_STATUS		0x8C
+ 
++/* aon pmu register offset */
++#define JH71XX_AON_PMU_SWITCH		0x00
++
+ /* sw encourage cfg */
+ #define JH71XX_PMU_SW_ENCOURAGE_EN_LO	0x05
+ #define JH71XX_PMU_SW_ENCOURAGE_EN_HI	0x50
+@@ -160,6 +163,26 @@ static int jh7110_pmu_set_state(struct j
+ 	return 0;
+ }
+ 
++static int jh7110_aon_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
++{
++	struct jh71xx_pmu *pmu = pmd->pmu;
++	unsigned long flags;
++	u32 val;
++
++	spin_lock_irqsave(&pmu->lock, flags);
++	val = readl(pmu->base + JH71XX_AON_PMU_SWITCH);
++
++	if (on)
++		val |= mask;
++	else
++		val &= ~mask;
++
++	writel(val, pmu->base + JH71XX_AON_PMU_SWITCH);
++	spin_unlock_irqrestore(&pmu->lock, flags);
++
++	return 0;
++}
++
+ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
+ {
+ 	struct jh71xx_pmu *pmu = pmd->pmu;
+@@ -317,10 +340,12 @@ static int jh71xx_pmu_probe(struct platf
+ 	if (!match_data)
+ 		return -EINVAL;
+ 
+-	ret = match_data->pmu_parse_irq(pdev, pmu);
+-	if (ret) {
+-		dev_err(dev, "failed to parse irq\n");
+-		return ret;
++	if (match_data->pmu_parse_irq) {
++		ret = match_data->pmu_parse_irq(pdev, pmu);
++		if (ret) {
++			dev_err(dev, "failed to parse irq\n");
++			return ret;
++		}
+ 	}
+ 
+ 	pmu->genpd = devm_kcalloc(dev, match_data->num_domains,
+@@ -394,11 +419,32 @@ static const struct jh71xx_pmu_match_dat
+ 	.pmu_set_state = jh7110_pmu_set_state,
+ };
+ 
++static const struct jh71xx_domain_info jh7110_aon_power_domains[] = {
++	[JH7110_PD_DPHY_TX] = {
++		.name = "DPHY-TX",
++		.bit = 30,
++	},
++	[JH7110_PD_DPHY_RX] = {
++		.name = "DPHY-RX",
++		.bit = 31,
++	},
++};
++
++static const struct jh71xx_pmu_match_data jh7110_aon_pmu = {
++	.num_domains = ARRAY_SIZE(jh7110_aon_power_domains),
++	.domain_info = jh7110_aon_power_domains,
++	.pmu_status = JH71XX_AON_PMU_SWITCH,
++	.pmu_set_state = jh7110_aon_pmu_set_state,
++};
++
+ static const struct of_device_id jh71xx_pmu_of_match[] = {
+ 	{
+ 		.compatible = "starfive,jh7110-pmu",
+ 		.data = (void *)&jh7110_pmu,
+ 	}, {
++		.compatible = "starfive,jh7110-aon-syscon",
++		.data = (void *)&jh7110_aon_pmu,
++	}, {
+ 		/* sentinel */
+ 	}
+ };
+@@ -414,5 +460,6 @@ static struct platform_driver jh71xx_pmu
+ builtin_platform_driver(jh71xx_pmu_driver);
+ 
+ MODULE_AUTHOR("Walker Chen <walker.chen@starfivetech.com>");
++MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+ MODULE_DESCRIPTION("StarFive JH71XX PMU Driver");
+ MODULE_LICENSE("GPL");