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@@ -0,0 +1,149 @@
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From 6cc4bcceff9af0e6be9738096d95e4ba75e75123 Mon Sep 17 00:00:00 2001
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From: Brandon Cheo Fusi <fusibrandon13@gmail.com>
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Date: Thu, 18 Apr 2024 16:44:04 +0100
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Subject: [PATCH] cpufreq: sun50i: Refactor speed bin decoding
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Make converting the speed bin value into a speed grade generic and
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determined by a platform specific callback. Also change the prototypes
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involved to encode the speed bin directly in the return value.
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This allows to extend the driver more easily to support more SoCs.
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Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com>
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[Andre: merge output into return value]
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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---
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drivers/cpufreq/sun50i-cpufreq-nvmem.c | 74 +++++++++++++++++---------
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1 file changed, 49 insertions(+), 25 deletions(-)
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--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
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+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
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@@ -25,19 +25,52 @@
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static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
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+struct sunxi_cpufreq_data {
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+ u32 (*efuse_xlate)(u32 speedbin);
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+};
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+
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+static u32 sun50i_h6_efuse_xlate(u32 speedbin)
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+{
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+ u32 efuse_value;
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+
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+ efuse_value = (speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
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+
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+ /*
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+ * We treat unexpected efuse values as if the SoC was from
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+ * the slowest bin. Expected efuse values are 1-3, slowest
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+ * to fastest.
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+ */
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+ if (efuse_value >= 1 && efuse_value <= 3)
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+ return efuse_value - 1;
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+ else
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+ return 0;
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+}
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+
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+static struct sunxi_cpufreq_data sun50i_h6_cpufreq_data = {
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+ .efuse_xlate = sun50i_h6_efuse_xlate,
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+};
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+
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+static const struct of_device_id cpu_opp_match_list[] = {
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+ { .compatible = "allwinner,sun50i-h6-operating-points",
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+ .data = &sun50i_h6_cpufreq_data,
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+ },
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+ {}
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+};
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+
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/**
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* sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
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- * @versions: Set to the value parsed from efuse
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*
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- * Returns 0 if success.
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+ * Returns non-negative speed bin index on success, a negative error
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+ * value otherwise.
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*/
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-static int sun50i_cpufreq_get_efuse(u32 *versions)
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+static int sun50i_cpufreq_get_efuse(void)
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{
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+ const struct sunxi_cpufreq_data *opp_data;
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struct nvmem_cell *speedbin_nvmem;
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+ const struct of_device_id *match;
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struct device_node *np;
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struct device *cpu_dev;
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- u32 *speedbin, efuse_value;
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- size_t len;
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+ u32 *speedbin;
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int ret;
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cpu_dev = get_cpu_device(0);
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@@ -48,12 +81,12 @@ static int sun50i_cpufreq_get_efuse(u32
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if (!np)
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return -ENOENT;
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- ret = of_device_is_compatible(np,
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- "allwinner,sun50i-h6-operating-points");
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- if (!ret) {
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+ match = of_match_node(cpu_opp_match_list, np);
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+ if (!match) {
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of_node_put(np);
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return -ENOENT;
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}
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+ opp_data = match->data;
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speedbin_nvmem = of_nvmem_cell_get(np, NULL);
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of_node_put(np);
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@@ -61,25 +94,16 @@ static int sun50i_cpufreq_get_efuse(u32
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return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem),
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"Could not get nvmem cell\n");
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- speedbin = nvmem_cell_read(speedbin_nvmem, &len);
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+ speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
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nvmem_cell_put(speedbin_nvmem);
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if (IS_ERR(speedbin))
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return PTR_ERR(speedbin);
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- efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
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-
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- /*
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- * We treat unexpected efuse values as if the SoC was from
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- * the slowest bin. Expected efuse values are 1-3, slowest
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- * to fastest.
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- */
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- if (efuse_value >= 1 && efuse_value <= 3)
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- *versions = efuse_value - 1;
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- else
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- *versions = 0;
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+ ret = opp_data->efuse_xlate(*speedbin);
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kfree(speedbin);
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- return 0;
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+
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+ return ret;
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};
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static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
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@@ -87,7 +111,7 @@ static int sun50i_cpufreq_nvmem_probe(st
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int *opp_tokens;
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char name[MAX_NAME_LEN];
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unsigned int cpu;
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- u32 speed = 0;
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+ int speed;
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int ret;
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opp_tokens = kcalloc(num_possible_cpus(), sizeof(*opp_tokens),
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@@ -95,10 +119,10 @@ static int sun50i_cpufreq_nvmem_probe(st
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if (!opp_tokens)
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return -ENOMEM;
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- ret = sun50i_cpufreq_get_efuse(&speed);
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- if (ret) {
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+ speed = sun50i_cpufreq_get_efuse();
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+ if (speed < 0) {
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kfree(opp_tokens);
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- return ret;
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+ return speed;
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}
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snprintf(name, MAX_NAME_LEN, "speed%d", speed);
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