c06fb25d1f
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62 lines
2.2 KiB
Diff
62 lines
2.2 KiB
Diff
From 0de9300833afc6b46d69c8d9584155a78c213f54 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Tue, 6 Feb 2024 19:59:13 +0000
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Subject: [PATCH 0885/1085] vc4/hvs: Support fixed alpha correctly on 2712D0
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2712D0 removed alpha_mode from control word 2 for choosing fixed alpha
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and replaced it with the previously reserved value of 3 in alpha_mask.
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Handle this to fix corrupt desktop when using X on 2712D0
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_plane.c | 17 ++++++++++++++++-
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drivers/gpu/drm/vc4/vc4_regs.h | 3 +++
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2 files changed, 19 insertions(+), 1 deletion(-)
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -1105,6 +1105,21 @@ static u32 vc4_hvs5_get_alpha_blend_mode
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}
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}
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+static u32 vc4_hvs6_get_alpha_mask_mode(struct drm_plane_state *state)
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+{
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+ struct drm_device *dev = state->state->dev;
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+ struct vc4_dev *vc4 = to_vc4_dev(dev);
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+
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+ WARN_ON_ONCE(vc4->gen != VC4_GEN_6);
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+
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+ if (vc4->step_d0 && (!state->fb->format->has_alpha ||
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+ state->pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE))
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+ return VC4_SET_FIELD(SCALER6_CTL0_ALPHA_MASK_FIXED,
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+ SCALER6_CTL0_ALPHA_MASK);
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+
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+ return VC4_SET_FIELD(SCALER6_CTL0_ALPHA_MASK_NONE, SCALER6_CTL0_ALPHA_MASK);
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+}
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+
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/* Writes out a full display list for an active plane to the plane's
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* private dlist state.
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*/
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@@ -1850,7 +1865,7 @@ static int vc6_plane_mode_set(struct drm
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vc4_dlist_write(vc4_state,
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SCALER6_CTL0_VALID |
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VC4_SET_FIELD(tiling, SCALER6_CTL0_ADDR_MODE) |
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- VC4_SET_FIELD(0, SCALER6_CTL0_ALPHA_MASK) |
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+ vc4_hvs6_get_alpha_mask_mode(state) |
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(vc4_state->is_unity ? SCALER6_CTL0_UNITY : 0) |
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VC4_SET_FIELD(format->pixel_order_hvs5, SCALER6_CTL0_ORDERRGBA) |
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VC4_SET_FIELD(scl1, SCALER6_CTL0_SCL1_MODE) |
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -1408,6 +1408,9 @@ enum hvs_pixel_format {
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#define SCALER6_CTL0_ADDR_MODE_UIF 4
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#define SCALER6_CTL0_ALPHA_MASK_MASK VC4_MASK(19, 18)
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+#define SCALER6_CTL0_ALPHA_MASK_NONE 0
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+#define SCALER6_CTL0_ALPHA_MASK_FIXED 3
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+
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#define SCALER6_CTL0_UNITY BIT(15)
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#define SCALER6_CTL0_ORDERRGBA_MASK VC4_MASK(14, 13)
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#define SCALER6_CTL0_SCL1_MODE_MASK VC4_MASK(10, 8)
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