c06fb25d1f
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36 lines
1.3 KiB
Diff
36 lines
1.3 KiB
Diff
From 3d21dabd055ca064880e775892a10c5e69fdf5e9 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Tue, 13 Aug 2024 17:18:51 +0100
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Subject: [PATCH 1227/1350] drm/vc4: Also power down the PLL core when
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resetting PHY
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The current reset code doesn't actually stop the hdmi output.
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That makes it difficult for displays to handle a mode set.
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Powering down the PLL does actually remove the hdmi signal
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and makes mode sets more reliable
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 2 ++
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1 file changed, 2 insertions(+)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
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@@ -137,6 +137,7 @@
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#define VC6_HDMI_TX_PHY_PLL_REFCLK_REFCLK_SEL_CMOS BIT(13)
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#define VC6_HDMI_TX_PHY_PLL_REFCLK_REFFRQ_MASK VC4_MASK(9, 0)
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+#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_BYPASS_EN BIT(4)
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#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_CLK0_SEL_MASK VC4_MASK(3, 2)
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#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_KDIV_MASK VC4_MASK(1, 0)
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@@ -947,6 +948,7 @@ static void vc6_hdmi_reset_phy(struct vc
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HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);
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HDMI_WRITE(HDMI_TX_PHY_POWERUP_CTL, 0);
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+ HDMI_WRITE(HDMI_TX_PHY_PLL_POST_KDIV, VC6_HDMI_TX_PHY_PLL_POST_KDIV_BYPASS_EN);
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}
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void vc6_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
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