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115 lines
3.8 KiB
Diff
115 lines
3.8 KiB
Diff
From 21a2802a8365cfa82cc02187c1f95136d85592ad Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Fri, 8 Dec 2023 15:51:59 +0100
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Subject: [PATCH 12/13] net: phy: at803x: move at8035 specific DT parse to
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dedicated probe
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Move at8035 specific DT parse for clock out frequency to dedicated probe
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to make at803x probe function more generic.
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This is to tidy code and no behaviour change are intended.
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Detection logic is changed, we check if the clk 25m mask is set and if
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it's not zero, we assume the qca,clk-out-frequency property is set.
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The property is checked in the generic at803x_parse_dt called by
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at803x_probe.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/phy/at803x.c | 60 +++++++++++++++++++++++++++-------------
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1 file changed, 41 insertions(+), 19 deletions(-)
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--- a/drivers/net/phy/at803x.c
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+++ b/drivers/net/phy/at803x.c
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@@ -638,23 +638,6 @@ static int at803x_parse_dt(struct phy_de
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priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
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priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
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-
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- /* Fixup for the AR8030/AR8035. This chip has another mask and
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- * doesn't support the DSP reference. Eg. the lowest bit of the
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- * mask. The upper two bits select the same frequencies. Mask
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- * the lowest bit here.
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- *
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- * Warning:
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- * There was no datasheet for the AR8030 available so this is
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- * just a guess. But the AR8035 is listed as pin compatible
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- * to the AR8030 so there might be a good chance it works on
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- * the AR8030 too.
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- */
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- if (phydev->drv->phy_id == ATH8030_PHY_ID ||
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- phydev->drv->phy_id == ATH8035_PHY_ID) {
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- priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
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- priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
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- }
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}
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ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
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@@ -1635,6 +1618,45 @@ static int at8031_config_intr(struct phy
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return at803x_config_intr(phydev);
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}
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+static int at8035_parse_dt(struct phy_device *phydev)
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+{
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+ struct at803x_priv *priv = phydev->priv;
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+
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+ /* Mask is set by the generic at803x_parse_dt
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+ * if property is set. Assume property is set
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+ * with the mask not zero.
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+ */
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+ if (priv->clk_25m_mask) {
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+ /* Fixup for the AR8030/AR8035. This chip has another mask and
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+ * doesn't support the DSP reference. Eg. the lowest bit of the
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+ * mask. The upper two bits select the same frequencies. Mask
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+ * the lowest bit here.
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+ *
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+ * Warning:
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+ * There was no datasheet for the AR8030 available so this is
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+ * just a guess. But the AR8035 is listed as pin compatible
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+ * to the AR8030 so there might be a good chance it works on
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+ * the AR8030 too.
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+ */
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+ priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
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+ priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
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+ }
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+
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+ return 0;
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+}
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+
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+/* AR8030 and AR8035 shared the same special mask for clk_25m */
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+static int at8035_probe(struct phy_device *phydev)
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+{
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+ int ret;
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+
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+ ret = at803x_probe(phydev);
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+ if (ret)
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+ return ret;
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+
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+ return at8035_parse_dt(phydev);
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+}
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+
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static int qca83xx_config_init(struct phy_device *phydev)
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{
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u8 switch_revision;
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@@ -2107,7 +2129,7 @@ static struct phy_driver at803x_driver[]
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PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
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.name = "Qualcomm Atheros AR8035",
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.flags = PHY_POLL_CABLE_TEST,
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- .probe = at803x_probe,
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+ .probe = at8035_probe,
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.config_aneg = at803x_config_aneg,
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.config_init = at803x_config_init,
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.soft_reset = genphy_soft_reset,
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@@ -2128,7 +2150,7 @@ static struct phy_driver at803x_driver[]
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.phy_id = ATH8030_PHY_ID,
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.name = "Qualcomm Atheros AR8030",
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.phy_id_mask = AT8030_PHY_ID_MASK,
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- .probe = at803x_probe,
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+ .probe = at8035_probe,
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.config_init = at803x_config_init,
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.link_change_notify = at803x_link_change_notify,
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.set_wol = at803x_set_wol,
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