c06fb25d1f
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52 lines
1.7 KiB
Diff
52 lines
1.7 KiB
Diff
From 9c7a86c935074525f24cc20e78a7d5150e4600e3 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Tue, 9 Jul 2024 00:23:04 +0200
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Subject: [PATCH] MIPS: lantiq: improve USB initialization
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This adds code to initialize the USB controller and PHY also on Danube,
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Amazon SE and AR10. This code is based on the Vendor driver from
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different UGW versions and compared to the hardware documentation.
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This patch is included in OpenWrt for many years.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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arch/mips/lantiq/xway/sysctrl.c | 20 ++++++++++++++++++++
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1 file changed, 20 insertions(+)
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -247,6 +247,25 @@ static void pmu_disable(struct clk *clk)
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pr_warn("deactivating PMU module failed!");
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}
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+static void usb_set_clock(void)
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+{
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+ unsigned int val = ltq_cgu_r32(ifccr);
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+
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+ if (of_machine_is_compatible("lantiq,ar10") ||
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+ of_machine_is_compatible("lantiq,grx390")) {
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+ val &= ~0x03; /* XTAL divided by 3 */
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+ } else if (of_machine_is_compatible("lantiq,ar9") ||
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+ of_machine_is_compatible("lantiq,vr9")) {
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+ /* TODO: this depends on the XTAL frequency */
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+ val |= 0x03; /* XTAL divided by 3 */
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+ } else if (of_machine_is_compatible("lantiq,ase")) {
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+ val |= 0x20; /* from XTAL */
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+ } else if (of_machine_is_compatible("lantiq,danube")) {
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+ val |= 0x30; /* 12 MHz, generated from 36 MHz */
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+ }
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+ ltq_cgu_w32(val, ifccr);
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+}
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+
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/* the pci enable helper */
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static int pci_enable(struct clk *clk)
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{
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@@ -588,4 +607,5 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
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clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
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}
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+ usb_set_clock();
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}
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