c06fb25d1f
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33 lines
1.2 KiB
Diff
33 lines
1.2 KiB
Diff
From bc1bb265f504ea19ce611a1aec1a40dec409cd15 Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Wed, 18 Sep 2024 15:32:55 +0200
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Subject: [PATCH 4/4] phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions
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Fix the following register definitions for REG_CSR_2L_RX{0,1}_REV0
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registers:
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- CSR_2L_PXP_VOS_PNINV
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- CSR_2L_PXP_FE_GAIN_NORMAL_MODE
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- CSR_2L_PXP_FE_GAIN_TRAIN_MODE
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Fixes: d7d2818b9383 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.")
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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---
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drivers/phy/phy-airoha-pcie-regs.h | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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--- a/drivers/phy/phy-airoha-pcie-regs.h
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+++ b/drivers/phy/phy-airoha-pcie-regs.h
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@@ -197,9 +197,9 @@
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#define CSR_2L_PXP_TX1_MULTLANE_EN BIT(0)
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#define REG_CSR_2L_RX0_REV0 0x00fc
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-#define CSR_2L_PXP_VOS_PNINV GENMASK(3, 2)
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-#define CSR_2L_PXP_FE_GAIN_NORMAL_MODE GENMASK(6, 4)
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-#define CSR_2L_PXP_FE_GAIN_TRAIN_MODE GENMASK(10, 8)
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+#define CSR_2L_PXP_VOS_PNINV GENMASK(19, 18)
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+#define CSR_2L_PXP_FE_GAIN_NORMAL_MODE GENMASK(22, 20)
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+#define CSR_2L_PXP_FE_GAIN_TRAIN_MODE GENMASK(26, 24)
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#define REG_CSR_2L_RX0_PHYCK_DIV 0x0100
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#define CSR_2L_PXP_RX0_PHYCK_SEL GENMASK(9, 8)
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