c06fb25d1f
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29 lines
1.0 KiB
Diff
29 lines
1.0 KiB
Diff
From f0537b9db29afd851323e4b7d7ae3156d6bfb1b6 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Mon, 13 May 2024 15:40:02 +0100
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Subject: [PATCH 1087/1135] spi: dw: Handle any number of gpiod CS lines
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Even when configured to use only gpiod CS lines, the DW SPI controller
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still expects a bit to be set in the SER register, otherwise transfers
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stall. For the csgpiod case, nominate bit 0 for the job.
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See: https://github.com/raspberrypi/linux/issues/6159
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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---
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drivers/spi/spi-dw-core.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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--- a/drivers/spi/spi-dw-core.c
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+++ b/drivers/spi/spi-dw-core.c
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@@ -98,7 +98,8 @@ void dw_spi_set_cs(struct spi_device *sp
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* support active-high or active-low CS level.
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*/
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if (cs_high == enable)
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- dw_writel(dws, DW_SPI_SER, BIT(spi_get_chipselect(spi, 0)));
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+ dw_writel(dws, DW_SPI_SER,
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+ BIT(spi_get_csgpiod(spi, 0) ? 0 : spi_get_chipselect(spi, 0)));
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else
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dw_writel(dws, DW_SPI_SER, 0);
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}
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