c06fb25d1f
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93 lines
4.0 KiB
Diff
93 lines
4.0 KiB
Diff
From 9a108c82b6f6526e0aa8a19befa1ed3f31f8fe52 Mon Sep 17 00:00:00 2001
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From: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
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Date: Fri, 10 May 2024 15:42:29 +0100
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Subject: [PATCH 1178/1215] dts: rp1: DSI drivers to use newly defined MIPI
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byte source clocks.
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Remove the "dummy" 72MHz fixed clock sources and associate DSI driver
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with the new "variable" clock sources now defined in RP1 clocks.
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Also add PLLSYS clock to DSI, which it will need as an alternative
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clock source in those cases where DPI pixclock > DSI byteclock.
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Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
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---
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arch/arm/boot/dts/broadcom/rp1.dtsi | 50 +++++++++--------------------
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1 file changed, 15 insertions(+), 35 deletions(-)
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--- a/arch/arm/boot/dts/broadcom/rp1.dtsi
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+++ b/arch/arm/boot/dts/broadcom/rp1.dtsi
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@@ -1109,16 +1109,15 @@
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interrupts = <RP1_INT_MIPI0 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>, // required, config bus clock
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- <&rp1_clocks RP1_CLK_MIPI0_DPI>, // required, pixel clock
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- <&clksrc_mipi0_dsi_byteclk>, // internal, parent for divide
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- <&clk_xosc>; // hardwired to DSI "refclk"
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- clock-names = "cfgclk", "dpiclk", "byteclk", "refclk";
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+ clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>,
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+ <&rp1_clocks RP1_CLK_MIPI0_DPI>,
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+ <&rp1_clocks RP1_CLK_MIPI0_DSI_BYTECLOCK>,
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+ <&clk_xosc>, // hardwired to DSI "refclk"
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+ <&rp1_clocks RP1_PLL_SYS>; // alternate parent for divide
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+ clock-names = "cfgclk", "dpiclk", "byteclk", "refclk", "pllsys";
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- assigned-clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>,
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- <&rp1_clocks RP1_CLK_MIPI0_DPI>;
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+ assigned-clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>;
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assigned-clock-rates = <25000000>;
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- assigned-clock-parents = <0>, <&clksrc_mipi0_dsi_byteclk>;
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};
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rp1_dsi1: dsi@128000 {
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@@ -1130,16 +1129,15 @@
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interrupts = <RP1_INT_MIPI1 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>, // required, config bus clock
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- <&rp1_clocks RP1_CLK_MIPI1_DPI>, // required, pixel clock
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- <&clksrc_mipi1_dsi_byteclk>, // internal, parent for divide
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- <&clk_xosc>; // hardwired to DSI "refclk"
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- clock-names = "cfgclk", "dpiclk", "byteclk", "refclk";
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+ clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>,
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+ <&rp1_clocks RP1_CLK_MIPI1_DPI>,
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+ <&rp1_clocks RP1_CLK_MIPI1_DSI_BYTECLOCK>,
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+ <&clk_xosc>, // hardwired to DSI "refclk"
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+ <&rp1_clocks RP1_PLL_SYS>; // alternate parent for divide
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+ clock-names = "cfgclk", "dpiclk", "byteclk", "refclk", "pllsys";
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- assigned-clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>,
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- <&rp1_clocks RP1_CLK_MIPI1_DPI>;
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+ assigned-clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>;
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assigned-clock-rates = <25000000>;
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- assigned-clock-parents = <0>, <&clksrc_mipi1_dsi_byteclk>;
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};
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/* VEC and DPI both need to control PLL_VIDEO and cannot work together; */
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@@ -1216,24 +1214,6 @@
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clock-output-names = "core";
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clock-frequency = <50000000>;
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};
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- clksrc_mipi0_dsi_byteclk: clksrc_mipi0_dsi_byteclk {
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- // This clock is synthesized by MIPI0 D-PHY, when DSI is running.
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- // Its frequency is not known a priori (until a panel driver attaches)
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- // so assign a made-up frequency of 72MHz so it can be divided for DPI.
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- compatible = "fixed-clock";
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- #clock-cells = <0>;
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- clock-output-names = "clksrc_mipi0_dsi_byteclk";
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- clock-frequency = <72000000>;
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- };
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- clksrc_mipi1_dsi_byteclk: clksrc_mipi1_dsi_byteclk {
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- // This clock is synthesized by MIPI1 D-PHY, when DSI is running.
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- // Its frequency is not known a priori (until a panel driver attaches)
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- // so assign a made-up frequency of 72MHz so it can be divided for DPI.
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- compatible = "fixed-clock";
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- #clock-cells = <0>;
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- clock-output-names = "clksrc_mipi1_dsi_byteclk";
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- clock-frequency = <72000000>;
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- };
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/* GPIO derived clock sources. Each GPIO with a GPCLK function
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* can drive its output from the respective GPCLK
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* generator, and provide a clock source to other internal
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