c06fb25d1f
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205 lines
6.6 KiB
Diff
205 lines
6.6 KiB
Diff
From 485d11cfa7df2d2deb39c9b3455cebcb1a85cea2 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Thu, 25 Jul 2024 14:36:32 +0100
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Subject: [PATCH 1199/1215] drm/vc4: Disable the 2pixel/clock odd timings
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workaround for interlaced
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Whilst BCM2712 does fix using odd horizontal timings, it doesn't
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work with interlaced modes.
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Drop the workaround for interlaced modes and revert to the same
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behaviour as BCM2711.
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https://github.com/raspberrypi/linux/issues/6281
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 20 +++++++++++++++++---
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drivers/gpu/drm/vc4/vc4_drv.h | 2 ++
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drivers/gpu/drm/vc4/vc4_hdmi.c | 8 +++++++-
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drivers/gpu/drm/vc4/vc4_hdmi.h | 4 ++++
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4 files changed, 30 insertions(+), 4 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -378,7 +378,9 @@ static void vc4_crtc_config_pv(struct dr
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bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;
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bool is_vec = vc4_encoder->type == VC4_ENCODER_TYPE_VEC;
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u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
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- u8 ppc = pv_data->pixels_per_clock;
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+ u8 ppc = (mode->flags & DRM_MODE_FLAG_INTERLACE) ?
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+ pv_data->pixels_per_clock_int :
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+ pv_data->pixels_per_clock;
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u16 vert_bp = mode->crtc_vtotal - mode->crtc_vsync_end;
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u16 vert_sync = mode->crtc_vsync_end - mode->crtc_vsync_start;
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@@ -443,7 +445,8 @@ static void vc4_crtc_config_pv(struct dr
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*/
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CRTC_WRITE(PV_V_CONTROL,
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PV_VCONTROL_CONTINUOUS |
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- (vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
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+ (vc4->gen >= VC4_GEN_6 && ppc == 1 ?
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+ PV_VCONTROL_ODD_TIMING : 0) |
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(is_dsi ? PV_VCONTROL_DSI : 0) |
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PV_VCONTROL_INTERLACE |
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(odd_field_first
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@@ -455,7 +458,8 @@ static void vc4_crtc_config_pv(struct dr
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} else {
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CRTC_WRITE(PV_V_CONTROL,
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PV_VCONTROL_CONTINUOUS |
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- (vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
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+ (vc4->gen >= VC4_GEN_6 && ppc == 1 ?
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+ PV_VCONTROL_ODD_TIMING : 0) |
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(is_dsi ? PV_VCONTROL_DSI : 0));
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CRTC_WRITE(PV_VSYNCD_EVEN, 0);
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}
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@@ -1223,6 +1227,7 @@ const struct vc4_pv_data bcm2835_pv0_dat
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},
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.fifo_depth = 64,
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.pixels_per_clock = 1,
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+ .pixels_per_clock_int = 1,
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.encoder_types = {
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[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
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[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
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@@ -1238,6 +1243,7 @@ const struct vc4_pv_data bcm2835_pv1_dat
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},
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.fifo_depth = 64,
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.pixels_per_clock = 1,
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+ .pixels_per_clock_int = 1,
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.encoder_types = {
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[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
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[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
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@@ -1253,6 +1259,7 @@ const struct vc4_pv_data bcm2835_pv2_dat
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},
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.fifo_depth = 64,
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.pixels_per_clock = 1,
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+ .pixels_per_clock_int = 1,
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.encoder_types = {
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[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
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[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
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@@ -1268,6 +1275,7 @@ const struct vc4_pv_data bcm2711_pv0_dat
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},
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.fifo_depth = 64,
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.pixels_per_clock = 1,
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+ .pixels_per_clock_int = 1,
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.encoder_types = {
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[0] = VC4_ENCODER_TYPE_DSI0,
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[1] = VC4_ENCODER_TYPE_DPI,
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@@ -1283,6 +1291,7 @@ const struct vc4_pv_data bcm2711_pv1_dat
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},
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.fifo_depth = 64,
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.pixels_per_clock = 1,
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+ .pixels_per_clock_int = 1,
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.encoder_types = {
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[0] = VC4_ENCODER_TYPE_DSI1,
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[1] = VC4_ENCODER_TYPE_SMI,
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@@ -1298,6 +1307,7 @@ const struct vc4_pv_data bcm2711_pv2_dat
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},
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.fifo_depth = 256,
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.pixels_per_clock = 2,
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+ .pixels_per_clock_int = 2,
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.encoder_types = {
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[0] = VC4_ENCODER_TYPE_HDMI0,
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},
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@@ -1312,6 +1322,7 @@ const struct vc4_pv_data bcm2711_pv3_dat
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},
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.fifo_depth = 64,
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.pixels_per_clock = 1,
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+ .pixels_per_clock_int = 1,
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.encoder_types = {
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[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
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},
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@@ -1326,6 +1337,7 @@ const struct vc4_pv_data bcm2711_pv4_dat
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},
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.fifo_depth = 64,
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.pixels_per_clock = 2,
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+ .pixels_per_clock_int = 2,
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.encoder_types = {
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[0] = VC4_ENCODER_TYPE_HDMI1,
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},
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@@ -1339,6 +1351,7 @@ const struct vc4_pv_data bcm2712_pv0_dat
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},
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.fifo_depth = 64,
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.pixels_per_clock = 1,
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+ .pixels_per_clock_int = 2,
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.encoder_types = {
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[0] = VC4_ENCODER_TYPE_HDMI0,
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},
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@@ -1352,6 +1365,7 @@ const struct vc4_pv_data bcm2712_pv1_dat
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},
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.fifo_depth = 64,
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.pixels_per_clock = 1,
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+ .pixels_per_clock_int = 2,
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.encoder_types = {
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[0] = VC4_ENCODER_TYPE_HDMI1,
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},
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -570,6 +570,8 @@ struct vc4_pv_data {
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/* Number of pixels output per clock period */
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u8 pixels_per_clock;
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+ /* Number of pixels output per clock period when in an interlaced mode */
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+ u8 pixels_per_clock_int;
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enum vc4_encoder_type encoder_types[4];
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};
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -2269,7 +2269,9 @@ static int vc4_hdmi_encoder_atomic_check
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unsigned long long tmds_bit_rate;
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int ret;
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- if (vc4_hdmi->variant->unsupported_odd_h_timings) {
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+ if (vc4_hdmi->variant->unsupported_odd_h_timings ||
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+ (vc4_hdmi->variant->unsupported_int_odd_h_timings &&
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+ (mode->flags & DRM_MODE_FLAG_INTERLACE))) {
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if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
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/* Only try to fixup DBLCLK modes to get 480i and 576i
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* working.
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@@ -3980,6 +3982,7 @@ static const struct vc4_hdmi_variant bcm
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PHY_LANE_CK,
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},
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.unsupported_odd_h_timings = true,
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+ .unsupported_int_odd_h_timings = true,
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.external_irq_controller = true,
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.init_resources = vc5_hdmi_init_resources,
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@@ -4009,6 +4012,7 @@ static const struct vc4_hdmi_variant bcm
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PHY_LANE_2,
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},
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.unsupported_odd_h_timings = true,
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+ .unsupported_int_odd_h_timings = true,
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.external_irq_controller = true,
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.init_resources = vc5_hdmi_init_resources,
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@@ -4038,6 +4042,7 @@ static const struct vc4_hdmi_variant bcm
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PHY_LANE_CK,
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},
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.unsupported_odd_h_timings = false,
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+ .unsupported_int_odd_h_timings = true,
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.external_irq_controller = true,
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.init_resources = vc5_hdmi_init_resources,
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@@ -4065,6 +4070,7 @@ static const struct vc4_hdmi_variant bcm
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PHY_LANE_CK,
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},
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.unsupported_odd_h_timings = false,
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+ .unsupported_int_odd_h_timings = true,
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.external_irq_controller = true,
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.init_resources = vc5_hdmi_init_resources,
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
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@@ -49,6 +49,10 @@ struct vc4_hdmi_variant {
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/* The BCM2711 cannot deal with odd horizontal pixel timings */
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bool unsupported_odd_h_timings;
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+ /* The BCM2712 can handle odd horizontal pixel timings, but not in
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+ * interlaced modes
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+ */
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+ bool unsupported_int_odd_h_timings;
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/*
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* The BCM2711 CEC/hotplug IRQ controller is shared between the
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