c06fb25d1f
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27 lines
1.1 KiB
Diff
27 lines
1.1 KiB
Diff
From e9294823cf02068189a0e901223ed4991923c689 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Wed, 31 Jul 2024 10:55:19 +0100
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Subject: [PATCH 1202/1215] spi: dw: Clamp the minimum clock speed
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The DW SPI interface has a 16-bit clock divider, where the bottom bit
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of the divisor must be 0. Limit how low the clock speed can go to
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prevent the clock divider from being truncated, as that could lead to
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a much higher clock rate than requested.
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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---
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drivers/spi/spi-dw-core.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/spi/spi-dw-core.c
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+++ b/drivers/spi/spi-dw-core.c
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@@ -397,7 +397,7 @@ void dw_spi_update_config(struct dw_spi
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dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0);
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/* Note DW APB SSI clock divider doesn't support odd numbers */
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- clk_div = (DIV_ROUND_UP(dws->max_freq, cfg->freq) + 1) & 0xfffe;
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+ clk_div = min(DIV_ROUND_UP(dws->max_freq, cfg->freq) + 1, 0xfffe) & 0xfffe;
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speed_hz = dws->max_freq / clk_div;
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if (dws->current_freq != speed_hz) {
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