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70 lines
1.7 KiB
Diff
70 lines
1.7 KiB
Diff
From 98f3b5f44b9ae86c4a80185b57149867472a2570 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Fri, 20 Oct 2023 15:11:41 +0200
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Subject: [PATCH] ARM: dts: usr8200: Fix phy registers
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The MV88E6060 switch has internal PHY registers at MDIO
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addresses 0x00..0x04. Tie each port to the corresponding
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PHY.
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Link: https://lore.kernel.org/r/20231020-ixp4xx-usr8200-dtsfix-v1-1-3a8591dea259@linaro.org
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Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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---
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.../ixp/intel-ixp42x-usrobotics-usr8200.dts | 22 +++++++++++++++++++
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1 file changed, 22 insertions(+)
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--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
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+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
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@@ -165,6 +165,24 @@
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#address-cells = <1>;
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#size-cells = <0>;
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+ /*
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+ * PHY 0..4 are internal to the MV88E6060 switch but appear
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+ * as independent devices.
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+ */
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+ phy0: ethernet-phy@0 {
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+ reg = <0>;
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+ };
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+ phy1: ethernet-phy@1 {
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+ reg = <1>;
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+ };
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+ phy2: ethernet-phy@2 {
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+ reg = <2>;
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+ };
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+ phy3: ethernet-phy@3 {
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+ reg = <3>;
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+ };
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+
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+ /* Altima AMI101L used by the WAN port */
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phy9: ethernet-phy@9 {
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reg = <9>;
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};
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@@ -181,21 +199,25 @@
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port@0 {
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reg = <0>;
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label = "lan1";
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+ phy-handle = <&phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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+ phy-handle = <&phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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+ phy-handle = <&phy2>;
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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+ phy-handle = <&phy3>;
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};
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port@5 {
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