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1118 lines
29 KiB
C
1118 lines
29 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* FILE NAME: en8801sc.c
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* PURPOSE:
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* EN8801SC phy driver for Linux
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* NOTES:
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*
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*/
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/* INCLUDE FILE DECLARATIONS
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*/
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/unistd.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/delay.h>
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#include <linux/uaccess.h>
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#include <linux/version.h>
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#include "en8801sc.h"
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MODULE_DESCRIPTION("Airoha EN8801S PHY drivers for MediaTek SoC");
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MODULE_AUTHOR("Airoha");
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MODULE_LICENSE("GPL");
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#define airoha_mdio_lock(bus) mutex_lock(&((bus)->mdio_lock))
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#define airoha_mdio_unlock(bus) mutex_unlock(&((bus)->mdio_lock))
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#define phydev_mdio_bus(_dev) (_dev->mdio.bus)
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#define phydev_phy_addr(_dev) (_dev->mdio.addr)
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#define phydev_dev(_dev) (&_dev->mdio.dev)
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#define phydev_pbus_addr(dev) ((dev)->mdio.addr + 1)
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enum {
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PHY_STATE_DONE = 0,
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PHY_STATE_INIT = 1,
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PHY_STATE_PROCESS = 2,
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PHY_STATE_FAIL = 3,
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};
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struct en8801s_priv {
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bool first_init;
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u16 count;
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u16 pro_version;
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};
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/*
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The following led_cfg example is for reference only.
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LED5 1000M/LINK/ACT (GPIO5) <-> BASE_T_LED0,
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LED6 10/100M/LINK/ACT (GPIO9) <-> BASE_T_LED1,
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LED4 100M/LINK/ACT (GPIO8) <-> BASE_T_LED2,
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*/
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/* User-defined.B */
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#define AIR_LED_SUPPORT
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#ifdef AIR_LED_SUPPORT
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static const struct AIR_BASE_T_LED_CFG_S led_cfg[4] = {
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/*
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* {LED Enable, GPIO, LED Polarity, LED ON, LED Blink}
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*/
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/* BASE-T LED0 */
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{LED_ENABLE, 5, AIR_ACTIVE_LOW,
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BASE_T_LED0_ON_CFG, BASE_T_LED0_BLK_CFG},
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/* BASE-T LED1 */
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{LED_ENABLE, 9, AIR_ACTIVE_LOW,
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BASE_T_LED1_ON_CFG, BASE_T_LED1_BLK_CFG},
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/* BASE-T LED2 */
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{LED_ENABLE, 8, AIR_ACTIVE_LOW,
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BASE_T_LED2_ON_CFG, BASE_T_LED2_BLK_CFG},
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/* BASE-T LED3 */
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{LED_DISABLE, 1, AIR_ACTIVE_LOW,
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BASE_T_LED3_ON_CFG, BASE_T_LED3_BLK_CFG},
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};
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static const u16 led_dur = UNIT_LED_BLINK_DURATION << AIR_LED_BLK_DUR_64M;
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#endif
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/* User-defined.E */
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/************************************************************************
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* F U N C T I O N S
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************************************************************************/
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static int en8801s_phase2_init(struct phy_device *phydev);
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static int __airoha_cl45_write(struct mii_bus *bus, int port,
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u32 devad, u32 reg, u16 val)
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{
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int ret = 0;
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struct device *dev = &bus->dev;
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ret = __mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG, devad);
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if (ret < 0) {
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dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
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return ret;
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}
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ret = __mdiobus_write(bus, port, MII_MMD_ADDR_DATA_REG, reg);
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if (ret < 0) {
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dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
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return ret;
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}
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ret = __mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG,
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MMD_OP_MODE_DATA | devad);
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if (ret < 0) {
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dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
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return ret;
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}
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ret = __mdiobus_write(bus, port, MII_MMD_ADDR_DATA_REG, val);
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if (ret < 0) {
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dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
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return ret;
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}
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return ret;
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}
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static int __airoha_cl45_read(struct mii_bus *bus, int port,
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u32 devad, u32 reg, u16 *read_data)
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{
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int ret = 0;
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struct device *dev = &bus->dev;
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ret = __mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG, devad);
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if (ret < 0) {
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dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
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return ret;
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}
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ret = __mdiobus_write(bus, port, MII_MMD_ADDR_DATA_REG, reg);
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if (ret < 0) {
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dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
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return ret;
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}
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ret = __mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG,
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MMD_OP_MODE_DATA | devad);
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if (ret < 0) {
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dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
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return ret;
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}
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*read_data = __mdiobus_read(bus, port, MII_MMD_ADDR_DATA_REG);
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return ret;
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}
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static int airoha_cl45_write(struct mii_bus *bus, int port,
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u32 devad, u32 reg, u16 val)
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{
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int ret = 0;
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airoha_mdio_lock(bus);
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ret = __airoha_cl45_write(bus, port, devad, reg, val);
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airoha_mdio_unlock(bus);
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return ret;
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}
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static int airoha_cl45_read(struct mii_bus *bus, int port,
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u32 devad, u32 reg, u16 *read_data)
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{
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int ret = 0;
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airoha_mdio_lock(bus);
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ret = __airoha_cl45_read(bus, port, devad, reg, read_data);
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airoha_mdio_unlock(bus);
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return ret;
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}
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static int __airoha_pbus_write(struct mii_bus *ebus, int pbus_id,
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unsigned long pbus_address, unsigned long pbus_data)
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{
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int ret = 0;
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ret = __mdiobus_write(ebus, pbus_id, 0x1F,
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(unsigned int)(pbus_address >> 6));
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if (ret < 0)
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return ret;
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ret = __mdiobus_write(ebus, pbus_id,
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(unsigned int)((pbus_address >> 2) & 0xf),
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(unsigned int)(pbus_data & 0xFFFF));
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if (ret < 0)
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return ret;
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ret = __mdiobus_write(ebus, pbus_id, 0x10,
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(unsigned int)(pbus_data >> 16));
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if (ret < 0)
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return ret;
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return ret;
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}
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static unsigned long __airoha_pbus_read(struct mii_bus *ebus, int pbus_id,
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unsigned long pbus_address)
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{
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unsigned long pbus_data;
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unsigned int pbus_data_low, pbus_data_high;
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int ret = 0;
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struct device *dev = &ebus->dev;
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ret = __mdiobus_write(ebus, pbus_id, 0x1F,
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(unsigned int)(pbus_address >> 6));
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if (ret < 0) {
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dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
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return INVALID_DATA;
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}
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pbus_data_low = __mdiobus_read(ebus, pbus_id,
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(unsigned int)((pbus_address >> 2) & 0xf));
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pbus_data_high = __mdiobus_read(ebus, pbus_id, 0x10);
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pbus_data = (pbus_data_high << 16) + pbus_data_low;
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return pbus_data;
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}
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static int airoha_pbus_write(struct mii_bus *ebus, int pbus_id,
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unsigned long pbus_address, unsigned long pbus_data)
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{
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int ret = 0;
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airoha_mdio_lock(ebus);
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ret = __airoha_pbus_write(ebus, pbus_id, pbus_address, pbus_data);
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airoha_mdio_unlock(ebus);
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return ret;
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}
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static unsigned long airoha_pbus_read(struct mii_bus *ebus, int pbus_id,
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unsigned long pbus_address)
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{
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unsigned long pbus_data;
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airoha_mdio_lock(ebus);
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pbus_data = __airoha_pbus_read(ebus, pbus_id, pbus_address);
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airoha_mdio_unlock(ebus);
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return pbus_data;
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}
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/* Airoha Token Ring Write function */
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static int airoha_tr_reg_write(struct phy_device *phydev,
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unsigned long tr_address, unsigned long tr_data)
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{
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int ret = 0;
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int phy_addr = phydev_phy_addr(phydev);
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struct mii_bus *ebus = phydev_mdio_bus(phydev);
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airoha_mdio_lock(ebus);
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ret = __mdiobus_write(ebus, phy_addr, 0x1F, 0x52b5); /* page select */
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ret = __mdiobus_write(ebus, phy_addr, 0x11,
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(unsigned int)(tr_data & 0xffff));
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ret = __mdiobus_write(ebus, phy_addr, 0x12,
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(unsigned int)(tr_data >> 16));
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ret = __mdiobus_write(ebus, phy_addr, 0x10,
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(unsigned int)(tr_address | TrReg_WR));
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ret = __mdiobus_write(ebus, phy_addr, 0x1F, 0x0); /* page resetore */
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airoha_mdio_unlock(ebus);
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return ret;
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}
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#ifdef AIR_LED_SUPPORT
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static int airoha_led_set_usr_def(struct phy_device *phydev, u8 entity,
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int polar, u16 on_evt, u16 blk_evt)
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{
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int ret = 0;
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int phy_addr = phydev_phy_addr(phydev);
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struct mii_bus *mbus = phydev_mdio_bus(phydev);
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if (polar == AIR_ACTIVE_HIGH)
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on_evt |= LED_ON_POL;
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else
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on_evt &= ~LED_ON_POL;
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ret = airoha_cl45_write(mbus, phy_addr, 0x1f,
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LED_ON_CTRL(entity), on_evt | LED_ON_EN);
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if (ret < 0)
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return ret;
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ret = airoha_cl45_write(mbus, phy_addr, 0x1f,
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LED_BLK_CTRL(entity), blk_evt);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int airoha_led_set_mode(struct phy_device *phydev, u8 mode)
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{
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u16 cl45_data;
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int err = 0;
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int phy_addr = phydev_phy_addr(phydev);
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struct mii_bus *mbus = phydev_mdio_bus(phydev);
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err = airoha_cl45_read(mbus, phy_addr, 0x1f, LED_BCR, &cl45_data);
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if (err < 0)
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return err;
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switch (mode) {
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case AIR_LED_MODE_DISABLE:
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cl45_data &= ~LED_BCR_EXT_CTRL;
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cl45_data &= ~LED_BCR_MODE_MASK;
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cl45_data |= LED_BCR_MODE_DISABLE;
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break;
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case AIR_LED_MODE_USER_DEFINE:
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cl45_data |= LED_BCR_EXT_CTRL;
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cl45_data |= LED_BCR_CLK_EN;
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break;
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default:
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return -EINVAL;
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}
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err = airoha_cl45_write(mbus, phy_addr, 0x1f, LED_BCR, cl45_data);
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if (err < 0)
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return err;
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return 0;
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}
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static int airoha_led_set_state(struct phy_device *phydev, u8 entity, u8 state)
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{
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u16 cl45_data;
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int err;
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int phy_addr = phydev_phy_addr(phydev);
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struct mii_bus *mbus = phydev_mdio_bus(phydev);
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err = airoha_cl45_read(mbus, phy_addr, 0x1f,
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LED_ON_CTRL(entity), &cl45_data);
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if (err < 0)
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return err;
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if (state == LED_ENABLE)
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cl45_data |= LED_ON_EN;
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else
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cl45_data &= ~LED_ON_EN;
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err = airoha_cl45_write(mbus, phy_addr, 0x1f,
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LED_ON_CTRL(entity), cl45_data);
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if (err < 0)
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return err;
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return 0;
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}
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static int en8801s_led_init(struct phy_device *phydev)
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{
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unsigned long led_gpio = 0, reg_value = 0;
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int ret = 0, led_id;
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struct mii_bus *mbus = phydev_mdio_bus(phydev);
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int gpio_led_rg[3] = {0x1870, 0x1874, 0x1878};
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u16 cl45_data = led_dur;
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struct device *dev = phydev_dev(phydev);
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int phy_addr = phydev_phy_addr(phydev);
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int pbus_addr = phydev_pbus_addr(phydev);
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ret = airoha_cl45_write(mbus, phy_addr, 0x1f, LED_BLK_DUR, cl45_data);
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if (ret < 0)
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return ret;
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cl45_data >>= 1;
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ret = airoha_cl45_write(mbus, phy_addr, 0x1f, LED_ON_DUR, cl45_data);
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if (ret < 0)
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return ret;
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ret = airoha_led_set_mode(phydev, AIR_LED_MODE_USER_DEFINE);
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if (ret != 0) {
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dev_err(dev, "LED fail to set mode, ret %d !\n", ret);
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return ret;
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}
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for (led_id = 0; led_id < EN8801S_LED_COUNT; led_id++) {
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reg_value = 0;
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ret = airoha_led_set_state(phydev, led_id, led_cfg[led_id].en);
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if (ret != 0) {
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dev_err(dev, "LED fail to set state, ret %d !\n", ret);
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return ret;
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}
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if (led_cfg[led_id].en == LED_ENABLE) {
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if ((led_cfg[led_id].gpio < 0)
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|| led_cfg[led_id].gpio > 9) {
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dev_err(dev, "GPIO%d is out of range!! GPIO number is 0~9.\n",
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led_cfg[led_id].gpio);
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return -EIO;
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}
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led_gpio |= BIT(led_cfg[led_id].gpio);
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reg_value = airoha_pbus_read(mbus, pbus_addr,
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gpio_led_rg[led_cfg[led_id].gpio / 4]);
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LED_SET_GPIO_SEL(led_cfg[led_id].gpio,
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led_id, reg_value);
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dev_dbg(dev, "[Airoha] gpio%d, reg_value 0x%lx\n",
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led_cfg[led_id].gpio, reg_value);
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ret = airoha_pbus_write(mbus, pbus_addr,
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gpio_led_rg[led_cfg[led_id].gpio / 4],
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reg_value);
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if (ret < 0)
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return ret;
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ret = airoha_led_set_usr_def(phydev, led_id,
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led_cfg[led_id].pol,
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led_cfg[led_id].on_cfg,
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led_cfg[led_id].blk_cfg);
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if (ret != 0) {
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dev_err(dev, "LED fail to set usr def, ret %d !\n",
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ret);
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return ret;
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}
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}
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}
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reg_value = (airoha_pbus_read(mbus, pbus_addr, 0x1880) & ~led_gpio);
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ret = airoha_pbus_write(mbus, pbus_addr, 0x1880, reg_value);
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if (ret < 0)
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return ret;
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ret = airoha_pbus_write(mbus, pbus_addr, 0x186c, led_gpio);
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if (ret < 0)
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return ret;
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dev_info(dev, "LED initialize OK !\n");
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return 0;
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}
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#endif
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static int en8801s_phy_process(struct phy_device *phydev)
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{
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struct mii_bus *mbus = phydev_mdio_bus(phydev);
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unsigned long reg_value = 0;
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int ret = 0;
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int pbus_addr = phydev_pbus_addr(phydev);
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reg_value = airoha_pbus_read(mbus, pbus_addr, 0x19e0);
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reg_value |= BIT(0);
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ret = airoha_pbus_write(mbus, pbus_addr, 0x19e0, reg_value);
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if (ret < 0)
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return ret;
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reg_value = airoha_pbus_read(mbus, pbus_addr, 0x19e0);
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reg_value &= ~BIT(0);
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ret = airoha_pbus_write(mbus, pbus_addr, 0x19e0, reg_value);
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if (ret < 0)
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return ret;
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return ret;
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}
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static int en8801s_phase1_init(struct phy_device *phydev)
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{
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unsigned long pbus_data;
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int pbus_addr = EN8801S_PBUS_DEFAULT_ADDR;
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u16 reg_value;
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int retry, ret = 0;
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struct mii_bus *mbus = phydev_mdio_bus(phydev);
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struct device *dev = phydev_dev(phydev);
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struct en8801s_priv *priv = phydev->priv;
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priv->count = 1;
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msleep(1000);
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retry = MAX_OUI_CHECK;
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while (1) {
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pbus_data = airoha_pbus_read(mbus, pbus_addr,
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|
EN8801S_RG_ETHER_PHY_OUI); /* PHY OUI */
|
|
if (pbus_data == EN8801S_PBUS_OUI) {
|
|
dev_info(dev, "PBUS addr 0x%x: Start initialized.\n",
|
|
pbus_addr);
|
|
break;
|
|
}
|
|
pbus_addr = phydev_pbus_addr(phydev);
|
|
if (0 == --retry) {
|
|
dev_err(dev, "Probe fail !\n");
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
ret = airoha_pbus_write(mbus, pbus_addr, EN8801S_RG_BUCK_CTL, 0x03);
|
|
if (ret < 0)
|
|
return ret;
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr, EN8801S_RG_PROD_VER);
|
|
priv->pro_version = pbus_data & 0xf;
|
|
dev_info(dev, "EN8801S Procduct Version :E%d\n", priv->pro_version);
|
|
mdelay(10);
|
|
pbus_data = (airoha_pbus_read(mbus, pbus_addr, EN8801S_RG_LTR_CTL)
|
|
& 0xfffffffc) | BIT(2);
|
|
ret = airoha_pbus_write(mbus, pbus_addr,
|
|
EN8801S_RG_LTR_CTL, pbus_data);
|
|
if (ret < 0)
|
|
return ret;
|
|
mdelay(500);
|
|
pbus_data = (pbus_data & ~BIT(2)) |
|
|
EN8801S_RX_POLARITY_NORMAL |
|
|
EN8801S_TX_POLARITY_NORMAL;
|
|
ret = airoha_pbus_write(mbus, pbus_addr,
|
|
EN8801S_RG_LTR_CTL, pbus_data);
|
|
if (ret < 0)
|
|
return ret;
|
|
mdelay(500);
|
|
if (priv->pro_version == 4) {
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1900);
|
|
dev_dbg(dev, "Before 0x1900 0x%lx\n", pbus_data);
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x1900, 0x101009f);
|
|
if (ret < 0)
|
|
return ret;
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1900);
|
|
dev_dbg(dev, "After 0x1900 0x%lx\n", pbus_data);
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x19a8);
|
|
dev_dbg(dev, "Before 19a8 0x%lx\n", pbus_data);
|
|
ret = airoha_pbus_write(mbus, pbus_addr,
|
|
0x19a8, pbus_data & ~BIT(16));
|
|
if (ret < 0)
|
|
return ret;
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x19a8);
|
|
dev_dbg(dev, "After 19a8 0x%lx\n", pbus_data);
|
|
}
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr,
|
|
EN8801S_RG_SMI_ADDR); /* SMI ADDR */
|
|
pbus_data = (pbus_data & 0xffff0000) |
|
|
(unsigned long)(phydev_pbus_addr(phydev) << 8) |
|
|
(unsigned long)(phydev_phy_addr(phydev));
|
|
dev_info(phydev_dev(phydev), "SMI_ADDR=%lx (renew)\n", pbus_data);
|
|
ret = airoha_pbus_write(mbus, pbus_addr,
|
|
EN8801S_RG_SMI_ADDR, pbus_data);
|
|
mdelay(10);
|
|
|
|
retry = MAX_RETRY;
|
|
while (1) {
|
|
mdelay(10);
|
|
reg_value = phy_read(phydev, MII_PHYSID2);
|
|
if (reg_value == EN8801S_PHY_ID2)
|
|
break; /* wait GPHY ready */
|
|
|
|
retry--;
|
|
if (retry == 0) {
|
|
dev_err(dev, "Initialize fail !\n");
|
|
return 0;
|
|
}
|
|
}
|
|
/* Software Reset PHY */
|
|
reg_value = phy_read(phydev, MII_BMCR);
|
|
reg_value |= BMCR_RESET;
|
|
ret = phy_write(phydev, MII_BMCR, reg_value);
|
|
if (ret < 0)
|
|
return ret;
|
|
retry = MAX_RETRY;
|
|
do {
|
|
mdelay(10);
|
|
reg_value = phy_read(phydev, MII_BMCR);
|
|
retry--;
|
|
if (retry == 0) {
|
|
dev_err(dev, "Reset fail !\n");
|
|
return 0;
|
|
}
|
|
} while (reg_value & BMCR_RESET);
|
|
|
|
phydev->dev_flags = PHY_STATE_INIT;
|
|
|
|
dev_info(dev, "Phase1 initialize OK ! (%s)\n", EN8801S_DRIVER_VERSION);
|
|
if (priv->pro_version == 4) {
|
|
ret = en8801s_phase2_init(phydev);
|
|
if (ret != 0) {
|
|
dev_info(dev, "en8801_phase2_init failed\n");
|
|
phydev->dev_flags = PHY_STATE_FAIL;
|
|
return 0;
|
|
}
|
|
phydev->dev_flags = PHY_STATE_PROCESS;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int en8801s_phase2_init(struct phy_device *phydev)
|
|
{
|
|
union gephy_all_REG_LpiReg1Ch GPHY_RG_LPI_1C;
|
|
union gephy_all_REG_dev1Eh_reg324h GPHY_RG_1E_324;
|
|
union gephy_all_REG_dev1Eh_reg012h GPHY_RG_1E_012;
|
|
union gephy_all_REG_dev1Eh_reg017h GPHY_RG_1E_017;
|
|
unsigned long pbus_data;
|
|
int phy_addr = phydev_phy_addr(phydev);
|
|
int pbus_addr = phydev_pbus_addr(phydev);
|
|
u16 cl45_value;
|
|
int retry, ret = 0;
|
|
struct mii_bus *mbus = phydev_mdio_bus(phydev);
|
|
struct device *dev = phydev_dev(phydev);
|
|
struct en8801s_priv *priv = phydev->priv;
|
|
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1690);
|
|
pbus_data |= BIT(31);
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x1690, pbus_data);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c000c00);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x10, 0xD801);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x0, 0x9140);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14, 0x0003);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c000c00);
|
|
if (ret < 0)
|
|
return ret;
|
|
/* Set FCM control */
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x1404, 0x004b);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x140c, 0x0007);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x142c, 0x05050505);
|
|
if (ret < 0)
|
|
return ret;
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1440);
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x1440, pbus_data & ~BIT(11));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1408);
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x1408, pbus_data | BIT(5));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Set GPHY Perfomance*/
|
|
/* Token Ring */
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_R1000DEC_15h, 0x0055A0);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_R1000DEC_17h, 0x07FF3F);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_PMA_00h, 0x00001E);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_PMA_01h, 0x6FB90A);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_PMA_17h, 0x060671);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_PMA_18h, 0x0E2F00);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_TR_26h, 0x444444);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_03h, 0x000000);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_06h, 0x2EBAEF);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_08h, 0x00000B);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Ch, 0x00504D);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Dh, 0x02314F);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Fh, 0x003028);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_10h, 0x005010);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_11h, 0x040001);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_13h, 0x018670);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_14h, 0x00024A);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_1Bh, 0x000072);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_1Ch, 0x003210);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* CL22 & CL45 */
|
|
ret = phy_write(phydev, 0x1f, 0x03);
|
|
if (ret < 0)
|
|
return ret;
|
|
GPHY_RG_LPI_1C.DATA = phy_read(phydev, RgAddr_LPI_1Ch);
|
|
GPHY_RG_LPI_1C.DataBitField.smi_deton_th = 0x0C;
|
|
ret = phy_write(phydev, RgAddr_LPI_1Ch, GPHY_RG_LPI_1C.DATA);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = phy_write(phydev, RgAddr_LPI_1Ch, 0xC92);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = phy_write(phydev, RgAddr_AUXILIARY_1Dh, 0x1);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = phy_write(phydev, 0x1f, 0x0);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x120, 0x8014);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x122, 0xffff);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x123, 0xffff);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x144, 0x0200);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x14A, 0xEE20);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x189, 0x0110);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x19B, 0x0111);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x234, 0x0181);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x238, 0x0120);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x239, 0x0117);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x268, 0x07F4);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x2D1, 0x0733);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x323, 0x0011);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x324, 0x013F);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x326, 0x0037);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = airoha_cl45_read(mbus, phy_addr, 0x1E, 0x324, &cl45_value);
|
|
if (ret < 0)
|
|
return ret;
|
|
GPHY_RG_1E_324.DATA = cl45_value;
|
|
GPHY_RG_1E_324.DataBitField.smi_det_deglitch_off = 0;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x324,
|
|
GPHY_RG_1E_324.DATA);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x19E, 0xC2);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x013, 0x0);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* EFUSE */
|
|
airoha_pbus_write(mbus, pbus_addr, 0x1C08, 0x40000040);
|
|
retry = MAX_RETRY;
|
|
while (retry != 0) {
|
|
mdelay(1);
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C08);
|
|
if ((pbus_data & BIT(30)) == 0)
|
|
break;
|
|
|
|
retry--;
|
|
}
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C38); /* RAW#2 */
|
|
ret = airoha_cl45_read(mbus, phy_addr, 0x1E, 0x12, &cl45_value);
|
|
if (ret < 0)
|
|
return ret;
|
|
GPHY_RG_1E_012.DATA = cl45_value;
|
|
GPHY_RG_1E_012.DataBitField.da_tx_i2mpb_a_tbt =
|
|
(u16)(pbus_data & 0x03f);
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x12,
|
|
GPHY_RG_1E_012.DATA);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_cl45_read(mbus, phy_addr, 0x1E, 0x17, &cl45_value);
|
|
if (ret < 0)
|
|
return ret;
|
|
GPHY_RG_1E_017.DATA = cl45_value;
|
|
GPHY_RG_1E_017.DataBitField.da_tx_i2mpb_b_tbt =
|
|
(u16)((pbus_data >> 8) & 0x03f);
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x17,
|
|
GPHY_RG_1E_017.DATA);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
airoha_pbus_write(mbus, pbus_addr, 0x1C08, 0x40400040);
|
|
retry = MAX_RETRY;
|
|
while (retry != 0) {
|
|
mdelay(1);
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C08);
|
|
if ((pbus_data & BIT(30)) == 0)
|
|
break;
|
|
|
|
retry--;
|
|
}
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C30); /* RAW#16 */
|
|
GPHY_RG_1E_324.DataBitField.smi_det_deglitch_off =
|
|
(u16)((pbus_data >> 12) & 0x01);
|
|
ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x324,
|
|
GPHY_RG_1E_324.DATA);
|
|
if (ret < 0)
|
|
return ret;
|
|
#ifdef AIR_LED_SUPPORT
|
|
ret = en8801s_led_init(phydev);
|
|
if (ret != 0)
|
|
dev_err(dev, "en8801s_led_init fail (ret:%d) !\n", ret);
|
|
#endif
|
|
|
|
ret = airoha_cl45_read(mbus, phy_addr, MDIO_MMD_AN,
|
|
MDIO_AN_EEE_ADV, &cl45_value);
|
|
if (ret < 0)
|
|
return ret;
|
|
if (cl45_value == 0) {
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1960);
|
|
if (0xA == ((pbus_data & 0x07c00000) >> 22)) {
|
|
pbus_data = (pbus_data & 0xf83fffff) | (0xC << 22);
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x1960,
|
|
pbus_data);
|
|
if (ret < 0)
|
|
return ret;
|
|
mdelay(10);
|
|
pbus_data = (pbus_data & 0xf83fffff) | (0xE << 22);
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x1960,
|
|
pbus_data);
|
|
if (ret < 0)
|
|
return ret;
|
|
mdelay(10);
|
|
}
|
|
} else {
|
|
pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1960);
|
|
if (0xE == ((pbus_data & 0x07c00000) >> 22)) {
|
|
pbus_data = (pbus_data & 0xf83fffff) | (0xC << 22);
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x1960,
|
|
pbus_data);
|
|
if (ret < 0)
|
|
return ret;
|
|
mdelay(10);
|
|
pbus_data = (pbus_data & 0xf83fffff) | (0xA << 22);
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x1960,
|
|
pbus_data);
|
|
if (ret < 0)
|
|
return ret;
|
|
mdelay(10);
|
|
}
|
|
}
|
|
|
|
priv->first_init = false;
|
|
dev_info(phydev_dev(phydev), "Phase2 initialize OK !\n");
|
|
return 0;
|
|
}
|
|
|
|
static int en8801s_read_status(struct phy_device *phydev)
|
|
{
|
|
int ret = 0, preSpeed = phydev->speed;
|
|
struct mii_bus *mbus = phydev_mdio_bus(phydev);
|
|
u32 reg_value;
|
|
struct device *dev = phydev_dev(phydev);
|
|
int pbus_addr = phydev_pbus_addr(phydev);
|
|
struct en8801s_priv *priv = phydev->priv;
|
|
|
|
ret = genphy_read_status(phydev);
|
|
if (phydev->link == LINK_DOWN)
|
|
preSpeed = phydev->speed = 0;
|
|
|
|
if (phydev->dev_flags == PHY_STATE_PROCESS) {
|
|
en8801s_phy_process(phydev);
|
|
phydev->dev_flags = PHY_STATE_DONE;
|
|
}
|
|
|
|
if (phydev->dev_flags == PHY_STATE_INIT) {
|
|
dev_dbg(dev, "phydev->link %d, count %d\n",
|
|
phydev->link, priv->count);
|
|
if ((phydev->link) || (priv->count == 5)) {
|
|
if (priv->pro_version != 4) {
|
|
ret = en8801s_phase2_init(phydev);
|
|
if (ret != 0) {
|
|
dev_info(dev, "en8801_phase2_init failed\n");
|
|
phydev->dev_flags = PHY_STATE_FAIL;
|
|
return 0;
|
|
}
|
|
phydev->dev_flags = PHY_STATE_PROCESS;
|
|
}
|
|
}
|
|
priv->count++;
|
|
}
|
|
|
|
if ((preSpeed != phydev->speed) && (phydev->link == LINK_UP)) {
|
|
preSpeed = phydev->speed;
|
|
|
|
if (preSpeed == SPEED_10) {
|
|
reg_value = airoha_pbus_read(mbus, pbus_addr, 0x1694);
|
|
reg_value |= BIT(31);
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x1694,
|
|
reg_value);
|
|
if (ret < 0)
|
|
return ret;
|
|
phydev->dev_flags = PHY_STATE_PROCESS;
|
|
} else {
|
|
reg_value = airoha_pbus_read(mbus, pbus_addr, 0x1694);
|
|
reg_value &= ~BIT(31);
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x1694,
|
|
reg_value);
|
|
if (ret < 0)
|
|
return ret;
|
|
phydev->dev_flags = PHY_STATE_PROCESS;
|
|
}
|
|
|
|
airoha_pbus_write(mbus, pbus_addr, 0x0600,
|
|
0x0c000c00);
|
|
if (preSpeed == SPEED_1000) {
|
|
dev_dbg(dev, "SPEED_1000\n");
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x10,
|
|
0xD801);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x0,
|
|
0x9140);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14,
|
|
0x0003);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x0600,
|
|
0x0c000c00);
|
|
if (ret < 0)
|
|
return ret;
|
|
mdelay(2); /* delay 2 ms */
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x1404,
|
|
0x004b);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x140c,
|
|
0x0007);
|
|
if (ret < 0)
|
|
return ret;
|
|
} else if (preSpeed == SPEED_100) {
|
|
dev_dbg(dev, "SPEED_100\n");
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x10,
|
|
0xD401);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x0,
|
|
0x9140);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14,
|
|
0x0007);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x0600,
|
|
0x0c11);
|
|
if (ret < 0)
|
|
return ret;
|
|
mdelay(2); /* delay 2 ms */
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x1404,
|
|
0x0027);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x140c,
|
|
0x0007);
|
|
if (ret < 0)
|
|
return ret;
|
|
} else if (preSpeed == SPEED_10) {
|
|
dev_dbg(dev, "SPEED_10\n");
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x10,
|
|
0xD001);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x0,
|
|
0x9140);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14,
|
|
0x000b);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x0600,
|
|
0x0c11);
|
|
if (ret < 0)
|
|
return ret;
|
|
mdelay(2); /* delay 2 ms */
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x1404,
|
|
0x0027);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = airoha_pbus_write(mbus, pbus_addr, 0x140c,
|
|
0x0007);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int en8801s_probe(struct phy_device *phydev)
|
|
{
|
|
struct en8801s_priv *priv;
|
|
unsigned long phy_addr = phydev_phy_addr(phydev);
|
|
struct mdio_device *mdiodev = &phydev->mdio;
|
|
|
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->count = 0;
|
|
priv->first_init = true;
|
|
|
|
if (mdiodev->reset_gpio) {
|
|
dev_dbg(phydev_dev(phydev),
|
|
"Assert PHY %lx HWRST until phy_init_hw\n",
|
|
phy_addr);
|
|
phy_device_reset(phydev, 1);
|
|
}
|
|
|
|
phydev->priv = priv;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int airoha_mmd_read(struct phy_device *phydev,
|
|
int devad, u16 reg)
|
|
{
|
|
struct mii_bus *mbus = phydev_mdio_bus(phydev);
|
|
int phy_addr = phydev_phy_addr(phydev);
|
|
int ret = 0;
|
|
u16 cl45_value;
|
|
|
|
ret = __airoha_cl45_read(mbus, phy_addr, devad, reg, &cl45_value);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return cl45_value;
|
|
}
|
|
|
|
static int airoha_mmd_write(struct phy_device *phydev,
|
|
int devad, u16 reg, u16 val)
|
|
{
|
|
struct mii_bus *mbus = phydev_mdio_bus(phydev);
|
|
int phy_addr = phydev_phy_addr(phydev);
|
|
int pbus_addr = phydev_pbus_addr(phydev);
|
|
unsigned long pbus_data;
|
|
int ret = 0;
|
|
|
|
if (MDIO_MMD_AN == devad && MDIO_AN_EEE_ADV == reg) {
|
|
if (val == 0) {
|
|
pbus_data = __airoha_pbus_read(mbus, pbus_addr, 0x1960);
|
|
if (0xA == ((pbus_data & 0x07c00000) >> 22)) {
|
|
pbus_data = (pbus_data & 0xf83fffff) |
|
|
(0xC << 22);
|
|
__airoha_pbus_write(mbus, pbus_addr, 0x1960,
|
|
pbus_data);
|
|
mdelay(10);
|
|
pbus_data = (pbus_data & 0xf83fffff) |
|
|
(0xE << 22);
|
|
__airoha_pbus_write(mbus, pbus_addr, 0x1960,
|
|
pbus_data);
|
|
mdelay(10);
|
|
}
|
|
} else {
|
|
pbus_data = __airoha_pbus_read(mbus, pbus_addr, 0x1960);
|
|
if (0xE == ((pbus_data & 0x07c00000) >> 22)) {
|
|
pbus_data = (pbus_data & 0xf83fffff) |
|
|
(0xC << 22);
|
|
__airoha_pbus_write(mbus, pbus_addr, 0x1960,
|
|
pbus_data);
|
|
mdelay(10);
|
|
pbus_data = (pbus_data & 0xf83fffff) |
|
|
(0xA << 22);
|
|
__airoha_pbus_write(mbus, pbus_addr, 0x1960,
|
|
pbus_data);
|
|
mdelay(10);
|
|
}
|
|
}
|
|
}
|
|
ret = __airoha_cl45_write(mbus, phy_addr, devad, reg, val);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct phy_driver Airoha_driver[] = {
|
|
{
|
|
.phy_id = EN8801SC_PHY_ID,
|
|
.name = "Airoha EN8801SC",
|
|
.phy_id_mask = 0x0ffffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.probe = en8801s_probe,
|
|
.config_init = en8801s_phase1_init,
|
|
.config_aneg = genphy_config_aneg,
|
|
.read_status = en8801s_read_status,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.read_mmd = airoha_mmd_read,
|
|
.write_mmd = airoha_mmd_write,
|
|
}
|
|
};
|
|
|
|
module_phy_driver(Airoha_driver);
|
|
|
|
static struct mdio_device_id __maybe_unused Airoha_tbl[] = {
|
|
{ EN8801SC_PHY_ID, 0x0ffffff0 },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(mdio, Airoha_tbl);
|