c06fb25d1f
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32 lines
1.3 KiB
Diff
32 lines
1.3 KiB
Diff
From c202f510bbaa34ab5d65a69a61e0e72761374b17 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Mon, 11 Mar 2024 17:14:19 +0000
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Subject: [PATCH] clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe port
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Due to what seems to be an undocumented oddity in MediaTek's MT7988
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SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires
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CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled.
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This currently leads to PCIe port 2 not working in Linux.
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Reflect the apparent relationship in the clk driver to make sure PCIe
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port 2 of the MT7988 SoC works.
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Suggested-by: Sam Shih <sam.shih@mediatek.com>
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/clk/mediatek/clk-mt7988-infracfg.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
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+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
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@@ -156,7 +156,7 @@ static const struct mtk_gate infra_clks[
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GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
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"csw_infra_f26m_sel", 8),
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GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
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- "csw_infra_f26m_sel", 9),
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+ "infra_pcie_peri_ck_26m_ck_p3", 9),
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GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
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"csw_infra_f26m_sel", 10),
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/* INFRA1 */
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