c06fb25d1f
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54 lines
2.0 KiB
Diff
54 lines
2.0 KiB
Diff
From abe68e0ca71dddce0e5419e35507cb464d61870d Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Tue, 9 Apr 2024 00:50:32 +0200
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Subject: [PATCH] arm64: dts: rockchip: reorder usb2phy properties for rk3588
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Reorder common DT properties alphabetically for usb2phy, according
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to latest DT style rules.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20240408225109.128953-6-sebastian.reichel@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++--------
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1 file changed, 8 insertions(+), 8 deletions(-)
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -602,13 +602,13 @@
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u2phy2: usb2phy@8000 {
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compatible = "rockchip,rk3588-usb2phy";
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reg = <0x8000 0x10>;
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- interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
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- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
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- reset-names = "phy", "apb";
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+ #clock-cells = <0>;
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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clock-names = "phyclk";
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clock-output-names = "usb480m_phy2";
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- #clock-cells = <0>;
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+ interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
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+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
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+ reset-names = "phy", "apb";
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status = "disabled";
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u2phy2_host: host-port {
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@@ -627,13 +627,13 @@
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u2phy3: usb2phy@c000 {
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compatible = "rockchip,rk3588-usb2phy";
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reg = <0xc000 0x10>;
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- interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
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- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
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- reset-names = "phy", "apb";
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+ #clock-cells = <0>;
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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clock-names = "phyclk";
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clock-output-names = "usb480m_phy3";
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- #clock-cells = <0>;
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+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
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+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
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+ reset-names = "phy", "apb";
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status = "disabled";
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u2phy3_host: host-port {
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