c06fb25d1f
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51 lines
1.5 KiB
Diff
51 lines
1.5 KiB
Diff
From e1918356dcc285eb7c50f271795e6fcc18d6c092 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Date: Thu, 30 Nov 2023 16:19:28 +0100
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Subject: [PATCH 1019/1024] riscv: dts: starfive: Add JH7100 cache controller
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The StarFive JH7100 SoC also features the SiFive L2 cache controller,
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so add the device tree nodes for it.
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Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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---
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arch/riscv/boot/dts/starfive/jh7100.dtsi | 13 +++++++++++++
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1 file changed, 13 insertions(+)
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--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
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@@ -32,6 +32,7 @@
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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+ next-level-cache = <&ccache>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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@@ -57,6 +58,7 @@
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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+ next-level-cache = <&ccache>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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@@ -148,6 +150,17 @@
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&cpu1_intc 3 &cpu1_intc 7>;
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};
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+ ccache: cache-controller@2010000 {
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+ compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache";
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+ reg = <0x0 0x2010000 0x0 0x1000>;
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+ interrupts = <128>, <130>, <131>, <129>;
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+ cache-block-size = <64>;
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+ cache-level = <2>;
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+ cache-sets = <2048>;
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+ cache-size = <2097152>;
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+ cache-unified;
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+ };
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+
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plic: interrupt-controller@c000000 {
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compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
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reg = <0x0 0xc000000 0x0 0x4000000>;
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