From 3fed02d930597c53f1c8500aff14581bb87a1e3d Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:22:31 +0800
Subject: [PATCH 07/25] doc: mediatek: add documentation for mt7621 reference
 boards

The MT7621 requires external binary blob being executed during u-boot's
boot-up flow. It's necessary to provide a guide here for users to correctly
build the u-boot.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
 doc/board/index.rst           |  1 +
 doc/board/mediatek/index.rst  |  9 +++++++
 doc/board/mediatek/mt7621.rst | 48 +++++++++++++++++++++++++++++++++++
 3 files changed, 58 insertions(+)
 create mode 100644 doc/board/mediatek/index.rst
 create mode 100644 doc/board/mediatek/mt7621.rst

--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -23,6 +23,7 @@ Board-specific doc
    highbank/index
    intel/index
    kontron/index
+   mediatek/index
    microchip/index
    nokia/index
    nxp/index
--- /dev/null
+++ b/doc/board/mediatek/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Mediatek
+=========
+
+.. toctree::
+   :maxdepth: 2
+
+   mt7621
--- /dev/null
+++ b/doc/board/mediatek/mt7621.rst
@@ -0,0 +1,48 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+mt7621_rfb/mt7621_nand_rfb
+==========================
+
+U-Boot for the MediaTek MT7621 boards
+
+Quick Start
+-----------
+
+- Get the DDR initialization binary blob
+- Configure CPU and DDR parameters
+- Build U-Boot
+
+Get the DDR initialization binary blob
+--------------------------------------
+
+Download one from:
+ - https://raw.githubusercontent.com/mtk-openwrt/mt7621-lowlevel-preloader/master/mt7621_stage_sram.bin
+ - https://raw.githubusercontent.com/mtk-openwrt/mt7621-lowlevel-preloader/master/mt7621_stage_sram_noprint.bin
+
+mt7621_stage_sram_noprint.bin has removed all output logs. To use this one,
+download and rename it to mt7621_stage_sram.bin
+
+Put the binary blob to the u-boot build directory.
+
+Configure CPU and DDR parameters
+--------------------------------
+
+menuconfig > MIPS architecture > MediaTek MIPS platforms > CPU & DDR configuration
+
+Select the correct DDR timing parameters for your board. The size shown here
+must match the DDR size of you board.
+
+The frequency of CPU and DDR can also be adjusted.
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+   $ export CROSS_COMPILE=mipsel-linux-
+   $ make O=build mt7621_rfb_defconfig # or mt7621_nand_rfb_defconfig
+   $ cp mt7621_stage_sram.bin ./build/mt7621_stage_sram.bin
+   $ # or cp mt7621_stage_sram_noprint.bin ./build/mt7621_stage_sram.bin
+   $ make O=build
+
+Burn the u-boot-mt7621.bin to the SPI-NOR or NAND flash.
