--- a/arch/mips/pci/pci-ar71xx.c
+++ b/arch/mips/pci/pci-ar71xx.c
@@ -51,11 +51,9 @@
 struct ar71xx_pci_controller {
 	struct device_node *np;
 	void __iomem *cfg_base;
-	int irq;
 	struct pci_controller pci_ctrl;
 	struct resource io_res;
 	struct resource mem_res;
-	struct irq_domain *domain;
 };
 
 /* Byte lane enable bits */
@@ -227,104 +225,6 @@ static struct pci_ops ar71xx_pci_ops = {
 	.write	= ar71xx_pci_write_config,
 };
 
-static void ar71xx_pci_irq_handler(struct irq_desc *desc)
-{
-	void __iomem *base = ath79_reset_base;
-	struct irq_chip *chip = irq_desc_get_chip(desc);
-	struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
-	u32 pending;
-
-	chained_irq_enter(chip, desc);
-	pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
-		  __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-
-	if (pending & AR71XX_PCI_INT_DEV0)
-		generic_handle_irq(irq_linear_revmap(apc->domain, 1));
-
-	else if (pending & AR71XX_PCI_INT_DEV1)
-		generic_handle_irq(irq_linear_revmap(apc->domain, 2));
-
-	else if (pending & AR71XX_PCI_INT_DEV2)
-		generic_handle_irq(irq_linear_revmap(apc->domain, 3));
-
-	else if (pending & AR71XX_PCI_INT_CORE)
-		generic_handle_irq(irq_linear_revmap(apc->domain, 4));
-
-	else
-		spurious_interrupt();
-	chained_irq_exit(chip, desc);
-}
-
-static void ar71xx_pci_irq_unmask(struct irq_data *d)
-{
-	struct ar71xx_pci_controller *apc;
-	unsigned int irq;
-	void __iomem *base = ath79_reset_base;
-	u32 t;
-
-	apc = irq_data_get_irq_chip_data(d);
-	irq = irq_linear_revmap(apc->domain, d->irq);
-
-	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-	__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-
-	/* flush write */
-	__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-}
-
-static void ar71xx_pci_irq_mask(struct irq_data *d)
-{
-	struct ar71xx_pci_controller *apc;
-	unsigned int irq;
-	void __iomem *base = ath79_reset_base;
-	u32 t;
-
-	apc = irq_data_get_irq_chip_data(d);
-	irq = irq_linear_revmap(apc->domain, d->irq);
-
-	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-	__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-
-	/* flush write */
-	__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-}
-
-static struct irq_chip ar71xx_pci_irq_chip = {
-	.name		= "AR71XX PCI",
-	.irq_mask	= ar71xx_pci_irq_mask,
-	.irq_unmask	= ar71xx_pci_irq_unmask,
-	.irq_mask_ack	= ar71xx_pci_irq_mask,
-};
-
-static int ar71xx_pci_irq_map(struct irq_domain *d,
-			      unsigned int irq, irq_hw_number_t hw)
-{
-	struct ar71xx_pci_controller *apc = d->host_data;
-
-	irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
-	irq_set_chip_data(irq, apc);
-
-	return 0;
-}
-
-static const struct irq_domain_ops ar71xx_pci_domain_ops = {
-	.xlate = irq_domain_xlate_onecell,
-	.map = ar71xx_pci_irq_map,
-};
-
-static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
-{
-	void __iomem *base = ath79_reset_base;
-
-	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
-
-	apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
-					    &ar71xx_pci_domain_ops, apc);
-	irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
-					 apc);
-}
-
 static void ar71xx_pci_reset(void)
 {
 	ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
@@ -358,10 +258,6 @@ static int ar71xx_pci_probe(struct platf
 	if (IS_ERR(apc->cfg_base))
 		return PTR_ERR(apc->cfg_base);
 
-	apc->irq = platform_get_irq(pdev, 0);
-	if (apc->irq < 0)
-		return -EINVAL;
-
 	ar71xx_pci_reset();
 
 	/* setup COMMAND register */
@@ -372,8 +268,6 @@ static int ar71xx_pci_probe(struct platf
 	/* clear bus errors */
 	ar71xx_pci_check_error(apc, 1);
 
-	ar71xx_pci_irq_init(apc);
-
 	apc->np = pdev->dev.of_node;
 	apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
 	apc->pci_ctrl.mem_resource = &apc->mem_res;
