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mediatek: add support t-phy settings from efuse on MT7986

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Import patches from mtk-openwrt-feeds (MTK SDK) to support reading
t-phy settings affecting PCIe as well as USB2 and USB3 from efuse.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle
2022-09-28 19:37:43 +01:00
parent b18b5a7ca3
commit 0419f7dead
3 changed files with 405 additions and 1 deletions
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32
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
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@@ -341,7 +341,7 @@
pcie_phy: t-phy@11c00000 {
compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2";
"mediatek,generic-tphy-v4";
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -352,6 +352,24 @@
clocks = <&clk40m>;
clock-names = "ref";
#phy-cells = <1>;
auto_load_valid;
auto_load_valid_ln1;
nvmem-cells = <&pcie_intr_ln0>,
<&pcie_rx_imp_ln0>,
<&pcie_tx_imp_ln0>,
<&pcie_auto_load_valid_ln0>,
<&pcie_intr_ln1>,
<&pcie_rx_imp_ln1>,
<&pcie_tx_imp_ln1>,
<&pcie_auto_load_valid_ln1>;
nvmem-cell-names = "intr",
"rx_imp",
"tx_imp",
"auto_load_valid",
"intr_ln1",
"rx_imp_ln1",
"tx_imp_ln1",
"auto_load_valid_ln1";
};
};
@@ -462,6 +480,9 @@
<&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
auto_load_valid;
nvmem-cells = <&u2_intr_p0>, <&u2_auto_load_valid_p0>;
nvmem-cell-names = "intr", "auto_load_valid";
};
u3port0: usb-phy@11e10700 {
@@ -469,6 +490,12 @@
clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
clock-names = "ref";
#phy-cells = <1>;
auto_load_valid;
nvmem-cells = <&comb_intr_p0>,
<&comb_rx_imp_p0>,
<&comb_tx_imp_p0>,
<&comb_auto_load_valid>;
nvmem-cell-names = "intr", "rx_imp", "tx_imp", "auto_load_valid";
};
u2port1: usb-phy@11e11000 {
@@ -477,6 +504,9 @@
<&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
auto_load_valid;
nvmem-cells = <&u2_intr_p1>, <&u2_auto_load_valid_p1>;
nvmem-cell-names = "intr", "auto_load_valid";
};
};