mvebu: 5.10 fix DVFS caused random boot crashes
5.10.37 and 5.4.119 introduced a lot of DVFS changes for Armada 37xx from 5.13 kernel.
Unfortunately commit:
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/cpufreq/armada-37xx-cpufreq.c?h=v5.10.37&id=a13b110e7c9e0dc2edcc7a19d4255fc88abd83cc
This patch actually corrects the things so that 1 or 1.2GHz models would actually get scaled to their native frequency.
However, due to a AVS setting voltages too low this will cause random crashes on 1.2GHz models.
So, until a new safe for everybody voltage is agreed on
lets revert the patch.
Fixes: d337731 ("kernel: bump 5.10 to 5.10.37")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This commit is contained in:
Robert Marko
committed by
Hauke Mehrtens
Hauke Mehrtens
parent
cc76e34c10
commit
080a0b74e3
@@ -0,0 +1,107 @@
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From 35639bac13927d1476398b740b11cbed0ee3ddb2 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robert.marko@sartura.hr>
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Date: Tue, 18 May 2021 13:24:30 +0200
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Subject: [PATCH] Revert "cpufreq: armada-37xx: Fix setting TBG parent for load
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levels"
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This reverts commit a13b110e7c9e0dc2edcc7a19d4255fc88abd83cc.
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This patch actually corrects the things so that 1 or 1.2GHz models would
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actually get scaled to their native frequency.
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However, due to a AVS setting voltages too low this will cause random
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crashes on 1.2GHz models.
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So, until a new safe for everybody voltage is agreed on
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lets revert the patch.
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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---
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drivers/cpufreq/armada-37xx-cpufreq.c | 35 +++++++++------------------
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1 file changed, 12 insertions(+), 23 deletions(-)
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--- a/drivers/cpufreq/armada-37xx-cpufreq.c
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+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
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@@ -25,10 +25,6 @@
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#include "cpufreq-dt.h"
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-/* Clk register set */
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-#define ARMADA_37XX_CLK_TBG_SEL 0
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-#define ARMADA_37XX_CLK_TBG_SEL_CPU_OFF 22
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-
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/* Power management in North Bridge register set */
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#define ARMADA_37XX_NB_L0L1 0x18
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#define ARMADA_37XX_NB_L2L3 0x1C
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@@ -126,15 +122,10 @@ static struct armada_37xx_dvfs *armada_3
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* will be configured then the DVFS will be enabled.
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*/
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static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
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- struct regmap *clk_base, u8 *divider)
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+ struct clk *clk, u8 *divider)
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{
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- u32 cpu_tbg_sel;
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int load_lvl;
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-
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- /* Determine to which TBG clock is CPU connected */
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- regmap_read(clk_base, ARMADA_37XX_CLK_TBG_SEL, &cpu_tbg_sel);
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- cpu_tbg_sel >>= ARMADA_37XX_CLK_TBG_SEL_CPU_OFF;
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- cpu_tbg_sel &= ARMADA_37XX_NB_TBG_SEL_MASK;
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+ struct clk *parent;
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for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
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unsigned int reg, mask, val, offset = 0;
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@@ -153,11 +144,6 @@ static void __init armada37xx_cpufreq_dv
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mask = (ARMADA_37XX_NB_CLK_SEL_MASK
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<< ARMADA_37XX_NB_CLK_SEL_OFF);
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- /* Set TBG index, for all levels we use the same TBG */
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- val = cpu_tbg_sel << ARMADA_37XX_NB_TBG_SEL_OFF;
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- mask = (ARMADA_37XX_NB_TBG_SEL_MASK
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- << ARMADA_37XX_NB_TBG_SEL_OFF);
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-
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/*
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* Set cpu divider based on the pre-computed array in
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* order to have balanced step.
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@@ -176,6 +162,14 @@ static void __init armada37xx_cpufreq_dv
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regmap_update_bits(base, reg, mask, val);
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}
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+
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+ /*
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+ * Set cpu clock source, for all the level we keep the same
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+ * clock source that the one already configured. For this one
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+ * we need to use the clock framework
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+ */
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+ parent = clk_get_parent(clk);
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+ clk_set_parent(clk, parent);
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}
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/*
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@@ -401,16 +395,11 @@ static int __init armada37xx_cpufreq_dri
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struct platform_device *pdev;
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unsigned long freq;
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unsigned int cur_frequency, base_frequency;
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- struct regmap *nb_clk_base, *nb_pm_base, *avs_base;
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+ struct regmap *nb_pm_base, *avs_base;
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struct device *cpu_dev;
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int load_lvl, ret;
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struct clk *clk, *parent;
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- nb_clk_base =
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- syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb");
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- if (IS_ERR(nb_clk_base))
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- return -ENODEV;
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-
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nb_pm_base =
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syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
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@@ -487,7 +476,7 @@ static int __init armada37xx_cpufreq_dri
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armada37xx_cpufreq_avs_configure(avs_base, dvfs);
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armada37xx_cpufreq_avs_setup(avs_base, dvfs);
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- armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider);
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+ armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
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clk_put(clk);
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for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
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@@ -0,0 +1,107 @@
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From 35639bac13927d1476398b740b11cbed0ee3ddb2 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robert.marko@sartura.hr>
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Date: Tue, 18 May 2021 13:24:30 +0200
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Subject: [PATCH] Revert "cpufreq: armada-37xx: Fix setting TBG parent for load
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levels"
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This reverts commit a13b110e7c9e0dc2edcc7a19d4255fc88abd83cc.
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This patch actually corrects the things so that 1 or 1.2GHz models would
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actually get scaled to their native frequency.
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However, due to a AVS setting voltages too low this will cause random
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crashes on 1.2GHz models.
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So, until a new safe for everybody voltage is agreed on
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lets revert the patch.
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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---
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drivers/cpufreq/armada-37xx-cpufreq.c | 35 +++++++++------------------
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1 file changed, 12 insertions(+), 23 deletions(-)
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--- a/drivers/cpufreq/armada-37xx-cpufreq.c
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+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
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@@ -25,10 +25,6 @@
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#include "cpufreq-dt.h"
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-/* Clk register set */
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-#define ARMADA_37XX_CLK_TBG_SEL 0
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-#define ARMADA_37XX_CLK_TBG_SEL_CPU_OFF 22
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-
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/* Power management in North Bridge register set */
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#define ARMADA_37XX_NB_L0L1 0x18
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#define ARMADA_37XX_NB_L2L3 0x1C
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@@ -126,15 +122,10 @@ static struct armada_37xx_dvfs *armada_3
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* will be configured then the DVFS will be enabled.
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*/
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static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
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- struct regmap *clk_base, u8 *divider)
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+ struct clk *clk, u8 *divider)
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{
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- u32 cpu_tbg_sel;
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int load_lvl;
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-
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- /* Determine to which TBG clock is CPU connected */
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- regmap_read(clk_base, ARMADA_37XX_CLK_TBG_SEL, &cpu_tbg_sel);
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- cpu_tbg_sel >>= ARMADA_37XX_CLK_TBG_SEL_CPU_OFF;
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- cpu_tbg_sel &= ARMADA_37XX_NB_TBG_SEL_MASK;
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+ struct clk *parent;
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for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
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unsigned int reg, mask, val, offset = 0;
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@@ -153,11 +144,6 @@ static void __init armada37xx_cpufreq_dv
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mask = (ARMADA_37XX_NB_CLK_SEL_MASK
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<< ARMADA_37XX_NB_CLK_SEL_OFF);
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- /* Set TBG index, for all levels we use the same TBG */
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- val = cpu_tbg_sel << ARMADA_37XX_NB_TBG_SEL_OFF;
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- mask = (ARMADA_37XX_NB_TBG_SEL_MASK
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- << ARMADA_37XX_NB_TBG_SEL_OFF);
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-
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/*
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* Set cpu divider based on the pre-computed array in
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* order to have balanced step.
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@@ -176,6 +162,14 @@ static void __init armada37xx_cpufreq_dv
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regmap_update_bits(base, reg, mask, val);
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}
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+
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+ /*
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+ * Set cpu clock source, for all the level we keep the same
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+ * clock source that the one already configured. For this one
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+ * we need to use the clock framework
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+ */
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+ parent = clk_get_parent(clk);
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+ clk_set_parent(clk, parent);
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}
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/*
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@@ -401,16 +395,11 @@ static int __init armada37xx_cpufreq_dri
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struct platform_device *pdev;
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unsigned long freq;
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unsigned int cur_frequency, base_frequency;
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- struct regmap *nb_clk_base, *nb_pm_base, *avs_base;
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+ struct regmap *nb_pm_base, *avs_base;
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struct device *cpu_dev;
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int load_lvl, ret;
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struct clk *clk, *parent;
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- nb_clk_base =
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- syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb");
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- if (IS_ERR(nb_clk_base))
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- return -ENODEV;
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-
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nb_pm_base =
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syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
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@@ -487,7 +476,7 @@ static int __init armada37xx_cpufreq_dri
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armada37xx_cpufreq_avs_configure(avs_base, dvfs);
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armada37xx_cpufreq_avs_setup(avs_base, dvfs);
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- armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider);
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+ armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
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clk_put(clk);
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for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
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