ramips: add second spi master sysclk
for mt7620, rt3883 and rt5350 Signed-off-by: Michael Lee <igvtee@gmail.com> SVN-Revision: 47616
This commit is contained in:
		| @@ -0,0 +1,30 @@ | ||||
| --- a/arch/mips/ralink/mt7620.c | ||||
| +++ b/arch/mips/ralink/mt7620.c | ||||
| @@ -434,6 +434,7 @@ void __init ralink_clk_init(void) | ||||
|  	ralink_clk_add("10000100.timer", periph_rate); | ||||
|  	ralink_clk_add("10000120.watchdog", periph_rate); | ||||
|  	ralink_clk_add("10000b00.spi", sys_rate); | ||||
| +	ralink_clk_add("10000b40.spi", sys_rate); | ||||
|  	ralink_clk_add("10000c00.uartlite", periph_rate); | ||||
|   	ralink_clk_add("10000d00.uart1", periph_rate); | ||||
|   	ralink_clk_add("10000e00.uart2", periph_rate); | ||||
| --- a/arch/mips/ralink/rt305x.c | ||||
| +++ b/arch/mips/ralink/rt305x.c | ||||
| @@ -199,6 +199,7 @@ void __init ralink_clk_init(void) | ||||
|  	ralink_clk_add("cpu", cpu_rate); | ||||
|  	ralink_clk_add("sys", sys_rate); | ||||
|  	ralink_clk_add("10000b00.spi", sys_rate); | ||||
| +	ralink_clk_add("10000b40.spi", sys_rate); | ||||
|  	ralink_clk_add("10000100.timer", wdt_rate); | ||||
|  	ralink_clk_add("10000120.watchdog", wdt_rate); | ||||
|  	ralink_clk_add("10000500.uart", uart_rate); | ||||
| --- a/arch/mips/ralink/rt3883.c | ||||
| +++ b/arch/mips/ralink/rt3883.c | ||||
| @@ -109,6 +109,7 @@ void __init ralink_clk_init(void) | ||||
|  	ralink_clk_add("10000120.watchdog", sys_rate); | ||||
|  	ralink_clk_add("10000500.uart", 40000000); | ||||
|  	ralink_clk_add("10000b00.spi", sys_rate); | ||||
| +	ralink_clk_add("10000b40.spi", sys_rate); | ||||
|  	ralink_clk_add("10000c00.uartlite", 40000000); | ||||
|  	ralink_clk_add("10100000.ethernet", sys_rate); | ||||
|  	ralink_clk_add("10180000.wmac", 40000000); | ||||
		Reference in New Issue
	
	Block a user
	 John Crispin
					John Crispin