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adds timer unit to ifxmips tree

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SVN-Revision: 11530
This commit is contained in:
John Crispin
2008-06-17 22:14:08 +00:00
parent cb076ccb14
commit 18ad6da063
8 changed files with 1484 additions and 13 deletions
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53
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
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@@ -148,8 +148,21 @@
/*------------ CGU */
#define IFXMIPS_CGU_BASE_ADDR 0xBF103000
#define IFXMIPS_CGU_BASE_ADDR (KSEG1 + 0x1F103000)
#define IFXMIPS_CGU_PLL0_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0004))
#define IFXMIPS_CGU_PLL1_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0008))
#define IFXMIPS_CGU_PLL2_CFG ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x000C))
#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
#define IFXMIPS_CGU_UPDATE ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0014))
#define IFXMIPS_CGU_IF_CLK ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
#define IFXMIPS_CGU_OSC_CON ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x001C))
#define IFXMIPS_CGU_SMD ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0020))
#define IFXMIPS_CGU_CT1SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0028))
#define IFXMIPS_CGU_CT2SR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x002C))
#define IFXMIPS_CGU_PCMCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0030))
#define IFXMIPS_CGU_PCI_CR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
#define IFXMIPS_CGU_PD_PC ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0038))
#define IFXMIPS_CGU_FMR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x003C))
/* clock mux */
#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
@@ -179,11 +192,12 @@
#define IFXMIPS_ICU_IM0_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0000))
#define IFXMIPS_ICU_IM0_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0008))
#define IFXMIPS_ICU_IM0_IOSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0010))
#define IFXMIPS_ICU_IM0_IRSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0018))
#define IFXMIPS_ICU_IM0_IOSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0010))
#define IFXMIPS_ICU_IM0_IRSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0018))
#define IFXMIPS_ICU_IM0_IMR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0020))
#define IFXMIPS_ICU_IM1_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0028))
#define IFXMIPS_ICU_IM5_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x00D0))
#define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR)
@@ -436,5 +450,36 @@
#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
#define IFXMIPS_MPS_CHIPID ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
#define IFXMIPS_MPS_VC0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
#define IFXMIPS_MPS_VC1ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0004))
#define IFXMIPS_MPS_VC2ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0008))
#define IFXMIPS_MPS_VC3ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x000C))
#define IFXMIPS_MPS_RVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
#define IFXMIPS_MPS_RVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0014))
#define IFXMIPS_MPS_RVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0018))
#define IFXMIPS_MPS_RVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x001C))
#define IFXMIPS_MPS_SVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0020))
#define IFXMIPS_MPS_SVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0024))
#define IFXMIPS_MPS_SVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0028))
#define IFXMIPS_MPS_SVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x002C))
#define IFXMIPS_MPS_CVC0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0030))
#define IFXMIPS_MPS_CVC1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0034))
#define IFXMIPS_MPS_CVC2SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0038))
#define IFXMIPS_MPS_CVC3SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x003C))
#define IFXMIPS_MPS_RAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0040))
#define IFXMIPS_MPS_RAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0044))
#define IFXMIPS_MPS_SAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0048))
#define IFXMIPS_MPS_SAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x004C))
#define IFXMIPS_MPS_CAD0SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0050))
#define IFXMIPS_MPS_CAD1SR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0054))
#define IFXMIPS_MPS_AD0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
#define IFXMIPS_MPS_AD1ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
#define IFXMIPS_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1)
#endif

11
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_cgu.h Normal file
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@@ -0,0 +1,11 @@
#ifndef _IFXMIPS_CGU_H__
#define _IFXMIPS_CGU_H__
u32 cgu_get_mips_clock(int cpu);
u32 cgu_get_cpu_clock(void);
u32 cgu_get_io_region_clock(void);
u32 cgu_get_fpi_bus_clock(int fpi);
u32 cgu_get_pp32_clock(void);
u32 cgu_get_ethernet_clock(int mii);
u32 cgu_get_usb_clock(void);
u32 cgu_get_clockout(int clkout);
#endif

169
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gptu.h Normal file
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@@ -0,0 +1,169 @@
#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
/******************************************************************************
Copyright (c) 2002, Infineon Technologies. All rights reserved.
No Warranty
Because the program is licensed free of charge, there is no warranty for
the program, to the extent permitted by applicable law. Except when
otherwise stated in writing the copyright holders and/or other parties
provide the program "as is" without warranty of any kind, either
expressed or implied, including, but not limited to, the implied
warranties of merchantability and fitness for a particular purpose. The
entire risk as to the quality and performance of the program is with
you. should the program prove defective, you assume the cost of all
necessary servicing, repair or correction.
In no event unless required by applicable law or agreed to in writing
will any copyright holder, or any other party who may modify and/or
redistribute the program as permitted above, be liable to you for
damages, including any general, special, incidental or consequential
damages arising out of the use or inability to use the program
(including but not limited to loss of data or data being rendered
inaccurate or losses sustained by you or third parties or a failure of
the program to operate with any other programs), even if such holder or
other party has been advised of the possibility of such damages.
******************************************************************************/
/*
* ####################################
* Definition
* ####################################
*/
/*
* Available Timer/Counter Index
*/
#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
#define TIMER_ANY 0x00
#define TIMER1A TIMER(1, 0)
#define TIMER1B TIMER(1, 1)
#define TIMER2A TIMER(2, 0)
#define TIMER2B TIMER(2, 1)
#define TIMER3A TIMER(3, 0)
#define TIMER3B TIMER(3, 1)
/*
* Flag of Timer/Counter
* These flags specify the way in which timer is configured.
*/
/* Bit size of timer/counter. */
#define TIMER_FLAG_16BIT 0x0000
#define TIMER_FLAG_32BIT 0x0001
/* Switch between timer and counter. */
#define TIMER_FLAG_TIMER 0x0000
#define TIMER_FLAG_COUNTER 0x0002
/* Stop or continue when overflowing/underflowing. */
#define TIMER_FLAG_ONCE 0x0000
#define TIMER_FLAG_CYCLIC 0x0004
/* Count up or counter down. */
#define TIMER_FLAG_UP 0x0000
#define TIMER_FLAG_DOWN 0x0008
/* Count on specific level or edge. */
#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
#define TIMER_FLAG_RISE_EDGE 0x0010
#define TIMER_FLAG_FALL_EDGE 0x0020
#define TIMER_FLAG_ANY_EDGE 0x0030
/* Signal is syncronous to module clock or not. */
#define TIMER_FLAG_UNSYNC 0x0000
#define TIMER_FLAG_SYNC 0x0080
/* Different interrupt handle type. */
#define TIMER_FLAG_NO_HANDLE 0x0000
#if defined(__KERNEL__)
#define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
#endif // defined(__KERNEL__)
#define TIMER_FLAG_SIGNAL 0x0300
/* Internal clock source or external clock source */
#define TIMER_FLAG_INT_SRC 0x0000
#define TIMER_FLAG_EXT_SRC 0x1000
/*
* ioctl Command
*/
#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
/*
* Data Type Used to Call ioctl
*/
struct gptu_ioctl_param {
unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
* GPTU_SET_COUNTER, this field is ID of expected *
* timer/counter. If it's zero, a timer/counter would *
* be dynamically allocated and ID would be stored in *
* this field. *
* In command GPTU_GET_COUNT_VALUE, this field is *
* ignored. *
* In other command, this field is ID of timer/counter *
* allocated. */
unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
* GPTU_SET_COUNTER, this field contains flags to *
* specify how to configure timer/counter. *
* In command GPTU_START_TIMER, zero indicate start *
* and non-zero indicate resume timer/counter. *
* In other command, this field is ignored. */
unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
* init/reload value. *
* In command GPTU_SET_TIMER, this field contains *
* frequency (0.001Hz) of timer. *
* In command GPTU_GET_COUNT_VALUE, current count *
* value would be stored in this field. *
* In command GPTU_CALCULATE_DIVIDER, this field *
* contains frequency wanted, and after calculation, *
* divider would be stored in this field to overwrite *
* the frequency. *
* In other command, this field is ignored. */
int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
* if signal is required, this field contains process *
* ID to which signal would be sent. *
* In other command, this field is ignored. */
int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
* if signal is required, this field contains signal *
* number which would be sent. *
* In other command, this field is ignored. */
};
/*
* ####################################
* Data Type
* ####################################
*/
#if defined(__KERNEL__)
typedef void (*timer_callback)(unsigned long arg);
#endif // defined(__KERNEL__)
/*
* ####################################
* Declaration
* ####################################
*/
#if defined(__KERNEL__)
extern int request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
extern int free_timer(unsigned int);
extern int start_timer(unsigned int, int);
extern int stop_timer(unsigned int);
extern int reset_counter_flags(u32 timer, u32 flags);
extern int get_count_value(unsigned int, unsigned long *);
extern u32 cal_divider(unsigned long);
extern int set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
extern int set_counter (unsigned int timer, unsigned int flag, u32 reload, unsigned long arg1, unsigned long arg2);
// extern int set_counter(unsigned int, int, int, int, unsigned int, unsigned int, unsigned long, unsigned long);
#endif // defined(__KERNEL__)
#endif // __DANUBE_GPTU_DEV_H__2005_07_26__10_19__