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mediatek: update to latest kernel patchset from v4.13-rc

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Signed-off-by: Muciri Gatimu <muciri@openmesh.com>
Signed-off-by: Shashidhar Lakkavalli <shashidhar.lakkavalli@openmesh.com>
Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin
2017-08-18 18:11:52 +02:00
parent 364befeccf
commit 1f068588ef
92 changed files with 10641 additions and 599 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
target/linux/mediatek/base-files/etc/board.d/02_network
View File

@@ -9,6 +9,7 @@ mediatek_setup_interfaces()
local board="$1"
case $board in
'bananapi,bpi-r2' | \
'mediatek,mt7623-rfb-emmc' | \
'mediatek,mt7623-rfb-nand-ephy')
ucidef_set_interface_lan "lan0 lan1 lan2 lan3"

60
target/linux/mediatek/base-files/etc/config/mtkhnat Normal file
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@@ -0,0 +1,60 @@
config global global
option enable 0
option upstream 1000000
option downstream 1000000
config queue
option id 0
option minrate 10
option maxrate 50
option weight 7
option resv 32
config queue
option id 1
option minrate 30
option maxrate 100
option weight 7
option resv 32
config queue
option id 2
option minrate 30
option maxrate 100
option weight 7
option resv 32
config queue
option id 3
option minrate 30
option maxrate 100
option weight 7
option resv 32
config queue
option id 4
option minrate 25
option maxrate 100
option weight 7
option resv 32
config queue
option id 5
option minrate 25
option maxrate 100
option weight 7
option resv 32
config queue
option id 6
option minrate 25
option maxrate 100
option weight 7
option resv 32
config queue
option id 7
option minrate 25
option maxrate 100
option weight 7
option resv 32

13
target/linux/mediatek/base-files/etc/init.d/mtkhnat Executable file
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@@ -0,0 +1,13 @@
#!/bin/sh /etc/rc.common
START=90
USE_PROCD=1
NAME=mtkhnat
PROG=/sbin/mtkhnat
start_service() {
procd_open_instance
procd_set_param command "${PROG}"
procd_close_instance
}

9
target/linux/mediatek/base-files/etc/uci-defaults/99-firewall Executable file
View File

@@ -0,0 +1,9 @@
echo "iptables -t mangle -A FORWARD -i br-lan -o eth1 -p tcp -m mark --mark 0/0x7 -j MARK --set-mark 4/0x7" >> /etc/firewall.user
echo "iptables -t mangle -A FORWARD -i br-lan -o eth1 -p udp -m mark --mark 0/0x7 -j MARK --set-mark 5/0x7" >> /etc/firewall.user
echo "iptables -t mangle -A FORWARD -i eth1 -o br-lan -p tcp -m mark --mark 0/0x7 -j MARK --set-mark 4/0x7" >> /etc/firewall.user
echo "iptables -t mangle -A FORWARD -i eth1 -o br-lan -p udp -m mark --mark 0/0x7 -j MARK --set-mark 5/0x7" >> /etc/firewall.user
echo "iptables -t mangle -A FORWARD -p udp -m mark --mark 0/0xf8 -j MARK --or-mark 0x60" >> /etc/firewall.user
echo "iptables -t mangle -A FORWARD -p tcp -m mark --mark 0/0xf8 -j MARK --or-mark 0xc0" >> /etc/firewall.user
exit 0

16
target/linux/mediatek/base-files/etc/uci-defaults/99-net-ps Executable file
View File

@@ -0,0 +1,16 @@
uci set network.globals.default_rps_val=14
uci set network.globals.default_rps_flow_cnt=256
uci set network.globals.default_xps_val=14
uci set network.globals.default_ps=1
uci set network.eth0=device
uci set network.eth0.name=eth0
uci set network.lan0=device
uci set network.lan0.name=lan0
uci set network.lan1=device
uci set network.lan1.name=lan1
uci set network.lan2=device
uci set network.lan2.name=lan2
uci set network.lan3=device
uci set network.lan3.name=lan3
uci commit
exit 0

8
target/linux/mediatek/base-files/lib/preinit/06_set_rps_sock_flow Normal file
View File

@@ -0,0 +1,8 @@
#!/bin/sh
set_rps_sock_flow() {
echo 1024 > /proc/sys/net/core/rps_sock_flow_entries
}
boot_hook_add preinit_main set_rps_sock_flow

1
target/linux/mediatek/base-files/lib/upgrade/platform.sh
View File

@@ -25,6 +25,7 @@ platform_check_image() {
nand_do_platform_check $board $1
return $?
;;
bananapi,bpi-r2 |\
mediatek,mt7623-rfb-emmc)
local kernel_length=`(tar xf $tar_file sysupgrade-$board/kernel -O | wc -c) 2> /dev/null`
local rootfs_length=`(tar xf $tar_file sysupgrade-$board/root -O | wc -c) 2> /dev/null`

64
target/linux/mediatek/base-files/sbin/mtkhnat Executable file
View File

@@ -0,0 +1,64 @@
#!/bin/sh
. /lib/functions.sh
config_load mtkhnat
config_get enable global enable 0
[ "${enable}" -eq 1 ] || {
echo 0 ${sch_upstream} > /sys/kernel/debug/hnat/scheduler0
echo 0 ${sch_downstream} > /sys/kernel/debug/hnat/scheduler1
rmmod mtkhnat
exit 0
}
insmod mtkhnat
sleep 1
config_get sch_upstream global upstream 100000
config_get sch_downstream global downstream 100000
echo 1 ${sch_upstream} > /sys/kernel/debug/hnat/scheduler0
echo 1 ${sch_downstream} > /sys/kernel/debug/hnat/scheduler1
setup_queue() {
local queue_id queue_scheduler queue_minebl queue_maxebl queue_minrate queue_maxrate queue_resv minrate maxrate queue_weight
config_get queue_id $1 id 0
config_get queue_minrate $1 minrate 0
config_get queue_maxrate $1 maxrate 0
config_get queue_resv $1 resv 22
config_get queue_weight $1 weight 7
[ "${queue_id}" -gt 7 ] && return 0
queue_minebl=1
queue_maxebl=1
queue_scheduler=0
[ "${queue_minrate}" -eq 0 ] && queue_minebl=0
[ "${queue_maxrate}" -eq 0 ] && queue_maxebl=0
minrate=$((sch_upstream * $queue_minrate))
minrate=$((minrate / 100))
maxrate=$((sch_upstream * $queue_maxrate))
maxrate=$((maxrate / 100))
echo 0 ${queue_minebl} ${minrate} ${queue_maxebl} ${maxrate} ${queue_weight} ${queue_resv} > /sys/kernel/debug/hnat/queue${queue_id}
queue_id=$((queue_id + 8))
minrate=$((sch_downstream * $queue_minrate))
minrate=$((minrate / 100))
maxrate=$((sch_downstream * $queue_maxrate))
maxrate=$((maxrate / 100))
echo 1 ${queue_minebl} ${minrate} ${queue_maxebl} ${maxrate} ${queue_weight} ${queue_resv} > /sys/kernel/debug/hnat/queue${queue_id}
}
config_foreach setup_scheduler scheduler
config_foreach setup_queue queue

26
target/linux/mediatek/config-4.9
View File

@@ -45,7 +45,6 @@ CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_ATAGS=y
CONFIG_AUTO_ZRELADDR=y
# CONFIG_BINFMT_FLAT is not set
CONFIG_BLK_MQ_PCI=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
@@ -104,13 +103,29 @@ CONFIG_CRC32_SLICEBY8=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DEV_MEDIATEK=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_BUGVERBOSE=y
@@ -213,6 +228,7 @@ CONFIG_HIGHMEM=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HWMON=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MTK=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
@@ -254,7 +270,6 @@ CONFIG_MDIO_GPIO=y
CONFIG_MEDIATEK_MT6577_AUXADC=y
CONFIG_MEDIATEK_WATCHDOG=y
CONFIG_MFD_CORE=y
# CONFIG_MFD_MAX77620 is not set
CONFIG_MFD_MT6397=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
@@ -275,7 +290,6 @@ CONFIG_MTD_MT81xx_NOR=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_MTK=y
# CONFIG_MTD_PHYSMAP_OF_VERSATILE is not set
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
@@ -300,6 +314,8 @@ CONFIG_NET_DSA=y
CONFIG_NET_DSA_MT7530=y
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_FLOW_LIMIT=y
# CONFIG_NET_MEDIATEK_HNAT is not set
CONFIG_NET_MEDIATEK_HW_QOS=y
CONFIG_NET_MEDIATEK_SOC=y
CONFIG_NET_SWITCHDEV=y
# CONFIG_NET_VENDOR_AURORA is not set
@@ -329,7 +345,10 @@ CONFIG_OLD_SIGSUSPEND3=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_MTK=y
CONFIG_PCIE_PME=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
@@ -366,6 +385,7 @@ CONFIG_PWM=y
CONFIG_PWM_MEDIATEK=y
# CONFIG_PWM_MTK_DISP is not set
CONFIG_PWM_SYSFS=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_RCU_CPU_STALL_TIMEOUT=21
# CONFIG_RCU_EXPERT is not set

169
target/linux/mediatek/files/arch/arm/boot/dts/_mt7623.dtsi
View File

@@ -19,6 +19,7 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
#include <dt-bindings/gpio/gpio.h>
#include "skeleton64.dtsi"
@@ -151,7 +152,7 @@
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt2701-pinctrl";
compatible = "mediatek,mt7623-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>;
pins-are-numbered;
@@ -211,6 +212,15 @@
clock-names = "spi", "wrap";
};
cir: cir@10013000 {
compatible = "mediatek,mt7623-cir";
reg = <0 0x10013000 0 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_IRRX>;
clock-names = "clk";
status = "disabled";
};
sysirq: interrupt-controller@10200100 {
compatible = "mediatek,mt7623-sysirq",
"mediatek,mt6577-sysirq";
@@ -240,6 +250,13 @@
#clock-cells = <1>;
};
rng: rng@1020f000 {
compatible = "mediatek,mt7623-rng";
reg = <0 0x1020f000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_TRNG>;
clock-names = "rng";
};
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
@@ -370,7 +387,7 @@
status = "disabled";
};
spi: spi@1100a000 {
spi0: spi@1100a000 {
compatible = "mediatek,mt7623-spi",
"mediatek,mt6589-spi";
reg = <0 0x1100a000 0 0x1000>;
@@ -399,6 +416,34 @@
nvmem-cell-names = "calibration-data";
};
spi1: spi@11016000 {
compatible = "mediatek,mt7623-spi",
"mediatek,mt2701-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11016000 0 0x100>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
<&topckgen CLK_TOP_SPI1_SEL>,
<&pericfg CLK_PERI_SPI1>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi2: spi@11017000 {
compatible = "mediatek,mt7623-spi",
"mediatek,mt2701-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11017000 0 0x1000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
<&topckgen CLK_TOP_SPI2_SEL>,
<&pericfg CLK_PERI_SPI2>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
nandc: nfi@1100d000 {
compatible = "mediatek,mt7623-nfc",
"mediatek,mt2701-nfc";
@@ -424,6 +469,104 @@
status = "disabled";
};
afe: audio-controller@11220000 {
compatible = "mediatek,mt7623-audio",
"mediatek,mt2701-audio";
reg = <0 0x11220000 0 0x2000>,
<0 0x112a0000 0 0x20000>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
<&topckgen CLK_TOP_AUD_MUX2_DIV>,
<&topckgen CLK_TOP_AUD_48K_TIMING>,
<&topckgen CLK_TOP_AUD_44K_TIMING>,
<&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
<&topckgen CLK_TOP_APLL_SEL>,
<&topckgen CLK_TOP_AUD1PLL_98M>,
<&topckgen CLK_TOP_AUD2PLL_90M>,
<&topckgen CLK_TOP_HADDS2PLL_98M>,
<&topckgen CLK_TOP_HADDS2PLL_294M>,
<&topckgen CLK_TOP_AUDPLL>,
<&topckgen CLK_TOP_AUDPLL_D4>,
<&topckgen CLK_TOP_AUDPLL_D8>,
<&topckgen CLK_TOP_AUDPLL_D16>,
<&topckgen CLK_TOP_AUDPLL_D24>,
<&topckgen CLK_TOP_AUDINTBUS_SEL>,
<&clk26m>,
<&topckgen CLK_TOP_SYSPLL1_D4>,
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
<&topckgen CLK_TOP_AUD_I2S5_MCLK>,
<&topckgen CLK_TOP_AUD_I2S6_MCLK>,
<&topckgen CLK_TOP_ASM_M_SEL>,
<&topckgen CLK_TOP_ASM_H_SEL>,
<&topckgen CLK_TOP_UNIVPLL2_D4>,
<&topckgen CLK_TOP_UNIVPLL2_D2>,
<&topckgen CLK_TOP_SYSPLL_D5>;
clock-names = "infra_sys_audio_clk",
"top_audio_mux1_sel",
"top_audio_mux2_sel",
"top_audio_mux1_div",
"top_audio_mux2_div",
"top_audio_48k_timing",
"top_audio_44k_timing",
"top_audpll_mux_sel",
"top_apll_sel",
"top_aud1_pll_98M",
"top_aud2_pll_90M",
"top_hadds2_pll_98M",
"top_hadds2_pll_294M",
"top_audpll",
"top_audpll_d4",
"top_audpll_d8",
"top_audpll_d16",
"top_audpll_d24",
"top_audintbus_sel",
"clk_26m",
"top_syspll1_d4",
"top_aud_k1_src_sel",
"top_aud_k2_src_sel",
"top_aud_k3_src_sel",
"top_aud_k4_src_sel",
"top_aud_k5_src_sel",
"top_aud_k6_src_sel",
"top_aud_k1_src_div",
"top_aud_k2_src_div",
"top_aud_k3_src_div",
"top_aud_k4_src_div",
"top_aud_k5_src_div",
"top_aud_k6_src_div",
"top_aud_i2s1_mclk",
"top_aud_i2s2_mclk",
"top_aud_i2s3_mclk",
"top_aud_i2s4_mclk",
"top_aud_i2s5_mclk",
"top_aud_i2s6_mclk",
"top_asm_m_sel",
"top_asm_h_sel",
"top_univpll2_d4",
"top_univpll2_d2",
"top_syspll_d5";
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt7623-mmc",
"mediatek,mt8135-mmc";
@@ -636,4 +779,26 @@
#size-cells = <0>;
};
};
hnat: hnat@1b000000 {
compatible = "mediatek,mt7623-hnat";
reg = <0 0x1b100000 0 0x3000>;
mtketh-wan = "eth1";
resets = <&ethsys 0>;
reset-names = "mtketh";
};
crypto: crypto@1b240000 {
compatible = "mediatek,mt7623-crypto", "mediatek,eip97-crypto";
reg = <0 0x1b240000 0 0x20000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
<&ethsys CLK_ETHSYS_CRYPTO>;
clock-names = "ethif","cryp";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
};
};

241
target/linux/mediatek/files/arch/arm/boot/dts/mt6323.dtsi Normal file
View File

@@ -0,0 +1,241 @@
/*
* Copyright (c) 2017 MediaTek Inc.
* Author: John Crispin <john@phrozen.org>
* Sean Wang <sean.wang@mediatek.com>
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&pwrap {
pmic: mt6323 {
compatible = "mediatek,mt6323";
interrupt-parent = <&pio>;
interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
mt6323regulator: mt6323regulator{
compatible = "mediatek,mt6323-regulator";
mt6323_vproc_reg: buck_vproc{
regulator-name = "vproc";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
regulator-boot-on;
};
mt6323_vsys_reg: buck_vsys{
regulator-name = "vsys";
regulator-min-microvolt = <1400000>;
regulator-max-microvolt = <2987500>;
regulator-ramp-delay = <25000>;
regulator-always-on;
regulator-boot-on;
};
mt6323_vpa_reg: buck_vpa{
regulator-name = "vpa";
regulator-min-microvolt = < 500000>;
regulator-max-microvolt = <3650000>;
};
mt6323_vtcxo_reg: ldo_vtcxo{
regulator-name = "vtcxo";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <90>;
regulator-always-on;
regulator-boot-on;
};
mt6323_vcn28_reg: ldo_vcn28{
regulator-name = "vcn28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <185>;
};
mt6323_vcn33_bt_reg: ldo_vcn33_bt{
regulator-name = "vcn33_bt";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3600000>;
regulator-enable-ramp-delay = <185>;
};
mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
regulator-name = "vcn33_wifi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3600000>;
regulator-enable-ramp-delay = <185>;
};
mt6323_va_reg: ldo_va{
regulator-name = "va";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <216>;
regulator-always-on;
regulator-boot-on;
};
mt6323_vcama_reg: ldo_vcama{
regulator-name = "vcama";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vio28_reg: ldo_vio28{
regulator-name = "vio28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <216>;
regulator-always-on;
regulator-boot-on;
};
mt6323_vusb_reg: ldo_vusb{
regulator-name = "vusb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <216>;
regulator-boot-on;
};
mt6323_vmc_reg: ldo_vmc{
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <36>;
regulator-boot-on;
};
mt6323_vmch_reg: ldo_vmch{
regulator-name = "vmch";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <36>;
regulator-boot-on;
};
mt6323_vemc3v3_reg: ldo_vemc3v3{
regulator-name = "vemc3v3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <36>;
regulator-boot-on;
};
mt6323_vgp1_reg: ldo_vgp1{
regulator-name = "vgp1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vgp2_reg: ldo_vgp2{
regulator-name = "vgp2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vgp3_reg: ldo_vgp3{
regulator-name = "vgp3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vcn18_reg: ldo_vcn18{
regulator-name = "vcn18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vsim1_reg: ldo_vsim1{
regulator-name = "vsim1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vsim2_reg: ldo_vsim2{
regulator-name = "vsim2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vrtc_reg: ldo_vrtc{
regulator-name = "vrtc";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
mt6323_vcamaf_reg: ldo_vcamaf{
regulator-name = "vcamaf";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vibr_reg: ldo_vibr{
regulator-name = "vibr";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <36>;
};
mt6323_vrf18_reg: ldo_vrf18{
regulator-name = "vrf18";
regulator-min-microvolt = <1825000>;
regulator-max-microvolt = <1825000>;
regulator-enable-ramp-delay = <187>;
};
mt6323_vm_reg: ldo_vm{
regulator-name = "vm";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
regulator-always-on;
regulator-boot-on;
};
mt6323_vio18_reg: ldo_vio18{
regulator-name = "vio18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
regulator-always-on;
regulator-boot-on;
};
mt6323_vcamd_reg: ldo_vcamd{
regulator-name = "vcamd";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vcamio_reg: ldo_vcamio{
regulator-name = "vcamio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
};
};
};
};

7
target/linux/mediatek/files/arch/arm/boot/dts/mt7623-NAND-ePHY.dts
View File

@@ -363,13 +363,6 @@
<MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
};
pins_eth_esw {
pinmux = <MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>;
input-enable;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up;
};
pins_eth_rst {
pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
output-low;

7
target/linux/mediatek/files/arch/arm/boot/dts/mt7623-NAND.dts
View File

@@ -363,13 +363,6 @@
<MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
};
pins_eth_esw {
pinmux = <MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>;
input-enable;
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up;
};
pins_eth_rst {
pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
output-low;

109
target/linux/mediatek/files/arch/arm/boot/dts/mt7623-eMMC.dts
View File

@@ -38,6 +38,61 @@
gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
switch {
compatible = "mediatek,mt7530";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
dsa,mii-bus = <&mdio0>;
pinctrl-names = "default";
pinctrl-0 = <&eth_default>;
core-supply = <&mt6323_vpa_reg>;
io-supply = <&mt6323_vemc3v3_reg>;
mediatek,mcm;
resets = <&ethsys 2>;
reset-names = "mcm";
ports {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
port@0 {
reg = <0>;
label = "lan0";
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
&cpu0 {
@@ -428,7 +483,6 @@
<MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
<MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
<MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
<MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>,
<MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
};
@@ -480,59 +534,6 @@
};
&mdio0 {
switch@0 {
compatible = "mediatek,mt7530";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&eth_default>;
core-supply = <&mt6323_vpa_reg>;
io-supply = <&mt6323_vemc3v3_reg>;
mediatek,mcm;
resets = <&ethsys 2>;
reset-names = "mcm";
ports {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
port@0 {
reg = <0>;
label = "lan0";
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
phy5: ethernet-phy@5 {
reg = <5>;
phy-mode = "rgmii-rxid";

443
target/linux/mediatek/files/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts Normal file
View File

@@ -0,0 +1,443 @@
/*
* Copyright 2017 Sean Wang <sean.wang@mediatek.com>
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "_mt7623.dtsi"
#include "mt6323.dtsi"
/ {
model = "Bananapi BPI-R2";
compatible = "bananapi,bpi-r2", "mediatek,mt7623";
aliases {
serial2 = &uart2;
};
chosen {
stdout-path = "serial2:115200n8";
};
cpus {
cpu@0 {
proc-supply = <&mt6323_vproc_reg>;
};
cpu@1 {
proc-supply = <&mt6323_vproc_reg>;
};
cpu@2 {
proc-supply = <&mt6323_vproc_reg>;
};
cpu@3 {
proc-supply = <&mt6323_vproc_reg>;
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_pins_a>;
factory {
label = "factory";
linux,code = <BTN_0>;
gpios = <&pio 256 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_a>;
red {
label = "bpi-r2:pio:red";
gpios = <&pio 239 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
green {
label = "bpi-r2:pio:green";
gpios = <&pio 240 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
blue {
label = "bpi-r2:pio:blue";
gpios = <&pio 241 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
memory@80000000 {
reg = <0 0x80000000 0 0x40000000>;
};
};
&cir {
pinctrl-names = "default";
pinctrl-0 = <&cir_pins_a>;
status = "okay";
};
&crypto {
status = "okay";
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
compatible = "mediatek,mt7530";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
pinctrl-names = "default";
reset-gpios = <&pio 33 0>;
core-supply = <&mt6323_vpa_reg>;
io-supply = <&mt6323_vemc3v3_reg>;
ports {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
port@0 {
reg = <0>;
label = "wan";
};
port@1 {
reg = <1>;
label = "lan0";
};
port@2 {
reg = <2>;
label = "lan1";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan3";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "trgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&pio {
cir_pins_a:cir@0 {
pins_cir {
pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
bias-disable;
};
};
i2c0_pins_a: i2c@0 {
pins_i2c0 {
pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
<MT7623_PIN_76_SCL0_FUNC_SCL0>;
bias-disable;
};
};
i2c1_pins_a: i2c@1 {
pin_i2c1 {
pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
<MT7623_PIN_58_SCL1_FUNC_SCL1>;
bias-disable;
};
};
i2s0_pins_a: i2s@0 {
pin_i2s0 {
pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
<MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
<MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
<MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
<MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
drive-strength = <MTK_DRIVE_12mA>;
bias-pull-down;
};
};
i2s1_pins_a: i2s@1 {
pin_i2s1 {
pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
<MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
<MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
<MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
<MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
drive-strength = <MTK_DRIVE_12mA>;
bias-pull-down;
};
};
key_pins_a: keys@0 {
pins_keys {
pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
<MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
input-enable;
};
};
led_pins_a: leds@0 {
pins_leds {
pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
<MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
<MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
};
};
mmc0_pins_default: mmc0default {
pins_cmd_dat {
pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
<MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
<MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
<MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
<MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
<MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
<MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
<MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
<MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
input-enable;
bias-pull-up;
};
pins_clk {
pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
bias-pull-down;
};
pins_rst {
pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
bias-pull-up;
};
};
mmc0_pins_uhs: mmc0 {
pins_cmd_dat {
pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
<MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
<MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
<MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
<MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
<MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
<MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
<MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
<MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_2mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins_clk {
pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_2mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
};
pins_rst {
pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
bias-pull-up;
};
};
mmc1_pins_default: mmc1default {
pins_cmd_dat {
pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
<MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
<MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
<MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
<MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
pins_clk {
pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
bias-pull-down;
drive-strength = <MTK_DRIVE_4mA>;
};
};
mmc1_pins_uhs: mmc1 {
pins_cmd_dat {
pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
<MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
<MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
<MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
<MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
input-enable;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
};
pins_clk {
pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_4mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
spi0_pins_a: spi@0 {
pins_spi {
pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
<MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
<MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
<MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
bias-disable;
};
};
pwm_pins_a: pwm@0 {
pins_pwm {
pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
<MT7623_PIN_204_PWM1_FUNC_PWM1>,
<MT7623_PIN_205_PWM2_FUNC_PWM2>,
<MT7623_PIN_206_PWM3_FUNC_PWM3>,
<MT7623_PIN_207_PWM4_FUNC_PWM4>;
};
};
uart0_pins_a: uart@0 {
pins_dat {
pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
<MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
};
};
uart1_pins_a: uart@1 {
pins_dat {
pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
<MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pins_a>;
status = "okay";
};
&pwrap {
mt6323 {
mt6323led: led {
compatible = "mediatek,mt6323-led";
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
label = "bpi-r2:isink:green";
default-state = "off";
};
led@1 {
reg = <1>;
label = "bpi-r2:isink:red";
default-state = "off";
};
led@2 {
reg = <2>;
label = "bpi-r2:isink:blue";
default-state = "off";
};
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins_a>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "disabled";
};
&u3phy1 {
status = "okay";
};
&u3phy2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins_a>;
status = "disabled";
};
&uart2 {
status = "okay";
};
&usb1 {
vusb33-supply = <&mt6323_vusb_reg>;
status = "okay";
};
&usb2 {
vusb33-supply = <&mt6323_vusb_reg>;
status = "okay";
};

168
target/linux/mediatek/files/drivers/char/hw_random/mtk-rng.c Normal file
View File

@@ -0,0 +1,168 @@
/*
* Driver for Mediatek Hardware Random Number Generator
*
* Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define MTK_RNG_DEV KBUILD_MODNAME
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/hw_random.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#define USEC_POLL 2
#define TIMEOUT_POLL 20
#define RNG_CTRL 0x00
#define RNG_EN BIT(0)
#define RNG_READY BIT(31)
#define RNG_DATA 0x08
#define to_mtk_rng(p) container_of(p, struct mtk_rng, rng)
struct mtk_rng {
void __iomem *base;
struct clk *clk;
struct hwrng rng;
};
static int mtk_rng_init(struct hwrng *rng)
{
struct mtk_rng *priv = to_mtk_rng(rng);
u32 val;
int err;
err = clk_prepare_enable(priv->clk);
if (err)
return err;
val = readl(priv->base + RNG_CTRL);
val |= RNG_EN;
writel(val, priv->base + RNG_CTRL);
return 0;
}
static void mtk_rng_cleanup(struct hwrng *rng)
{
struct mtk_rng *priv = to_mtk_rng(rng);
u32 val;
val = readl(priv->base + RNG_CTRL);
val &= ~RNG_EN;
writel(val, priv->base + RNG_CTRL);
clk_disable_unprepare(priv->clk);
}
static bool mtk_rng_wait_ready(struct hwrng *rng, bool wait)
{
struct mtk_rng *priv = to_mtk_rng(rng);
int ready;
ready = readl(priv->base + RNG_CTRL) & RNG_READY;
if (!ready && wait)
readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready,
ready & RNG_READY, USEC_POLL,
TIMEOUT_POLL);
return !!ready;
}
static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
{
struct mtk_rng *priv = to_mtk_rng(rng);
int retval = 0;
while (max >= sizeof(u32)) {
if (!mtk_rng_wait_ready(rng, wait))
break;
*(u32 *)buf = readl(priv->base + RNG_DATA);
retval += sizeof(u32);
buf += sizeof(u32);
max -= sizeof(u32);
}
return retval || !wait ? retval : -EIO;
}
static int mtk_rng_probe(struct platform_device *pdev)
{
struct resource *res;
int ret;
struct mtk_rng *priv;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "no iomem resource\n");
return -ENXIO;
}
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->rng.name = pdev->name;
priv->rng.init = mtk_rng_init;
priv->rng.cleanup = mtk_rng_cleanup;
priv->rng.read = mtk_rng_read;
priv->clk = devm_clk_get(&pdev->dev, "rng");
if (IS_ERR(priv->clk)) {
ret = PTR_ERR(priv->clk);
dev_err(&pdev->dev, "no clock for device: %d\n", ret);
return ret;
}
priv->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
ret = devm_hwrng_register(&pdev->dev, &priv->rng);
if (ret) {
dev_err(&pdev->dev, "failed to register rng device: %d\n",
ret);
return ret;
}
dev_info(&pdev->dev, "registered RNG driver\n");
return 0;
}
static const struct of_device_id mtk_rng_match[] = {
{ .compatible = "mediatek,mt7623-rng" },
{},
};
MODULE_DEVICE_TABLE(of, mtk_rng_match);
static struct platform_driver mtk_rng_driver = {
.probe = mtk_rng_probe,
.driver = {
.name = MTK_RNG_DEV,
.of_match_table = mtk_rng_match,
},
};
module_platform_driver(mtk_rng_driver);
MODULE_DESCRIPTION("Mediatek Random Number Generator Driver");
MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
MODULE_LICENSE("GPL");

2
target/linux/mediatek/files/drivers/crypto/mediatek/Makefile Normal file
View File

@@ -0,0 +1,2 @@
obj-$(CONFIG_CRYPTO_DEV_MEDIATEK) += mtk-crypto.o
mtk-crypto-objs:= mtk-platform.o mtk-aes.o mtk-sha.o

1304
target/linux/mediatek/files/drivers/crypto/mediatek/mtk-aes.c Normal file
View File

File diff suppressed because it is too large Load Diff

607
target/linux/mediatek/files/drivers/crypto/mediatek/mtk-platform.c Normal file
View File

@@ -0,0 +1,607 @@
/*
* Driver for EIP97 cryptographic accelerator.
*
* Copyright (c) 2016 Ryder Lee <ryder.lee@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/clk.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include "mtk-platform.h"
#define MTK_BURST_SIZE_MSK GENMASK(7, 4)
#define MTK_BURST_SIZE(x) ((x) << 4)
#define MTK_DESC_SIZE(x) ((x) << 0)
#define MTK_DESC_OFFSET(x) ((x) << 16)
#define MTK_DESC_FETCH_SIZE(x) ((x) << 0)
#define MTK_DESC_FETCH_THRESH(x) ((x) << 16)
#define MTK_DESC_OVL_IRQ_EN BIT(25)
#define MTK_DESC_ATP_PRESENT BIT(30)
#define MTK_DFSE_IDLE GENMASK(3, 0)
#define MTK_DFSE_THR_CTRL_EN BIT(30)
#define MTK_DFSE_THR_CTRL_RESET BIT(31)
#define MTK_DFSE_RING_ID(x) (((x) >> 12) & GENMASK(3, 0))
#define MTK_DFSE_MIN_DATA(x) ((x) << 0)
#define MTK_DFSE_MAX_DATA(x) ((x) << 8)
#define MTK_DFE_MIN_CTRL(x) ((x) << 16)
#define MTK_DFE_MAX_CTRL(x) ((x) << 24)
#define MTK_IN_BUF_MIN_THRESH(x) ((x) << 8)
#define MTK_IN_BUF_MAX_THRESH(x) ((x) << 12)
#define MTK_OUT_BUF_MIN_THRESH(x) ((x) << 0)
#define MTK_OUT_BUF_MAX_THRESH(x) ((x) << 4)
#define MTK_IN_TBUF_SIZE(x) (((x) >> 4) & GENMASK(3, 0))
#define MTK_IN_DBUF_SIZE(x) (((x) >> 8) & GENMASK(3, 0))
#define MTK_OUT_DBUF_SIZE(x) (((x) >> 16) & GENMASK(3, 0))
#define MTK_CMD_FIFO_SIZE(x) (((x) >> 8) & GENMASK(3, 0))
#define MTK_RES_FIFO_SIZE(x) (((x) >> 12) & GENMASK(3, 0))
#define MTK_PE_TK_LOC_AVL BIT(2)
#define MTK_PE_PROC_HELD BIT(14)
#define MTK_PE_TK_TIMEOUT_EN BIT(22)
#define MTK_PE_INPUT_DMA_ERR BIT(0)
#define MTK_PE_OUTPUT_DMA_ERR BIT(1)
#define MTK_PE_PKT_PORC_ERR BIT(2)
#define MTK_PE_PKT_TIMEOUT BIT(3)
#define MTK_PE_FATAL_ERR BIT(14)
#define MTK_PE_INPUT_DMA_ERR_EN BIT(16)
#define MTK_PE_OUTPUT_DMA_ERR_EN BIT(17)
#define MTK_PE_PKT_PORC_ERR_EN BIT(18)
#define MTK_PE_PKT_TIMEOUT_EN BIT(19)
#define MTK_PE_FATAL_ERR_EN BIT(30)
#define MTK_PE_INT_OUT_EN BIT(31)
#define MTK_HIA_SIGNATURE ((u16)0x35ca)
#define MTK_HIA_DATA_WIDTH(x) (((x) >> 25) & GENMASK(1, 0))
#define MTK_HIA_DMA_LENGTH(x) (((x) >> 20) & GENMASK(4, 0))
#define MTK_CDR_STAT_CLR GENMASK(4, 0)
#define MTK_RDR_STAT_CLR GENMASK(7, 0)
#define MTK_AIC_INT_MSK GENMASK(5, 0)
#define MTK_AIC_VER_MSK (GENMASK(15, 0) | GENMASK(27, 20))
#define MTK_AIC_VER11 0x011036c9
#define MTK_AIC_VER12 0x012036c9
#define MTK_AIC_G_CLR GENMASK(30, 20)
/**
* EIP97 is an integrated security subsystem to accelerate cryptographic
* functions and protocols to offload the host processor.
* Some important hardware modules are briefly introduced below:
*
* Host Interface Adapter(HIA) - the main interface between the host
* system and the hardware subsystem. It is responsible for attaching
* processing engine to the specific host bus interface and provides a
* standardized software view for off loading tasks to the engine.
*
* Command Descriptor Ring Manager(CDR Manager) - keeps track of how many
* CD the host has prepared in the CDR. It monitors the fill level of its
* CD-FIFO and if there's sufficient space for the next block of descriptors,
* then it fires off a DMA request to fetch a block of CDs.
*
* Data fetch engine(DFE) - It is responsible for parsing the CD and
* setting up the required control and packet data DMA transfers from
* system memory to the processing engine.
*
* Result Descriptor Ring Manager(RDR Manager) - same as CDR Manager,
* but target is result descriptors, Moreover, it also handles the RD
* updates under control of the DSE. For each packet data segment
* processed, the DSE triggers the RDR Manager to write the updated RD.
* If triggered to update, the RDR Manager sets up a DMA operation to
* copy the RD from the DSE to the correct location in the RDR.
*
* Data Store Engine(DSE) - It is responsible for parsing the prepared RD
* and setting up the required control and packet data DMA transfers from
* the processing engine to system memory.
*
* Advanced Interrupt Controllers(AICs) - receive interrupt request signals
* from various sources and combine them into one interrupt output.
* The AICs are used by:
* - One for the HIA global and processing engine interrupts.
* - The others for the descriptor ring interrupts.
*/
/* Cryptographic engine capabilities */
struct mtk_sys_cap {
/* host interface adapter */
u32 hia_ver;
u32 hia_opt;
/* packet engine */
u32 pkt_eng_opt;
/* global hardware */
u32 hw_opt;
};
static void mtk_desc_ring_link(struct mtk_cryp *cryp, u32 mask)
{
/* Assign rings to DFE/DSE thread and enable it */
writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DFE_THR_CTRL);
writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DSE_THR_CTRL);
}
static void mtk_dfe_dse_buf_setup(struct mtk_cryp *cryp,
struct mtk_sys_cap *cap)
{
u32 width = MTK_HIA_DATA_WIDTH(cap->hia_opt) + 2;
u32 len = MTK_HIA_DMA_LENGTH(cap->hia_opt) - 1;
u32 ipbuf = min((u32)MTK_IN_DBUF_SIZE(cap->hw_opt) + width, len);
u32 opbuf = min((u32)MTK_OUT_DBUF_SIZE(cap->hw_opt) + width, len);
u32 itbuf = min((u32)MTK_IN_TBUF_SIZE(cap->hw_opt) + width, len);
writel(MTK_DFSE_MIN_DATA(ipbuf - 1) |
MTK_DFSE_MAX_DATA(ipbuf) |
MTK_DFE_MIN_CTRL(itbuf - 1) |
MTK_DFE_MAX_CTRL(itbuf),
cryp->base + DFE_CFG);
writel(MTK_DFSE_MIN_DATA(opbuf - 1) |
MTK_DFSE_MAX_DATA(opbuf),
cryp->base + DSE_CFG);
writel(MTK_IN_BUF_MIN_THRESH(ipbuf - 1) |
MTK_IN_BUF_MAX_THRESH(ipbuf),
cryp->base + PE_IN_DBUF_THRESH);
writel(MTK_IN_BUF_MIN_THRESH(itbuf - 1) |
MTK_IN_BUF_MAX_THRESH(itbuf),
cryp->base + PE_IN_TBUF_THRESH);
writel(MTK_OUT_BUF_MIN_THRESH(opbuf - 1) |
MTK_OUT_BUF_MAX_THRESH(opbuf),
cryp->base + PE_OUT_DBUF_THRESH);
writel(0, cryp->base + PE_OUT_TBUF_THRESH);
writel(0, cryp->base + PE_OUT_BUF_CTRL);
}
static int mtk_dfe_dse_state_check(struct mtk_cryp *cryp)
{
int ret = -EINVAL;
u32 val;
/* Check for completion of all DMA transfers */
val = readl(cryp->base + DFE_THR_STAT);
if (MTK_DFSE_RING_ID(val) == MTK_DFSE_IDLE) {
val = readl(cryp->base + DSE_THR_STAT);
if (MTK_DFSE_RING_ID(val) == MTK_DFSE_IDLE)
ret = 0;
}
if (!ret) {
/* Take DFE/DSE thread out of reset */
writel(0, cryp->base + DFE_THR_CTRL);
writel(0, cryp->base + DSE_THR_CTRL);
} else {
return -EBUSY;
}
return 0;
}
static int mtk_dfe_dse_reset(struct mtk_cryp *cryp)
{
int err;
/* Reset DSE/DFE and correct system priorities for all rings. */
writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DFE_THR_CTRL);
writel(0, cryp->base + DFE_PRIO_0);
writel(0, cryp->base + DFE_PRIO_1);
writel(0, cryp->base + DFE_PRIO_2);
writel(0, cryp->base + DFE_PRIO_3);
writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DSE_THR_CTRL);
writel(0, cryp->base + DSE_PRIO_0);
writel(0, cryp->base + DSE_PRIO_1);
writel(0, cryp->base + DSE_PRIO_2);
writel(0, cryp->base + DSE_PRIO_3);
err = mtk_dfe_dse_state_check(cryp);
if (err)
return err;
return 0;
}
static void mtk_cmd_desc_ring_setup(struct mtk_cryp *cryp,
int i, struct mtk_sys_cap *cap)
{
/* Full descriptor that fits FIFO minus one */
u32 count =
((1 << MTK_CMD_FIFO_SIZE(cap->hia_opt)) / MTK_DESC_SZ) - 1;
/* Temporarily disable external triggering */
writel(0, cryp->base + CDR_CFG(i));
/* Clear CDR count */
writel(MTK_CNT_RST, cryp->base + CDR_PREP_COUNT(i));
writel(MTK_CNT_RST, cryp->base + CDR_PROC_COUNT(i));
writel(0, cryp->base + CDR_PREP_PNTR(i));
writel(0, cryp->base + CDR_PROC_PNTR(i));
writel(0, cryp->base + CDR_DMA_CFG(i));
/* Configure CDR host address space */
writel(0, cryp->base + CDR_BASE_ADDR_HI(i));
writel(cryp->ring[i]->cmd_dma, cryp->base + CDR_BASE_ADDR_LO(i));
writel(MTK_DESC_RING_SZ, cryp->base + CDR_RING_SIZE(i));
/* Clear and disable all CDR interrupts */
writel(MTK_CDR_STAT_CLR, cryp->base + CDR_STAT(i));
/*
* Set command descriptor offset and enable additional
* token present in descriptor.
*/
writel(MTK_DESC_SIZE(MTK_DESC_SZ) |
MTK_DESC_OFFSET(MTK_DESC_OFF) |
MTK_DESC_ATP_PRESENT,
cryp->base + CDR_DESC_SIZE(i));
writel(MTK_DESC_FETCH_SIZE(count * MTK_DESC_OFF) |
MTK_DESC_FETCH_THRESH(count * MTK_DESC_SZ),
cryp->base + CDR_CFG(i));
}
static void mtk_res_desc_ring_setup(struct mtk_cryp *cryp,
int i, struct mtk_sys_cap *cap)
{
u32 rndup = 2;
u32 count = ((1 << MTK_RES_FIFO_SIZE(cap->hia_opt)) / rndup) - 1;
/* Temporarily disable external triggering */
writel(0, cryp->base + RDR_CFG(i));
/* Clear RDR count */
writel(MTK_CNT_RST, cryp->base + RDR_PREP_COUNT(i));
writel(MTK_CNT_RST, cryp->base + RDR_PROC_COUNT(i));
writel(0, cryp->base + RDR_PREP_PNTR(i));
writel(0, cryp->base + RDR_PROC_PNTR(i));
writel(0, cryp->base + RDR_DMA_CFG(i));
/* Configure RDR host address space */
writel(0, cryp->base + RDR_BASE_ADDR_HI(i));
writel(cryp->ring[i]->res_dma, cryp->base + RDR_BASE_ADDR_LO(i));
writel(MTK_DESC_RING_SZ, cryp->base + RDR_RING_SIZE(i));
writel(MTK_RDR_STAT_CLR, cryp->base + RDR_STAT(i));
/*
* RDR manager generates update interrupts on a per-completed-packet,
* and the rd_proc_thresh_irq interrupt is fired when proc_pkt_count
* for the RDR exceeds the number of packets.
*/
writel(MTK_RDR_PROC_THRESH | MTK_RDR_PROC_MODE,
cryp->base + RDR_THRESH(i));
/*
* Configure a threshold and time-out value for the processed
* result descriptors (or complete packets) that are written to
* the RDR.
*/
writel(MTK_DESC_SIZE(MTK_DESC_SZ) | MTK_DESC_OFFSET(MTK_DESC_OFF),
cryp->base + RDR_DESC_SIZE(i));
/*
* Configure HIA fetch size and fetch threshold that are used to
* fetch blocks of multiple descriptors.
*/
writel(MTK_DESC_FETCH_SIZE(count * MTK_DESC_OFF) |
MTK_DESC_FETCH_THRESH(count * rndup) |
MTK_DESC_OVL_IRQ_EN,
cryp->base + RDR_CFG(i));
}
static int mtk_packet_engine_setup(struct mtk_cryp *cryp)
{
struct mtk_sys_cap cap;
int i, err;
u32 val;
cap.hia_ver = readl(cryp->base + HIA_VERSION);
cap.hia_opt = readl(cryp->base + HIA_OPTIONS);
cap.hw_opt = readl(cryp->base + EIP97_OPTIONS);
if (!(((u16)cap.hia_ver) == MTK_HIA_SIGNATURE))
return -EINVAL;
/* Configure endianness conversion method for master (DMA) interface */
writel(0, cryp->base + EIP97_MST_CTRL);
/* Set HIA burst size */
val = readl(cryp->base + HIA_MST_CTRL);
val &= ~MTK_BURST_SIZE_MSK;
val |= MTK_BURST_SIZE(5);
writel(val, cryp->base + HIA_MST_CTRL);
err = mtk_dfe_dse_reset(cryp);
if (err) {
dev_err(cryp->dev, "Failed to reset DFE and DSE.\n");
return err;
}
mtk_dfe_dse_buf_setup(cryp, &cap);
/* Enable the 4 rings for the packet engines. */
mtk_desc_ring_link(cryp, 0xf);
for (i = 0; i < MTK_RING_MAX; i++) {
mtk_cmd_desc_ring_setup(cryp, i, &cap);
mtk_res_desc_ring_setup(cryp, i, &cap);
}
writel(MTK_PE_TK_LOC_AVL | MTK_PE_PROC_HELD | MTK_PE_TK_TIMEOUT_EN,
cryp->base + PE_TOKEN_CTRL_STAT);
/* Clear all pending interrupts */
writel(MTK_AIC_G_CLR, cryp->base + AIC_G_ACK);
writel(MTK_PE_INPUT_DMA_ERR | MTK_PE_OUTPUT_DMA_ERR |
MTK_PE_PKT_PORC_ERR | MTK_PE_PKT_TIMEOUT |
MTK_PE_FATAL_ERR | MTK_PE_INPUT_DMA_ERR_EN |
MTK_PE_OUTPUT_DMA_ERR_EN | MTK_PE_PKT_PORC_ERR_EN |
MTK_PE_PKT_TIMEOUT_EN | MTK_PE_FATAL_ERR_EN |
MTK_PE_INT_OUT_EN,
cryp->base + PE_INTERRUPT_CTRL_STAT);
return 0;
}
static int mtk_aic_cap_check(struct mtk_cryp *cryp, int hw)
{
u32 val;
if (hw == MTK_RING_MAX)
val = readl(cryp->base + AIC_G_VERSION);
else
val = readl(cryp->base + AIC_VERSION(hw));
val &= MTK_AIC_VER_MSK;
if (val != MTK_AIC_VER11 && val != MTK_AIC_VER12)
return -ENXIO;
if (hw == MTK_RING_MAX)
val = readl(cryp->base + AIC_G_OPTIONS);
else
val = readl(cryp->base + AIC_OPTIONS(hw));
val &= MTK_AIC_INT_MSK;
if (!val || val > 32)
return -ENXIO;
return 0;
}
static int mtk_aic_init(struct mtk_cryp *cryp, int hw)
{
int err;
err = mtk_aic_cap_check(cryp, hw);
if (err)
return err;
/* Disable all interrupts and set initial configuration */
if (hw == MTK_RING_MAX) {
writel(0, cryp->base + AIC_G_ENABLE_CTRL);
writel(0, cryp->base + AIC_G_POL_CTRL);
writel(0, cryp->base + AIC_G_TYPE_CTRL);
writel(0, cryp->base + AIC_G_ENABLE_SET);
} else {
writel(0, cryp->base + AIC_ENABLE_CTRL(hw));
writel(0, cryp->base + AIC_POL_CTRL(hw));
writel(0, cryp->base + AIC_TYPE_CTRL(hw));
writel(0, cryp->base + AIC_ENABLE_SET(hw));
}
return 0;
}
static int mtk_accelerator_init(struct mtk_cryp *cryp)
{
int i, err;
/* Initialize advanced interrupt controller(AIC) */
for (i = 0; i < MTK_IRQ_NUM; i++) {
err = mtk_aic_init(cryp, i);
if (err) {
dev_err(cryp->dev, "Failed to initialize AIC.\n");
return err;
}
}
/* Initialize packet engine */
err = mtk_packet_engine_setup(cryp);
if (err) {
dev_err(cryp->dev, "Failed to configure packet engine.\n");
return err;
}
return 0;
}
static void mtk_desc_dma_free(struct mtk_cryp *cryp)
{
int i;
for (i = 0; i < MTK_RING_MAX; i++) {
dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
cryp->ring[i]->res_base,
cryp->ring[i]->res_dma);
dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
cryp->ring[i]->cmd_base,
cryp->ring[i]->cmd_dma);
kfree(cryp->ring[i]);
}
}
static int mtk_desc_ring_alloc(struct mtk_cryp *cryp)
{
struct mtk_ring **ring = cryp->ring;
int i, err = ENOMEM;
for (i = 0; i < MTK_RING_MAX; i++) {
ring[i] = kzalloc(sizeof(**ring), GFP_KERNEL);
if (!ring[i])
goto err_cleanup;
ring[i]->cmd_base = dma_zalloc_coherent(cryp->dev,
MTK_DESC_RING_SZ,
&ring[i]->cmd_dma,
GFP_KERNEL);
if (!ring[i]->cmd_base)
goto err_cleanup;
ring[i]->res_base = dma_zalloc_coherent(cryp->dev,
MTK_DESC_RING_SZ,
&ring[i]->res_dma,
GFP_KERNEL);
if (!ring[i]->res_base)
goto err_cleanup;
ring[i]->cmd_next = ring[i]->cmd_base;
ring[i]->res_next = ring[i]->res_base;
}
return 0;
err_cleanup:
for (; i--; ) {
dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
ring[i]->res_base, ring[i]->res_dma);
dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
ring[i]->cmd_base, ring[i]->cmd_dma);
kfree(ring[i]);
}
return err;
}
static int mtk_crypto_probe(struct platform_device *pdev)
{
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
struct mtk_cryp *cryp;
int i, err;
cryp = devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL);
if (!cryp)
return -ENOMEM;
cryp->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(cryp->base))
return PTR_ERR(cryp->base);
for (i = 0; i < MTK_IRQ_NUM; i++) {
cryp->irq[i] = platform_get_irq(pdev, i);
if (cryp->irq[i] < 0) {
dev_err(cryp->dev, "no IRQ:%d resource info\n", i);
return -ENXIO;
}
}
cryp->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
cryp->clk_cryp = devm_clk_get(&pdev->dev, "cryp");
if (IS_ERR(cryp->clk_ethif) || IS_ERR(cryp->clk_cryp))
return -EPROBE_DEFER;
cryp->dev = &pdev->dev;
pm_runtime_enable(cryp->dev);
pm_runtime_get_sync(cryp->dev);
err = clk_prepare_enable(cryp->clk_ethif);
if (err)
goto err_clk_ethif;
err = clk_prepare_enable(cryp->clk_cryp);
if (err)
goto err_clk_cryp;
/* Allocate four command/result descriptor rings */
err = mtk_desc_ring_alloc(cryp);
if (err) {
dev_err(cryp->dev, "Unable to allocate descriptor rings.\n");
goto err_resource;
}
/* Initialize hardware modules */
err = mtk_accelerator_init(cryp);
if (err) {
dev_err(cryp->dev, "Failed to initialize cryptographic engine.\n");
goto err_engine;
}
err = mtk_cipher_alg_register(cryp);
if (err) {
dev_err(cryp->dev, "Unable to register cipher algorithm.\n");
goto err_cipher;
}
err = mtk_hash_alg_register(cryp);
if (err) {
dev_err(cryp->dev, "Unable to register hash algorithm.\n");
goto err_hash;
}
platform_set_drvdata(pdev, cryp);
return 0;
err_hash:
mtk_cipher_alg_release(cryp);
err_cipher:
mtk_dfe_dse_reset(cryp);
err_engine:
mtk_desc_dma_free(cryp);
err_resource:
clk_disable_unprepare(cryp->clk_cryp);
err_clk_cryp:
clk_disable_unprepare(cryp->clk_ethif);
err_clk_ethif:
pm_runtime_put_sync(cryp->dev);
pm_runtime_disable(cryp->dev);
return err;
}
static int mtk_crypto_remove(struct platform_device *pdev)
{
struct mtk_cryp *cryp = platform_get_drvdata(pdev);
mtk_hash_alg_release(cryp);
mtk_cipher_alg_release(cryp);
mtk_desc_dma_free(cryp);
clk_disable_unprepare(cryp->clk_cryp);
clk_disable_unprepare(cryp->clk_ethif);
pm_runtime_put_sync(cryp->dev);
pm_runtime_disable(cryp->dev);
platform_set_drvdata(pdev, NULL);
return 0;
}
static const struct of_device_id of_crypto_id[] = {
{ .compatible = "mediatek,eip97-crypto" },
{},
};
MODULE_DEVICE_TABLE(of, of_crypto_id);
static struct platform_driver mtk_crypto_driver = {
.probe = mtk_crypto_probe,
.remove = mtk_crypto_remove,
.driver = {
.name = "mtk-crypto",
.owner = THIS_MODULE,
.of_match_table = of_crypto_id,
},
};
module_platform_driver(mtk_crypto_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Ryder Lee <ryder.lee@mediatek.com>");
MODULE_DESCRIPTION("Cryptographic accelerator driver for EIP97");

237
target/linux/mediatek/files/drivers/crypto/mediatek/mtk-platform.h Normal file
View File

@@ -0,0 +1,237 @@
/*
* Driver for EIP97 cryptographic accelerator.
*
* Copyright (c) 2016 Ryder Lee <ryder.lee@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __MTK_PLATFORM_H_
#define __MTK_PLATFORM_H_
#include <crypto/algapi.h>
#include <crypto/internal/aead.h>
#include <crypto/internal/hash.h>
#include <crypto/scatterwalk.h>
#include <crypto/skcipher.h>
#include <linux/crypto.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/scatterlist.h>
#include "mtk-regs.h"
#define MTK_RDR_PROC_THRESH BIT(0)
#define MTK_RDR_PROC_MODE BIT(23)
#define MTK_CNT_RST BIT(31)
#define MTK_IRQ_RDR0 BIT(1)
#define MTK_IRQ_RDR1 BIT(3)
#define MTK_IRQ_RDR2 BIT(5)
#define MTK_IRQ_RDR3 BIT(7)
#define SIZE_IN_WORDS(x) ((x) >> 2)
/**
* Ring 0/1 are used by AES encrypt and decrypt.
* Ring 2/3 are used by SHA.
*/
enum {
MTK_RING0,
MTK_RING1,
MTK_RING2,
MTK_RING3,
MTK_RING_MAX
};
#define MTK_REC_NUM (MTK_RING_MAX / 2)
#define MTK_IRQ_NUM 5
/**
* struct mtk_desc - DMA descriptor
* @hdr: the descriptor control header
* @buf: DMA address of input buffer segment
* @ct: DMA address of command token that control operation flow
* @ct_hdr: the command token control header
* @tag: the user-defined field
* @tfm: DMA address of transform state
* @bound: align descriptors offset boundary
*
* Structure passed to the crypto engine to describe where source
* data needs to be fetched and how it needs to be processed.
*/
struct mtk_desc {
__le32 hdr;
__le32 buf;
__le32 ct;
__le32 ct_hdr;
__le32 tag;
__le32 tfm;
__le32 bound[2];
};
#define MTK_DESC_NUM 512
#define MTK_DESC_OFF SIZE_IN_WORDS(sizeof(struct mtk_desc))
#define MTK_DESC_SZ (MTK_DESC_OFF - 2)
#define MTK_DESC_RING_SZ ((sizeof(struct mtk_desc) * MTK_DESC_NUM))
#define MTK_DESC_CNT(x) ((MTK_DESC_OFF * (x)) << 2)
#define MTK_DESC_LAST cpu_to_le32(BIT(22))
#define MTK_DESC_FIRST cpu_to_le32(BIT(23))
#define MTK_DESC_BUF_LEN(x) cpu_to_le32(x)
#define MTK_DESC_CT_LEN(x) cpu_to_le32((x) << 24)
/**
* struct mtk_ring - Descriptor ring
* @cmd_base: pointer to command descriptor ring base
* @cmd_next: pointer to the next command descriptor
* @cmd_dma: DMA address of command descriptor ring
* @res_base: pointer to result descriptor ring base
* @res_next: pointer to the next result descriptor
* @res_prev: pointer to the previous result descriptor
* @res_dma: DMA address of result descriptor ring
*
* A descriptor ring is a circular buffer that is used to manage
* one or more descriptors. There are two type of descriptor rings;
* the command descriptor ring and result descriptor ring.
*/
struct mtk_ring {
struct mtk_desc *cmd_base;
struct mtk_desc *cmd_next;
dma_addr_t cmd_dma;
struct mtk_desc *res_base;
struct mtk_desc *res_next;
struct mtk_desc *res_prev;
dma_addr_t res_dma;
};
/**
* struct mtk_aes_dma - Structure that holds sg list info
* @sg: pointer to scatter-gather list
* @nents: number of entries in the sg list
* @remainder: remainder of sg list
* @sg_len: number of entries in the sg mapped list
*/
struct mtk_aes_dma {
struct scatterlist *sg;
int nents;
u32 remainder;
u32 sg_len;
};
struct mtk_aes_base_ctx;
struct mtk_aes_rec;
struct mtk_cryp;
typedef int (*mtk_aes_fn)(struct mtk_cryp *cryp, struct mtk_aes_rec *aes);
/**
* struct mtk_aes_rec - AES operation record
* @cryp: pointer to Cryptographic device
* @queue: crypto request queue
* @areq: pointer to async request
* @done_task: the tasklet is use in AES interrupt
* @queue_task: the tasklet is used to dequeue request
* @ctx: pointer to current context
* @src: the structure that holds source sg list info
* @dst: the structure that holds destination sg list info
* @aligned_sg: the scatter list is use to alignment
* @real_dst: pointer to the destination sg list
* @resume: pointer to resume function
* @total: request buffer length
* @buf: pointer to page buffer
* @id: the current use of ring
* @flags: it's describing AES operation state
* @lock: the async queue lock
*
* Structure used to record AES execution state.
*/
struct mtk_aes_rec {
struct mtk_cryp *cryp;
struct crypto_queue queue;
struct crypto_async_request *areq;
struct tasklet_struct done_task;
struct tasklet_struct queue_task;
struct mtk_aes_base_ctx *ctx;
struct mtk_aes_dma src;
struct mtk_aes_dma dst;
struct scatterlist aligned_sg;
struct scatterlist *real_dst;
mtk_aes_fn resume;
size_t total;
void *buf;
u8 id;
unsigned long flags;
/* queue lock */
spinlock_t lock;
};
/**
* struct mtk_sha_rec - SHA operation record
* @cryp: pointer to Cryptographic device
* @queue: crypto request queue
* @req: pointer to ahash request
* @done_task: the tasklet is use in SHA interrupt
* @queue_task: the tasklet is used to dequeue request
* @id: the current use of ring
* @flags: it's describing SHA operation state
* @lock: the async queue lock
*
* Structure used to record SHA execution state.
*/
struct mtk_sha_rec {
struct mtk_cryp *cryp;
struct crypto_queue queue;
struct ahash_request *req;
struct tasklet_struct done_task;
struct tasklet_struct queue_task;
u8 id;
unsigned long flags;
/* queue lock */
spinlock_t lock;
};
/**
* struct mtk_cryp - Cryptographic device
* @base: pointer to mapped register I/O base
* @dev: pointer to device
* @clk_ethif: pointer to ethif clock
* @clk_cryp: pointer to crypto clock
* @irq: global system and rings IRQ
* @ring: pointer to descriptor rings
* @aes: pointer to operation record of AES
* @sha: pointer to operation record of SHA
* @aes_list: device list of AES
* @sha_list: device list of SHA
* @rec: it's used to select SHA record for tfm
*
* Structure storing cryptographic device information.
*/
struct mtk_cryp {
void __iomem *base;
struct device *dev;
struct clk *clk_ethif;
struct clk *clk_cryp;
int irq[MTK_IRQ_NUM];
struct mtk_ring *ring[MTK_RING_MAX];
struct mtk_aes_rec *aes[MTK_REC_NUM];
struct mtk_sha_rec *sha[MTK_REC_NUM];
struct list_head aes_list;
struct list_head sha_list;
bool rec;
};
int mtk_cipher_alg_register(struct mtk_cryp *cryp);
void mtk_cipher_alg_release(struct mtk_cryp *cryp);
int mtk_hash_alg_register(struct mtk_cryp *cryp);
void mtk_hash_alg_release(struct mtk_cryp *cryp);
#endif /* __MTK_PLATFORM_H_ */

194
target/linux/mediatek/files/drivers/crypto/mediatek/mtk-regs.h Normal file
View File

@@ -0,0 +1,194 @@
/*
* Support for MediaTek cryptographic accelerator.
*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ryder Lee <ryder.lee@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*
*/
#ifndef __MTK_REGS_H__
#define __MTK_REGS_H__
/* HIA, Command Descriptor Ring Manager */
#define CDR_BASE_ADDR_LO(x) (0x0 + ((x) << 12))
#define CDR_BASE_ADDR_HI(x) (0x4 + ((x) << 12))
#define CDR_DATA_BASE_ADDR_LO(x) (0x8 + ((x) << 12))
#define CDR_DATA_BASE_ADDR_HI(x) (0xC + ((x) << 12))
#define CDR_ACD_BASE_ADDR_LO(x) (0x10 + ((x) << 12))
#define CDR_ACD_BASE_ADDR_HI(x) (0x14 + ((x) << 12))
#define CDR_RING_SIZE(x) (0x18 + ((x) << 12))
#define CDR_DESC_SIZE(x) (0x1C + ((x) << 12))
#define CDR_CFG(x) (0x20 + ((x) << 12))
#define CDR_DMA_CFG(x) (0x24 + ((x) << 12))
#define CDR_THRESH(x) (0x28 + ((x) << 12))
#define CDR_PREP_COUNT(x) (0x2C + ((x) << 12))
#define CDR_PROC_COUNT(x) (0x30 + ((x) << 12))
#define CDR_PREP_PNTR(x) (0x34 + ((x) << 12))
#define CDR_PROC_PNTR(x) (0x38 + ((x) << 12))
#define CDR_STAT(x) (0x3C + ((x) << 12))
/* HIA, Result Descriptor Ring Manager */
#define RDR_BASE_ADDR_LO(x) (0x800 + ((x) << 12))
#define RDR_BASE_ADDR_HI(x) (0x804 + ((x) << 12))
#define RDR_DATA_BASE_ADDR_LO(x) (0x808 + ((x) << 12))
#define RDR_DATA_BASE_ADDR_HI(x) (0x80C + ((x) << 12))
#define RDR_ACD_BASE_ADDR_LO(x) (0x810 + ((x) << 12))
#define RDR_ACD_BASE_ADDR_HI(x) (0x814 + ((x) << 12))
#define RDR_RING_SIZE(x) (0x818 + ((x) << 12))
#define RDR_DESC_SIZE(x) (0x81C + ((x) << 12))
#define RDR_CFG(x) (0x820 + ((x) << 12))
#define RDR_DMA_CFG(x) (0x824 + ((x) << 12))
#define RDR_THRESH(x) (0x828 + ((x) << 12))
#define RDR_PREP_COUNT(x) (0x82C + ((x) << 12))
#define RDR_PROC_COUNT(x) (0x830 + ((x) << 12))
#define RDR_PREP_PNTR(x) (0x834 + ((x) << 12))
#define RDR_PROC_PNTR(x) (0x838 + ((x) << 12))
#define RDR_STAT(x) (0x83C + ((x) << 12))
/* HIA, Ring AIC */
#define AIC_POL_CTRL(x) (0xE000 - ((x) << 12))
#define AIC_TYPE_CTRL(x) (0xE004 - ((x) << 12))
#define AIC_ENABLE_CTRL(x) (0xE008 - ((x) << 12))
#define AIC_RAW_STAL(x) (0xE00C - ((x) << 12))
#define AIC_ENABLE_SET(x) (0xE00C - ((x) << 12))
#define AIC_ENABLED_STAT(x) (0xE010 - ((x) << 12))
#define AIC_ACK(x) (0xE010 - ((x) << 12))
#define AIC_ENABLE_CLR(x) (0xE014 - ((x) << 12))
#define AIC_OPTIONS(x) (0xE018 - ((x) << 12))
#define AIC_VERSION(x) (0xE01C - ((x) << 12))
/* HIA, Global AIC */
#define AIC_G_POL_CTRL 0xF800
#define AIC_G_TYPE_CTRL 0xF804
#define AIC_G_ENABLE_CTRL 0xF808
#define AIC_G_RAW_STAT 0xF80C
#define AIC_G_ENABLE_SET 0xF80C
#define AIC_G_ENABLED_STAT 0xF810
#define AIC_G_ACK 0xF810
#define AIC_G_ENABLE_CLR 0xF814
#define AIC_G_OPTIONS 0xF818
#define AIC_G_VERSION 0xF81C
/* HIA, Data Fetch Engine */
#define DFE_CFG 0xF000
#define DFE_PRIO_0 0xF010
#define DFE_PRIO_1 0xF014
#define DFE_PRIO_2 0xF018
#define DFE_PRIO_3 0xF01C
/* HIA, Data Fetch Engine access monitoring for CDR */
#define DFE_RING_REGION_LO(x) (0xF080 + ((x) << 3))
#define DFE_RING_REGION_HI(x) (0xF084 + ((x) << 3))
/* HIA, Data Fetch Engine thread control and status for thread */
#define DFE_THR_CTRL 0xF200
#define DFE_THR_STAT 0xF204
#define DFE_THR_DESC_CTRL 0xF208
#define DFE_THR_DESC_DPTR_LO 0xF210
#define DFE_THR_DESC_DPTR_HI 0xF214
#define DFE_THR_DESC_ACDPTR_LO 0xF218
#define DFE_THR_DESC_ACDPTR_HI 0xF21C
/* HIA, Data Store Engine */
#define DSE_CFG 0xF400
#define DSE_PRIO_0 0xF410
#define DSE_PRIO_1 0xF414
#define DSE_PRIO_2 0xF418
#define DSE_PRIO_3 0xF41C
/* HIA, Data Store Engine access monitoring for RDR */
#define DSE_RING_REGION_LO(x) (0xF480 + ((x) << 3))
#define DSE_RING_REGION_HI(x) (0xF484 + ((x) << 3))
/* HIA, Data Store Engine thread control and status for thread */
#define DSE_THR_CTRL 0xF600
#define DSE_THR_STAT 0xF604
#define DSE_THR_DESC_CTRL 0xF608
#define DSE_THR_DESC_DPTR_LO 0xF610
#define DSE_THR_DESC_DPTR_HI 0xF614
#define DSE_THR_DESC_S_DPTR_LO 0xF618
#define DSE_THR_DESC_S_DPTR_HI 0xF61C
#define DSE_THR_ERROR_STAT 0xF620
/* HIA Global */
#define HIA_MST_CTRL 0xFFF4
#define HIA_OPTIONS 0xFFF8
#define HIA_VERSION 0xFFFC
/* Processing Engine Input Side, Processing Engine */
#define PE_IN_DBUF_THRESH 0x10000
#define PE_IN_TBUF_THRESH 0x10100
/* Packet Engine Configuration / Status Registers */
#define PE_TOKEN_CTRL_STAT 0x11000
#define PE_FUNCTION_EN 0x11004
#define PE_CONTEXT_CTRL 0x11008
#define PE_INTERRUPT_CTRL_STAT 0x11010
#define PE_CONTEXT_STAT 0x1100C
#define PE_OUT_TRANS_CTRL_STAT 0x11018
#define PE_OUT_BUF_CTRL 0x1101C
/* Packet Engine PRNG Registers */
#define PE_PRNG_STAT 0x11040
#define PE_PRNG_CTRL 0x11044
#define PE_PRNG_SEED_L 0x11048
#define PE_PRNG_SEED_H 0x1104C
#define PE_PRNG_KEY_0_L 0x11050
#define PE_PRNG_KEY_0_H 0x11054
#define PE_PRNG_KEY_1_L 0x11058
#define PE_PRNG_KEY_1_H 0x1105C
#define PE_PRNG_RES_0 0x11060
#define PE_PRNG_RES_1 0x11064
#define PE_PRNG_RES_2 0x11068
#define PE_PRNG_RES_3 0x1106C
#define PE_PRNG_LFSR_L 0x11070
#define PE_PRNG_LFSR_H 0x11074
/* Packet Engine AIC */
#define PE_EIP96_AIC_POL_CTRL 0x113C0
#define PE_EIP96_AIC_TYPE_CTRL 0x113C4
#define PE_EIP96_AIC_ENABLE_CTRL 0x113C8
#define PE_EIP96_AIC_RAW_STAT 0x113CC
#define PE_EIP96_AIC_ENABLE_SET 0x113CC
#define PE_EIP96_AIC_ENABLED_STAT 0x113D0
#define PE_EIP96_AIC_ACK 0x113D0
#define PE_EIP96_AIC_ENABLE_CLR 0x113D4
#define PE_EIP96_AIC_OPTIONS 0x113D8
#define PE_EIP96_AIC_VERSION 0x113DC
/* Packet Engine Options & Version Registers */
#define PE_EIP96_OPTIONS 0x113F8
#define PE_EIP96_VERSION 0x113FC
/* Processing Engine Output Side */
#define PE_OUT_DBUF_THRESH 0x11C00
#define PE_OUT_TBUF_THRESH 0x11D00
/* Processing Engine Local AIC */
#define PE_AIC_POL_CTRL 0x11F00
#define PE_AIC_TYPE_CTRL 0x11F04
#define PE_AIC_ENABLE_CTRL 0x11F08
#define PE_AIC_RAW_STAT 0x11F0C
#define PE_AIC_ENABLE_SET 0x11F0C
#define PE_AIC_ENABLED_STAT 0x11F10
#define PE_AIC_ENABLE_CLR 0x11F14
#define PE_AIC_OPTIONS 0x11F18
#define PE_AIC_VERSION 0x11F1C
/* Processing Engine General Configuration and Version */
#define PE_IN_FLIGHT 0x11FF0
#define PE_OPTIONS 0x11FF8
#define PE_VERSION 0x11FFC
/* EIP-97 - Global */
#define EIP97_CLOCK_STATE 0x1FFE4
#define EIP97_FORCE_CLOCK_ON 0x1FFE8
#define EIP97_FORCE_CLOCK_OFF 0x1FFEC
#define EIP97_MST_CTRL 0x1FFF4
#define EIP97_OPTIONS 0x1FFF8
#define EIP97_VERSION 0x1FFFC
#endif /* __MTK_REGS_H__ */

1358
target/linux/mediatek/files/drivers/crypto/mediatek/mtk-sha.c Normal file
View File

File diff suppressed because it is too large Load Diff

22
target/linux/mediatek/image/32.mk
View File

@@ -1,6 +1,6 @@
define Image/BuilduImage
$(CP) $(KDIR)/zImage$(2) $(KDIR)/zImage-$(1)$(2)
cat $(LINUX_DIR)/arch/arm/boot/dts/mt7623-$1.dtb >> $(KDIR)/zImage-$(1)$(2)
cat $(LINUX_DIR)/arch/arm/boot/dts/$1.dtb >> $(KDIR)/zImage-$(1)$(2)
mkimage -A arm -O linux -T kernel -C none -a 0x80008000 -e 0x80008000 -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' -d $(KDIR)/zImage-$(1)$(2) $(KDIR)/uImage-$(1)$(2)
endef
@@ -20,6 +20,7 @@ endif
)
endef
COMPAT_BPI-R2:=bananapi,bpi-r2
COMPAT_EMMC:=mediatek,mt7623-rfb-emmc
COMPAT_NAND:=mediatek,mt7623-rfb-nand
COMPAT_NAND_EPHY:=mediatek,mt7623-rfb-nand-ephy
@@ -28,16 +29,17 @@ define Image/Build/squashfs
$(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
$(CP) $(KDIR)/root.squashfs $(BIN_DIR)/$(IMG_PREFIX)-root.squashfs
$(call Image/Build/SysupgradeCombined,eMMC,squashfs,$$(COMPAT_EMMC))
$(call Image/Build/SysupgradeCombined,mt7623n-bananapi-bpi-r2,squashfs,$$(COMPAT_EMMC))
$(call Image/Build/SysupgradeCombined,mt7623-eMMC,squashfs,$$(COMPAT_BPI-R2))
$(call Image/BuilduImage,NAND)
$(call Image/BuilduImage,NAND-ePHY)
$(call Image/BuilduImage,mt7623-NAND)
$(call Image/BuilduImage,mt7623-NAND-ePHY)
ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
$(call Image/BuilduImage,NAND,-initramfs)
$(call Image/BuilduImage,NAND-ePHY,-initramfs)
$(CP) $(KDIR)/uImage-NAND-initramfs $(BIN_DIR)/$(IMG_PREFIX)-uImage-NAND-initramfs
$(CP) $(KDIR)/uImage-NAND-ePHY-initramfs $(BIN_DIR)/$(IMG_PREFIX)-uImage-NAND-ePHY-initramfs
$(call Image/BuilduImage,mt7623-NAND,-initramfs)
$(call Image/BuilduImage,mt7623-NAND-ePHY,-initramfs)
$(CP) $(KDIR)/uImage-mt7623-NAND-initramfs $(BIN_DIR)/$(IMG_PREFIX)-uImage-NAND-initramfs
$(CP) $(KDIR)/uImage-mt7623-NAND-ePHY-initramfs $(BIN_DIR)/$(IMG_PREFIX)-uImage-NAND-ePHY-initramfs
endif
$(call Image/Build/SysupgradeNAND,NAND,$(1),$(KDIR)/uImage-NAND,$$(COMPAT_NAND))
$(call Image/Build/SysupgradeNAND,NAND-ePHY,$(1),$(KDIR)/uImage-NAND-ePHY,$$(COMPAT_NAND_EPHY))
$(call Image/Build/SysupgradeNAND,mt7623-NAND,$(1),$(KDIR)/uImage-mt7623-NAND,$$(COMPAT_NAND))
$(call Image/Build/SysupgradeNAND,mt7623-NAND-ePHY,$(1),$(KDIR)/uImage-mt7623-NAND-ePHY,$$(COMPAT_NAND_EPHY))
endef

14
target/linux/mediatek/modules.mk Normal file
View File

@@ -0,0 +1,14 @@
define KernelPackage/mediatek_hnat
SUBMENU:=Network Devices
TITLE:=MT7623 HNAT
DEPENDS:=@TARGET_mediatek +kmod-nf-conntrack +iptables-mod-ipmark
KCONFIG:= CONFIG_NET_MEDIATEK_HNAT=y
FILES:= \
$(LINUX_DIR)/drivers/net/ethernet/mediatek/mtk_hnat/mtkhnat.ko
endef
define KernelPackage/mediatek_hnat/description
Kernel modules for MediaTek HW NAT offloading
endef
$(eval $(call KernelPackage,mediatek_hnat))

26
target/linux/mediatek/patches-4.9/0000-pinctrl-esw.patch
View File

@@ -1,26 +0,0 @@
--- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h
+++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
@@ -505,6 +505,9 @@
#define MT7623_PIN_272_G2_RXD3_FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
#define MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
+#define MT7623_PIN_273_ESW_INT_FUNC_GPIO273 (MTK_PIN_NO(273) | 0)
+#define MT7623_PIN_273_ESW_INT_FUNC_ESW_INT (MTK_PIN_NO(273) | 1)
+
#define MT7623_PIN_274_G2_RXDV_FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
#define MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
@@ -1894,8 +1894,9 @@ static const struct mtk_desc_pin mtk_pin
MTK_PIN(
PINCTRL_PIN(273, "GPIO273"),
NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO273")
+ MTK_EINT_FUNCTION(0, 168),
+ MTK_FUNCTION(0, "GPIO273"),
+ MTK_FUNCTION(1, "ESW_INT")
),
MTK_PIN(
PINCTRL_PIN(274, "G2_RXDV"),

53
target/linux/mediatek/patches-4.9/0001-NET-multi-phy-support.patch
View File

@@ -1,53 +0,0 @@
From 1e021917e634b173d466bf0dd3d2ae84e51a77ff Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 27 Jul 2014 09:38:50 +0100
Subject: [PATCH 001/102] NET: multi phy support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/net/phy/phy.c | 9 ++++++---
include/linux/phy.h | 1 +
2 files changed, 7 insertions(+), 3 deletions(-)
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -1035,7 +1035,8 @@ void phy_state_machine(struct work_struc
/* If the link is down, give up on negotiation for now */
if (!phydev->link) {
phydev->state = PHY_NOLINK;
- netif_carrier_off(phydev->attached_dev);
+ if (!phydev->no_auto_carrier_off)
+ netif_carrier_off(phydev->attached_dev);
phydev->adjust_link(phydev->attached_dev);
break;
}
@@ -1127,7 +1128,8 @@ void phy_state_machine(struct work_struc
netif_carrier_on(phydev->attached_dev);
} else {
phydev->state = PHY_NOLINK;
- netif_carrier_off(phydev->attached_dev);
+ if (!phydev->no_auto_carrier_off)
+ netif_carrier_off(phydev->attached_dev);
}
phydev->adjust_link(phydev->attached_dev);
@@ -1139,7 +1141,8 @@ void phy_state_machine(struct work_struc
case PHY_HALTED:
if (phydev->link) {
phydev->link = 0;
- netif_carrier_off(phydev->attached_dev);
+ if (!phydev->no_auto_carrier_off)
+ netif_carrier_off(phydev->attached_dev);
phydev->adjust_link(phydev->attached_dev);
do_suspend = true;
}
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -373,6 +373,7 @@ struct phy_device {
bool is_pseudo_fixed_link;
bool has_fixups;
bool suspended;
+ bool no_auto_carrier_off;
enum phy_state state;

23
target/linux/mediatek/patches-4.9/0001-arch-arm-add-dts-build-code.patch Normal file
View File

@@ -0,0 +1,23 @@
From 9fdcf63545855f3a6f82dee109510f4735e861c8 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 15:54:13 +0200
Subject: [PATCH 01/57] arch: arm: add dts build code
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/arm/boot/dts/Makefile | 3 +++
1 file changed, 3 insertions(+)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -950,6 +950,10 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt6589-aquaris5.dtb \
mt6592-evb.dtb \
mt7623-evb.dtb \
+ mt7623-eMMC.dtb \
+ mt7623-NAND.dtb \
+ mt7623-NAND-ePHY.dtb \
+ mt7623n-bananapi-bpi-r2.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb

6
target/linux/mediatek/patches-4.9/0024-dt-bindings-add-MediaTek-PCIe-binding-documentation.patch → target/linux/mediatek/patches-4.9/0002-dt-bindings-add-MediaTek-PCIe-binding-documentation.patch
View File

@@ -1,11 +1,11 @@
From 05be818061b9f2a0fa5ad0cde6881917ff14a2f2 Mon Sep 17 00:00:00 2001
From ad2d4df46d8ef6a7aab20f0b668fa7db5257cbea Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 6 Jan 2016 21:55:10 +0100
Subject: [PATCH 024/102] dt-bindings: add MediaTek PCIe binding documentation
Subject: [PATCH 02/57] dt-bindings: add MediaTek PCIe binding documentation
Signed-off-by: John Crispin <blogic@openwrt.org>
---
.../devicetree/bindings/pci/mediatek-pcie.txt | 140 ++++++++++++++++++++
.../devicetree/bindings/pci/mediatek-pcie.txt | 140 +++++++++++++++++++++
1 file changed, 140 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt

8
target/linux/mediatek/patches-4.9/0025-PCI-mediatek-add-support-for-PCIe-found-on-MT7623-MT.patch → target/linux/mediatek/patches-4.9/0003-PCI-mediatek-add-support-for-PCIe-found-on-MT7623-MT.patch
View File

@@ -1,7 +1,7 @@
From 8ab1d4e0a9a68e03f472dee1c036a01d0198c20c Mon Sep 17 00:00:00 2001
From 950bd9b0691dd10209c333086a6bdda0108ed3a8 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 5 Jan 2016 20:20:04 +0100
Subject: [PATCH 025/102] PCI: mediatek: add support for PCIe found on
Subject: [PATCH 03/57] PCI: mediatek: add support for PCIe found on
MT7623/MT2701
Add PCIe controller support on MediaTek MT2701/MT7623. The driver supports
@@ -13,13 +13,13 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
arch/arm/mach-mediatek/Kconfig | 1 +
drivers/pci/host/Kconfig | 11 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-mediatek.c | 641 ++++++++++++++++++++++++++++++++++++++
drivers/pci/host/pcie-mediatek.c | 641 +++++++++++++++++++++++++++++++++++++++
4 files changed, 654 insertions(+)
create mode 100644 drivers/pci/host/pcie-mediatek.c
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -29,6 +29,7 @@ config MACH_MT6592
@@ -25,6 +25,7 @@ config MACH_MT6592
config MACH_MT7623
bool "MediaTek MT7623 SoCs support"
default ARCH_MEDIATEK

10
target/linux/mediatek/patches-4.9/00013-soc-mediatek-Add-MT2701-power-dt-bindings.patch → target/linux/mediatek/patches-4.9/0004-soc-mediatek-Add-MT2701-power-dt-bindings.patch
View File

@@ -1,7 +1,7 @@
From 3e96c653372d8852c45dcd3bd856975157a0fd6a Mon Sep 17 00:00:00 2001
From 2f47c01fe3015f4c649849ddffe04f12a122abe2 Mon Sep 17 00:00:00 2001
From: Shunli Wang <shunli.wang@mediatek.com>
Date: Thu, 20 Oct 2016 16:56:37 +0800
Subject: [PATCH] soc: mediatek: Add MT2701 power dt-bindings
Subject: [PATCH 04/57] soc: mediatek: Add MT2701 power dt-bindings
Add power dt-bindings for MT2701.
@@ -11,9 +11,9 @@ Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
.../devicetree/bindings/soc/mediatek/scpsys.txt | 13 +++++++----
include/dt-bindings/power/mt2701-power.h | 27 ++++++++++++++++++++++
2 files changed, 35 insertions(+), 5 deletions(-)
.../devicetree/bindings/soc/mediatek/scpsys.txt | 13 ++++++-----
include/dt-bindings/power/mt2701-power.h | 26 ++++++++++++++++++++++
2 files changed, 34 insertions(+), 5 deletions(-)
create mode 100644 include/dt-bindings/power/mt2701-power.h
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt

4
target/linux/mediatek/patches-4.9/0009-clk-mediatek-Add-MT2701-clock-support.patch → target/linux/mediatek/patches-4.9/0005-clk-mediatek-Add-MT2701-clock-support.patch
View File

@@ -1,7 +1,7 @@
From a4c507d052390b42d7e8c59241e3c336796f730f Mon Sep 17 00:00:00 2001
From f76b34c799d87ab241432b1241f6fc6d9db3ecb6 Mon Sep 17 00:00:00 2001
From: Shunli Wang <shunli.wang@mediatek.com>
Date: Tue, 5 Jan 2016 14:30:20 +0800
Subject: [PATCH 009/102] clk: mediatek: Add MT2701 clock support
Subject: [PATCH 05/57] clk: mediatek: Add MT2701 clock support
Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.

4
target/linux/mediatek/patches-4.9/0011-reset-mediatek-mt2701-reset-driver.patch → target/linux/mediatek/patches-4.9/0006-reset-mediatek-mt2701-reset-driver.patch
View File

@@ -1,7 +1,7 @@
From 3ba0020ea70ffb5503eff1823be7fa5ceda38286 Mon Sep 17 00:00:00 2001
From 596c3a7300c0419dba71d58cbd4136e0d1e12a4e Mon Sep 17 00:00:00 2001
From: Shunli Wang <shunli.wang@mediatek.com>
Date: Tue, 5 Jan 2016 14:30:22 +0800
Subject: [PATCH 011/102] reset: mediatek: mt2701 reset driver
Subject: [PATCH 06/57] reset: mediatek: mt2701 reset driver
In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are

6
target/linux/mediatek/patches-4.9/0012-ARM-mediatek-Add-MT2701-config-options-for-mediatek-.patch → target/linux/mediatek/patches-4.9/0007-ARM-mediatek-Add-MT2701-config-options-for-mediatek-.patch
View File

@@ -1,8 +1,8 @@
From 32fa899c6ab79953e4f470fb23c38bcc40edc5c8 Mon Sep 17 00:00:00 2001
From 60c14df3cc898b6b03d66ec725f9705bf431b677 Mon Sep 17 00:00:00 2001
From: Erin Lo <erin.lo@mediatek.com>
Date: Mon, 28 Dec 2015 15:09:02 +0800
Subject: [PATCH 012/102] ARM: mediatek: Add MT2701 config options for
mediatek SoCs.
Subject: [PATCH 07/57] ARM: mediatek: Add MT2701 config options for mediatek
SoCs.
The upcoming MTK pinctrl driver have a big pin table for each SoC
and we don't want to bloat the kernel binary if we don't need it.

5
target/linux/mediatek/patches-4.9/0014-soc-mediatek-Refine-scpsys-to-support-multiple-platf.patch → target/linux/mediatek/patches-4.9/0008-soc-mediatek-Refine-scpsys-to-support-multiple-platf.patch
View File

@@ -1,7 +1,8 @@
From 6078c651947a148c1de543b54fe55af43a63043a Mon Sep 17 00:00:00 2001
From b5a1e520d8039c242b2157b511f684ce464d6e21 Mon Sep 17 00:00:00 2001
From: James Liao <jamesjj.liao@mediatek.com>
Date: Thu, 20 Oct 2016 16:56:35 +0800
Subject: [PATCH 1/2] soc: mediatek: Refine scpsys to support multiple platform
Subject: [PATCH 08/57] soc: mediatek: Refine scpsys to support multiple
platform
Refine scpsys driver common code to support multiple SoC / platform.

8
target/linux/mediatek/patches-4.9/0015-soc-mediatek-Add-MT2701-scpsys-driver.patch → target/linux/mediatek/patches-4.9/0009-soc-mediatek-Add-MT2701-scpsys-driver.patch
View File

@@ -1,7 +1,7 @@
From 112ef1882e12094c823937f9d72f2f598db02df7 Mon Sep 17 00:00:00 2001
From fb9f97e047f5a831a54cd61529b8cfdc4d413bb6 Mon Sep 17 00:00:00 2001
From: Shunli Wang <shunli.wang@mediatek.com>
Date: Thu, 20 Oct 2016 16:56:38 +0800
Subject: [PATCH 2/2] soc: mediatek: Add MT2701 scpsys driver
Subject: [PATCH 09/57] soc: mediatek: Add MT2701 scpsys driver
Add scpsys driver for MT2701.
@@ -14,8 +14,8 @@ Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
---
drivers/soc/mediatek/Kconfig | 2 +-
drivers/soc/mediatek/mtk-scpsys.c | 117 +++++++++++++++++++++++++++++++++++++-
2 files changed, 117 insertions(+), 2 deletions(-)
drivers/soc/mediatek/mtk-scpsys.c | 108 +++++++++++++++++++++++++++++++++++++-
2 files changed, 108 insertions(+), 2 deletions(-)
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig

7
target/linux/mediatek/patches-4.9/0017-clk-add-hifsys-reset.patch → target/linux/mediatek/patches-4.9/0010-clk-add-hifsys-reset.patch
View File

@@ -1,7 +1,7 @@
From f7121d2b19ddad33a09408a2c5923bfd95da8533 Mon Sep 17 00:00:00 2001
From 600e2bd5c3019f31e90ec876f4efb6c209cf0d73 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 6 Jan 2016 20:06:49 +0100
Subject: [PATCH 017/102] clk: add hifsys reset
Subject: [PATCH 10/57] clk: add hifsys reset
Hi,
@@ -15,8 +15,7 @@ thanks,
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/clk/mediatek/clk-mt2701.c | 2 ++
include/dt-bindings/reset-controller/mt2701-resets.h | 9 +++++++++
2 files changed, 11 insertions(+)
1 file changed, 2 insertions(+)
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c

8
target/linux/mediatek/patches-4.9/0026-scpsys-various-fixes.patch → target/linux/mediatek/patches-4.9/0011-scpsys-various-fixes.patch
View File

@@ -1,13 +1,11 @@
From 59aafd667d2880c90776931b6102b8252214d93c Mon Sep 17 00:00:00 2001
From 1e889b3d38ab5fb425762da57313b4cc8fc2f165 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 21 Feb 2016 13:52:12 +0100
Subject: [PATCH 026/102] scpsys: various fixes
Subject: [PATCH 11/57] scpsys: various fixes
---
drivers/clk/mediatek/clk-mt2701.c | 2 ++
drivers/soc/mediatek/mtk-scpsys-mt2701.c | 8 --------
include/dt-bindings/power/mt2701-power.h | 4 ++--
3 files changed, 4 insertions(+), 10 deletions(-)
1 file changed, 2 insertions(+)
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c

4
target/linux/mediatek/patches-4.9/0052-clk-dont-disable-unused-clocks.patch → target/linux/mediatek/patches-4.9/0012-clk-dont-disable-unused-clocks.patch
View File

@@ -1,7 +1,7 @@
From 5238c5d1d38661955ed3b52f45c46e00bfc9eb6e Mon Sep 17 00:00:00 2001
From 0e60d2112968ccb2570535bf19fb5020c9b28c08 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 7 Apr 2016 07:18:35 +0200
Subject: [PATCH 052/102] clk: dont disable unused clocks
Subject: [PATCH 12/57] clk: dont disable unused clocks
Signed-off-by: John Crispin <blogic@openwrt.org>
---

4
target/linux/mediatek/patches-4.9/0053-clk-mediatek-enable-critical-clocks.patch → target/linux/mediatek/patches-4.9/0013-clk-mediatek-enable-critical-clocks.patch
View File

@@ -1,7 +1,7 @@
From c8fd103d6c07af5db47f061b70759b7c69169656 Mon Sep 17 00:00:00 2001
From 03bead9276653dc842f6970250bc7eba41faf777 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 31 Mar 2016 06:46:51 +0200
Subject: [PATCH 053/102] clk: mediatek: enable critical clocks
Subject: [PATCH 13/57] clk: mediatek: enable critical clocks
Signed-off-by: John Crispin <blogic@openwrt.org>
---

10
target/linux/mediatek/patches-4.9/0054-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch → target/linux/mediatek/patches-4.9/0014-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch
View File

@@ -1,8 +1,8 @@
From 1387d4f0ebf4b48c09f2ea0d27a02936c3fa0010 Mon Sep 17 00:00:00 2001
From 3a947321d72af191ee87a390295c661c876cc6f4 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 31 Mar 2016 02:26:37 +0200
Subject: [PATCH 054/102] clk: mediatek: Export CPU mux clocks for CPU
frequency control
Subject: [PATCH 14/57] clk: mediatek: Export CPU mux clocks for CPU frequency
control
This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
for intermediate clock source switching.
@@ -10,9 +10,9 @@ for intermediate clock source switching.
Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-cpumux.c | 127 ++++++++++++++++++++++++++++++++
drivers/clk/mediatek/clk-cpumux.c | 127 +++++++++++++++++++++++++++++++++
drivers/clk/mediatek/clk-cpumux.h | 22 ++++++
drivers/clk/mediatek/clk-mt2701.c | 8 ++
drivers/clk/mediatek/clk-mt2701.c | 8 +++
drivers/clk/mediatek/clk-mt8173.c | 23 ++++++
include/dt-bindings/clock/mt2701-clk.h | 3 +-
include/dt-bindings/clock/mt8173-clk.h | 4 +-

6
target/linux/mediatek/patches-4.9/0055-cpufreq-mediatek-add-driver.patch → target/linux/mediatek/patches-4.9/0015-cpufreq-mediatek-add-driver.patch
View File

@@ -1,13 +1,13 @@
From 60f4e41b367bdb29530468c91c1e613b17a37755 Mon Sep 17 00:00:00 2001
From 8aa2c6c4d8b20c0e9c69b15db4a0039d33f8b365 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 30 Mar 2016 23:48:53 +0200
Subject: [PATCH 055/102] cpufreq: mediatek: add driver
Subject: [PATCH 15/57] cpufreq: mediatek: add driver
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/cpufreq/Kconfig.arm | 9 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/mt7623-cpufreq.c | 389 ++++++++++++++++++++++++++++++++++++++
drivers/cpufreq/mt7623-cpufreq.c | 389 +++++++++++++++++++++++++++++++++++++++
3 files changed, 399 insertions(+)
create mode 100644 drivers/cpufreq/mt7623-cpufreq.c

10
target/linux/mediatek/patches-4.9/0071-pwm-add-pwm-mediatek.patch → target/linux/mediatek/patches-4.9/0016-pwm-add-pwm-mediatek.patch
View File

@@ -1,16 +1,14 @@
From 6f5941c93bdf7649f392f1263b9068d360ceab4d Mon Sep 17 00:00:00 2001
From 201be68268eddb1568c41780a62868cc1666a2de Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Fri, 6 May 2016 02:55:48 +0200
Subject: [PATCH 071/102] pwm: add pwm-mediatek
Subject: [PATCH 16/57] pwm: add pwm-mediatek
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/arm/boot/dts/mt7623-evb.dts | 17 +++
arch/arm/boot/dts/mt7623.dtsi | 22 ++++
drivers/pwm/Kconfig | 9 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-mediatek.c | 230 ++++++++++++++++++++++++++++++++++++++
5 files changed, 279 insertions(+)
drivers/pwm/pwm-mediatek.c | 230 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 240 insertions(+)
create mode 100644 drivers/pwm/pwm-mediatek.c
--- a/drivers/pwm/Kconfig

27
target/linux/mediatek/patches-4.9/0017-mfd-mt6397-Add-MT6323-LED-support-into-MT6397-driver.patch Normal file
View File

@@ -0,0 +1,27 @@
From 2b866d69f6198701457d29c5886c0ad7865c785f Mon Sep 17 00:00:00 2001
From: Sean Wang <sean.wang@mediatek.com>
Date: Sat, 25 Feb 2017 02:47:21 +0800
Subject: [PATCH 17/57] mfd: mt6397: Add MT6323 LED support into MT6397 driver
Add compatible string as "mt6323-led" that will make
the OF core spawn child devices for the LED subnode
of that MT6323 MFD device.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
drivers/mfd/mt6397-core.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -48,6 +48,10 @@ static const struct mfd_cell mt6323_devs
.name = "mt6323-regulator",
.of_compatible = "mediatek,mt6323-regulator"
},
+ {
+ .name = "mt6323-led",
+ .of_compatible = "mediatek,mt6323-led"
+ },
};
static const struct mfd_cell mt6397_devs[] = {

21
target/linux/mediatek/patches-4.9/0085-pmic-led0.patch → target/linux/mediatek/patches-4.9/0018-dt-bindings-leds-Add-document-bindings-for-leds-mt63.patch
View File

@@ -1,21 +1,8 @@
From patchwork Mon Mar 20 06:47:24 2017
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v6,1/4] dt-bindings: leds: Add document bindings for leds-mt6323
From: sean.wang@mediatek.com
X-Patchwork-Id: 9633073
Message-Id: <1489992447-13007-2-git-send-email-sean.wang@mediatek.com>
To: <rpurdie@rpsys.net>, <jacek.anaszewski@gmail.com>, <lee.jones@linaro.org>,
<matthias.bgg@gmail.com>, <pavel@ucw.cz>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, keyhaede@gmail.com,
Sean Wang <sean.wang@mediatek.com>, linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org, linux-leds@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Date: Mon, 20 Mar 2017 14:47:24 +0800
From 424ca23e68b043ce26d6981839ca825ef8637aba Mon Sep 17 00:00:00 2001
From: Sean Wang <sean.wang@mediatek.com>
Date: Mon, 20 Mar 2017 14:47:24 +0800
Subject: [PATCH 18/57] dt-bindings: leds: Add document bindings for
leds-mt6323
This patch adds documentation for devicetree bindings for LED support on
MT6323 PMIC.

24
target/linux/mediatek/patches-4.9/0019-dt-bindings-mfd-Add-the-description-for-LED-as-the-s.patch Normal file
View File

@@ -0,0 +1,24 @@
From 7c137e4b83f32a67ccf6b39fa455aca71980a21f Mon Sep 17 00:00:00 2001
From: Sean Wang <sean.wang@mediatek.com>
Date: Mon, 20 Mar 2017 14:47:25 +0800
Subject: [PATCH 19/57] dt-bindings: mfd: Add the description for LED as the
sub module
This patch adds description for LED as the sub-module on MT6397/MT6323
multifunction device.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
Documentation/devicetree/bindings/mfd/mt6397.txt | 1 +
1 file changed, 1 insertion(+)
--- a/Documentation/devicetree/bindings/mfd/mt6397.txt
+++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
@@ -6,6 +6,7 @@ MT6397/MT6323 is a multifunction device
- Audio codec
- GPIO
- Clock
+- LED
It is interfaced to host controller using SPI interface by a proprietary hardware
called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap.

23
target/linux/mediatek/patches-4.9/0087-pmic-led2.patch → target/linux/mediatek/patches-4.9/0020-leds-Add-LED-support-for-MT6323-PMIC.patch
View File

@@ -1,21 +1,7 @@
From patchwork Mon Mar 20 06:47:26 2017
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v6,3/4] leds: Add LED support for MT6323 PMIC
From: sean.wang@mediatek.com
X-Patchwork-Id: 9633081
Message-Id: <1489992447-13007-4-git-send-email-sean.wang@mediatek.com>
To: <rpurdie@rpsys.net>, <jacek.anaszewski@gmail.com>, <lee.jones@linaro.org>,
<matthias.bgg@gmail.com>, <pavel@ucw.cz>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, keyhaede@gmail.com,
Sean Wang <sean.wang@mediatek.com>, linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org, linux-leds@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Date: Mon, 20 Mar 2017 14:47:26 +0800
From e482f9590f2e831c68bcf85e3f9f4c88bbd3329f Mon Sep 17 00:00:00 2001
From: Sean Wang <sean.wang@mediatek.com>
Date: Mon, 20 Mar 2017 14:47:26 +0800
Subject: [PATCH 20/57] leds: Add LED support for MT6323 PMIC
MT6323 PMIC is a multi-function device that includes LED function.
It allows attaching up to 4 LEDs which can either be on, off or dimmed
@@ -25,9 +11,8 @@ Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Jacek Anaszewski <jacek.anaszewski@gmail.com>
---
drivers/leds/Kconfig | 8 +
drivers/leds/Makefile | 1 +
drivers/leds/leds-mt6323.c | 502 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 511 insertions(+)
2 files changed, 510 insertions(+)
create mode 100644 drivers/leds/leds-mt6323.c
--- a/drivers/leds/Kconfig

27
target/linux/mediatek/patches-4.9/0021-mfd-mt6397-Align-the-placement-at-which-the-mfd_cell.patch Normal file
View File

@@ -0,0 +1,27 @@
From 6e81b4fee93c004078465589128ba07b6855be02 Mon Sep 17 00:00:00 2001
From: Sean Wang <sean.wang@mediatek.com>
Date: Mon, 20 Mar 2017 14:47:27 +0800
Subject: [PATCH 21/57] mfd: mt6397: Align the placement at which the mfd_cell
of LED is defined
Align the placement as which the mfd_cell of LED is defined as the other
members done on the structure.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mfd/mt6397-core.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -47,8 +47,7 @@ static const struct mfd_cell mt6323_devs
{
.name = "mt6323-regulator",
.of_compatible = "mediatek,mt6323-regulator"
- },
- {
+ }, {
.name = "mt6323-led",
.of_compatible = "mediatek,mt6323-led"
},

10
target/linux/mediatek/patches-4.9/0103-nand_fixes.patch → target/linux/mediatek/patches-4.9/0022-nand-make-bootrom-work-with-upstream-driver.patch
View File

@@ -1,3 +1,13 @@
From 453ebd5d6b535388972fcea747025ced3afca5cc Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 14:47:06 +0200
Subject: [PATCH 22/57] nand: make bootrom work with upstream driver
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/mtd/nand/mtk_nand.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/drivers/mtd/nand/mtk_nand.c
+++ b/drivers/mtd/nand/mtk_nand.c
@@ -1073,8 +1073,8 @@ static int mtk_nfc_ooblayout_free(struct

81
target/linux/mediatek/patches-4.9/0023-rng-add-mediatek-hw-rng.patch Normal file
View File

@@ -0,0 +1,81 @@
From 4ad0accdfb0941de1440906461c08bee715378d5 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 15:57:44 +0200
Subject: [PATCH 23/57] rng: add mediatek hw rng
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/char/hw_random/Kconfig | 14 ++++++++++++++
drivers/char/hw_random/Makefile | 1 +
drivers/crypto/Kconfig | 18 ++++++++++++++++++
drivers/crypto/Makefile | 1 +
4 files changed, 34 insertions(+)
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -166,6 +166,20 @@ config HW_RANDOM_IXP4XX
If unsure, say Y.
+config HW_RANDOM_MTK
+ tristate "Mediatek Random Number Generator support"
+ depends on HW_RANDOM
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ default y
+ ---help---
+ This driver provides kernel-side support for the Random Number
+ Generator hardware found on Mediatek SoCs.
+
+ To compile this driver as a module, choose M here. the
+ module will be called mtk-rng.
+
+ If unsure, say Y.
+
config HW_RANDOM_OMAP
tristate "OMAP Random Number Generator support"
depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -35,4 +35,5 @@ obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-r
obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
+obj-$(CONFIG_HW_RANDOM_MTK) += mtk-rng.o
obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -553,6 +553,24 @@ config CRYPTO_DEV_ROCKCHIP
This driver interfaces with the hardware crypto accelerator.
Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
+config CRYPTO_DEV_MEDIATEK
+ tristate "MediaTek's EIP97 Cryptographic Engine driver"
+ depends on HAS_DMA
+ depends on (ARM && ARCH_MEDIATEK) || COMPILE_TEST
+ select CRYPTO_AES
+ select CRYPTO_AEAD
+ select CRYPTO_BLKCIPHER
+ select CRYPTO_CTR
+ select CRYPTO_SHA1
+ select CRYPTO_SHA256
+ select CRYPTO_SHA512
+ select CRYPTO_HMAC
+ help
+ This driver allows you to utilize the hardware crypto accelerator
+ EIP97 which can be found on the MT7623 MT2701, MT8521p, etc ....
+ Select this if you want to use it for AES/SHA1/SHA2 algorithms.
+
+
source "drivers/crypto/chelsio/Kconfig"
endif # CRYPTO_HW
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CRYPTO_DEV_IMGTEC_HASH) +=
obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
obj-$(CONFIG_CRYPTO_DEV_MV_CESA) += mv_cesa.o
obj-$(CONFIG_CRYPTO_DEV_MARVELL_CESA) += marvell/
+obj-$(CONFIG_CRYPTO_DEV_MEDIATEK) += mediatek/
obj-$(CONFIG_CRYPTO_DEV_MXS_DCP) += mxs-dcp.o
obj-$(CONFIG_CRYPTO_DEV_NIAGARA2) += n2_crypto.o
n2_crypto-y := n2_core.o n2_asm.o

1034
target/linux/mediatek/patches-4.9/0024-media-rc-add-driver-for-IR-remote-receiver-on-MT7623.patch Normal file
View File

File diff suppressed because it is too large Load Diff

20
target/linux/mediatek/patches-4.9/0091-dsa1.patch → target/linux/mediatek/patches-4.9/0025-dt-bindings-net-dsa-add-Mediatek-MT7530-binding.patch
View File

@@ -1,21 +1,7 @@
From patchwork Wed Mar 29 09:38:19 2017
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [net-next,v3,1/5] dt-bindings: net: dsa: add Mediatek MT7530 binding
From: sean.wang@mediatek.com
X-Patchwork-Id: 9651093
Message-Id: <1490780303-18598-2-git-send-email-sean.wang@mediatek.com>
To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, Landen.Chao@mediatek.com, keyhaede@gmail.com,
netdev@vger.kernel.org, sean.wang@mediatek.com,
linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org, objelf@gmail.com, davem@davemloft.net
Date: Wed, 29 Mar 2017 17:38:19 +0800
From 3b9b46b5705214b16c5356284ad68be32ae56a26 Mon Sep 17 00:00:00 2001
From: Sean Wang <sean.wang@mediatek.com>
Date: Wed, 29 Mar 2017 17:38:19 +0800
Subject: [PATCH 25/57] dt-bindings: net: dsa: add Mediatek MT7530 binding
Add device-tree binding for Mediatek MT7530 switch.

1788
target/linux/mediatek/patches-4.9/0026-net-mediatek-backport-v4.10-driver.patch Normal file
View File

File diff suppressed because it is too large Load Diff

18
target/linux/mediatek/patches-4.9/0091-net-next-mediatek-fix-DQL-support.patch → target/linux/mediatek/patches-4.9/0027-net-next-mediatek-fix-DQL-support.patch
View File

@@ -1,7 +1,7 @@
From 81cdbda2a08375b9d5915567d2210bf2433e7332 Mon Sep 17 00:00:00 2001
From f974e397b806f7b16d11cc1542538616291924f1 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Sat, 23 Apr 2016 11:57:21 +0200
Subject: [PATCH 081/102] net-next: mediatek: fix DQL support
Subject: [PATCH 27/57] net-next: mediatek: fix DQL support
The MTK ethernet core has 2 MACs both sitting on the same DMA ring. The
current code will assign the TX traffic of each MAC to its own DQL. This
@@ -13,12 +13,12 @@ using the DMA.
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 33 ++++++++++++++++-----------
1 file changed, 20 insertions(+), 13 deletions(-)
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 +++++++++++++++++------------
1 file changed, 21 insertions(+), 14 deletions(-)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -706,7 +706,16 @@ static int mtk_tx_map(struct sk_buff *sk
@@ -710,7 +710,16 @@ static int mtk_tx_map(struct sk_buff *sk
WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
(!nr_frags * TX_DMA_LS0)));
@@ -36,7 +36,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
skb_tx_timestamp(skb);
ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
@@ -998,21 +1007,18 @@ static int mtk_poll_tx(struct mtk_eth *e
@@ -1002,21 +1011,18 @@ static int mtk_poll_tx(struct mtk_eth *e
struct mtk_tx_dma *desc;
struct sk_buff *skb;
struct mtk_tx_buf *tx_buf;
@@ -60,9 +60,9 @@ Signed-off-by: John Crispin <john@phrozen.org>
- while ((cpu != dma) && budget) {
+ while ((cpu != dma) && done < budget) {
u32 next_cpu = desc->txd2;
int mac;
int mac = 0;
@@ -1032,9 +1038,8 @@ static int mtk_poll_tx(struct mtk_eth *e
@@ -1035,9 +1041,8 @@ static int mtk_poll_tx(struct mtk_eth *e
}
if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
@@ -74,7 +74,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
}
mtk_tx_unmap(eth, tx_buf);
@@ -1046,11 +1051,13 @@ static int mtk_poll_tx(struct mtk_eth *e
@@ -1049,11 +1054,13 @@ static int mtk_poll_tx(struct mtk_eth *e
mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);

20
target/linux/mediatek/patches-4.9/0092-dsa2.patch → target/linux/mediatek/patches-4.9/0028-net-next-dsa-add-Mediatek-tag-RX-TX-handler.patch
View File

@@ -1,21 +1,7 @@
From patchwork Wed Mar 29 09:38:20 2017
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [net-next,v3,2/5] net-next: dsa: add Mediatek tag RX/TX handler
From: sean.wang@mediatek.com
X-Patchwork-Id: 9651099
Message-Id: <1490780303-18598-3-git-send-email-sean.wang@mediatek.com>
To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, Landen.Chao@mediatek.com, keyhaede@gmail.com,
netdev@vger.kernel.org, sean.wang@mediatek.com,
linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org, objelf@gmail.com, davem@davemloft.net
Date: Wed, 29 Mar 2017 17:38:20 +0800
From 5c01c03920c63630864d2b8641924a8c7c6cb62f Mon Sep 17 00:00:00 2001
From: Sean Wang <sean.wang@mediatek.com>
Date: Wed, 29 Mar 2017 17:38:20 +0800
Subject: [PATCH 28/57] net-next: dsa: add Mediatek tag RX/TX handler
Add the support for the 4-bytes tag for DSA port distinguishing inserted
allowing receiving and transmitting the packet via the particular port.

35
target/linux/mediatek/patches-4.9/0092-dsa3.patch → target/linux/mediatek/patches-4.9/0029-net-next-ethernet-mediatek-add-CDM-able-to-recognize.patch
View File

@@ -1,23 +1,8 @@
From patchwork Wed Mar 29 09:38:21 2017
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [net-next, v3,
3/5] net-next: ethernet: mediatek: add CDM able to recognize the tag
for DSA
From: sean.wang@mediatek.com
X-Patchwork-Id: 9651091
Message-Id: <1490780303-18598-4-git-send-email-sean.wang@mediatek.com>
To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, Landen.Chao@mediatek.com, keyhaede@gmail.com,
netdev@vger.kernel.org, sean.wang@mediatek.com,
linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org, objelf@gmail.com, davem@davemloft.net
Date: Wed, 29 Mar 2017 17:38:21 +0800
From de3c04b820e1d396bf12e88ea87271a84f6fedb7 Mon Sep 17 00:00:00 2001
From: Sean Wang <sean.wang@mediatek.com>
Date: Wed, 29 Mar 2017 17:38:21 +0800
Subject: [PATCH 29/57] net-next: ethernet: mediatek: add CDM able to recognize
the tag for DSA
The patch adds the setup for allowing CDM can recognize these packets with
carrying port-distinguishing tag. Otherwise, these tagging packets will be
@@ -35,9 +20,9 @@ Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1855,6 +1855,12 @@ static int mtk_hw_init(struct mtk_eth *e
/* GE2, Force 1000M/FD, FC ON */
mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
@@ -1864,6 +1864,12 @@ static int mtk_hw_init(struct mtk_eth *e
val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
+ /* Indicates CDM to parse the MTK special tag from CPU
+ * which also is working out for untag packets.
@@ -50,9 +35,9 @@ Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -70,6 +70,10 @@
/* Frame Engine Interrupt Grouping Register */
#define MTK_FE_INT_GRP 0x20
@@ -74,6 +74,10 @@
#define MTK_CDMQ_IG_CTRL 0x1400
#define MTK_CDMQ_STAG_EN BIT(0)
+/* CDMP Ingress Control Register */
+#define MTK_CDMQ_IG_CTRL 0x1400

22
target/linux/mediatek/patches-4.9/0092-dsa5.patch → target/linux/mediatek/patches-4.9/0030-net-next-dsa-add-dsa-support-for-Mediatek-MT7530-swi.patch
View File

@@ -1,22 +1,8 @@
From patchwork Wed Mar 29 09:38:23 2017
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [net-next, v3,
5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch
From: sean.wang@mediatek.com
X-Patchwork-Id: 9651095
Message-Id: <1490780303-18598-6-git-send-email-sean.wang@mediatek.com>
To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, Landen.Chao@mediatek.com, keyhaede@gmail.com,
netdev@vger.kernel.org, sean.wang@mediatek.com,
linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org, objelf@gmail.com, davem@davemloft.net
Date: Wed, 29 Mar 2017 17:38:23 +0800
From 6a0a62dec3c582db4260f411294770448efc3d6c Mon Sep 17 00:00:00 2001
From: Sean Wang <sean.wang@mediatek.com>
Date: Wed, 29 Mar 2017 17:38:23 +0800
Subject: [PATCH 30/57] net-next: dsa: add dsa support for Mediatek MT7530
switch
MT7530 is a 7-ports Gigabit Ethernet Switch that could be found on
Mediatek router platforms such as MT7623A or MT7623N platform which

14
target/linux/mediatek/patches-4.9/0093-dsa-compat.patch → target/linux/mediatek/patches-4.9/0031-net-dsa-dsa-api-compat.patch
View File

@@ -1,3 +1,17 @@
From a319687ac18dcc557a88054282508e061ad8495f Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 14:42:19 +0200
Subject: [PATCH 31/57] net: dsa: dsa api compat
make the latest driver work on the old API
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/dsa/mt7530.c | 14 ++++++++------
drivers/net/dsa/mt7530.h | 2 ++
net/dsa/tag_mtk.c | 2 +-
3 files changed, 11 insertions(+), 7 deletions(-)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -834,6 +834,7 @@ mt7530_port_bridge_join(struct dsa_switc

12
target/linux/mediatek/patches-4.9/0095-ephy.patch → target/linux/mediatek/patches-4.9/0032-net-dsa-mediatek-add-support-for-GMAC2-wired-to-ext-.patch
View File

@@ -1,3 +1,15 @@
From 52e9ce30a2b3c414e0efb20632fefa7cfc5096e6 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 14:44:18 +0200
Subject: [PATCH 32/57] net: dsa: mediatek: add support for GMAC2 wired to ext
phy
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/dsa/mt7530.c | 5 +++++
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 3 +++
2 files changed, 8 insertions(+)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -629,6 +629,11 @@ mt7530_setup(struct dsa_switch *ds)

14
target/linux/mediatek/patches-4.9/0096-dsa-multi-cpu.patch → target/linux/mediatek/patches-4.9/0033-net-dsa-add-multi-gmac-support.patch
View File

@@ -1,3 +1,17 @@
From cce5dd6034ed1651ee25c910edee708e6b84a44a Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 14:45:08 +0200
Subject: [PATCH 33/57] net: dsa: add multi gmac support
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/dsa/mt7530.c | 10 +---------
include/net/dsa.h | 21 ++++++++++++++++++++-
net/dsa/dsa2.c | 40 +++++++++++++++++++++++++++++++++-------
net/dsa/dsa_priv.h | 1 +
net/dsa/slave.c | 26 ++++++++++++++++----------
5 files changed, 71 insertions(+), 27 deletions(-)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -996,15 +996,7 @@ err:

10
target/linux/mediatek/patches-4.9/0097-dsa-mt7530.patch → target/linux/mediatek/patches-4.9/0034-net-dsa-mediatek-add-dual-gmac-support.patch
View File

@@ -1,3 +1,13 @@
From dcb751a52b2ee69c16db2fef8f92a96ab13b6bb4 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 14:45:34 +0200
Subject: [PATCH 34/57] net: dsa: mediatek: add dual gmac support
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/dsa/mt7530.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -627,7 +627,7 @@ mt7530_setup(struct dsa_switch *ds)

47
target/linux/mediatek/patches-4.9/0035-net-mediatek-disable-RX-VLan-offloading.patch Normal file
View File

@@ -0,0 +1,47 @@
From 35b83b85e752a6660b92f08c0fb912308f25cf6d Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 15:56:40 +0200
Subject: [PATCH 35/57] net: mediatek: disable RX VLan offloading
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 9 ++++++---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 --
2 files changed, 6 insertions(+), 5 deletions(-)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -643,8 +643,8 @@ static int mtk_tx_map(struct sk_buff *sk
txd4 |= TX_DMA_CHKSUM;
/* VLAN header offload */
- if (skb_vlan_tag_present(skb))
- txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
+// if (skb_vlan_tag_present(skb))
+// txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
mapped_addr = dma_map_single(eth->dev, skb->data,
skb_headlen(skb), DMA_TO_DEVICE);
@@ -1874,7 +1874,10 @@ static int mtk_hw_init(struct mtk_eth *e
mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
/* Enable RX VLan Offloading */
- mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
+ if (MTK_HW_FEATURES & NETIF_F_HW_VLAN_CTAG_RX)
+ mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
+ else
+ mtk_w32(eth, 0, MTK_CDMP_EG_CTRL);
/* disable delay and normal interrupt */
mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -34,8 +34,6 @@
NETIF_MSG_TX_ERR)
#define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \
NETIF_F_RXCSUM | \
- NETIF_F_HW_VLAN_CTAG_TX | \
- NETIF_F_HW_VLAN_CTAG_RX | \
NETIF_F_SG | NETIF_F_TSO | \
NETIF_F_TSO6 | \
NETIF_F_IPV6_CSUM)

25
target/linux/mediatek/patches-4.9/0036-net-next-mediatek-fix-typos-inside-the-header-file.patch Normal file
View File

@@ -0,0 +1,25 @@
From bf25fbdc7dfb256f267725336e29e232aadd5123 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Fri, 21 Jul 2017 08:43:58 +0200
Subject: [PATCH 36/57] net-next: mediatek: fix typos inside the header file
Trivial patch fixing 2 typos.
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -525,8 +525,8 @@ struct mtk_rx_ring {
* @pctl: The register map pointing at the range used to setup
* GMAC port drive/slew values
* @dma_refcnt: track how many netdevs are using the DMA engine
- * @tx_ring: Pointer to the memore holding info about the TX ring
- * @rx_ring: Pointer to the memore holding info about the RX ring
+ * @tx_ring: Pointer to the memory holding info about the TX ring
+ * @rx_ring: Pointer to the memory holding info about the RX ring
* @tx_napi: The TX NAPI struct
* @rx_napi: The RX NAPI struct
* @scratch_ring: Newer SoCs need memory for a second HW managed TX ring

128
target/linux/mediatek/patches-4.9/0037-net-next-mediatek-bring-up-QDMA-RX-ring-0.patch Normal file
View File

@@ -0,0 +1,128 @@
From 047a4e7b17322c1b32d8db32a0df9899cb4963a3 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Fri, 21 Jul 2017 08:48:38 +0200
Subject: [PATCH 37/57] net-next: mediatek: bring up QDMA RX ring 0
This patch is in peparation for adding HW flow and QoS offloading. For
those features to work, the driver needs to bring up the first QDMA RX
ring. This ring is used by the PPE offloading HW.
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 38 ++++++++++++++++++++---------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 +++
2 files changed, 30 insertions(+), 11 deletions(-)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1224,11 +1224,21 @@ static void mtk_tx_clean(struct mtk_eth
static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
{
- struct mtk_rx_ring *ring = &eth->rx_ring[ring_no];
+ struct mtk_rx_ring *ring;
int rx_data_len, rx_dma_size;
int i;
+ u32 offset = 0;
- if (rx_flag == MTK_RX_FLAGS_HWLRO) {
+ if (rx_flag & MTK_RX_FLAGS_QDMA) {
+ if (ring_no)
+ return -EINVAL;
+ ring = &eth->rx_ring_qdma;
+ offset = 0x1000;
+ } else {
+ ring = &eth->rx_ring[ring_no];
+ }
+
+ if (rx_flag & MTK_RX_FLAGS_HWLRO) {
rx_data_len = MTK_MAX_LRO_RX_LENGTH;
rx_dma_size = MTK_HW_LRO_DMA_SIZE;
} else {
@@ -1276,17 +1286,16 @@ static int mtk_rx_alloc(struct mtk_eth *
*/
wmb();
- mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no));
- mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no));
- mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
- mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX);
+ mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
+ mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
+ mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
+ mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
return 0;
}
-static void mtk_rx_clean(struct mtk_eth *eth, int ring_no)
+static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
{
- struct mtk_rx_ring *ring = &eth->rx_ring[ring_no];
int i;
if (ring->data && ring->dma) {
@@ -1612,6 +1621,10 @@ static int mtk_dma_init(struct mtk_eth *
if (err)
return err;
+ err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
+ if (err)
+ return err;
+
err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
if (err)
return err;
@@ -1651,12 +1664,13 @@ static void mtk_dma_free(struct mtk_eth
eth->phy_scratch_ring = 0;
}
mtk_tx_clean(eth);
- mtk_rx_clean(eth, 0);
+ mtk_rx_clean(eth, &eth->rx_ring[0]);
+ mtk_rx_clean(eth, &eth->rx_ring_qdma);
if (eth->hwlro) {
mtk_hwlro_rx_uninit(eth);
for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
- mtk_rx_clean(eth, i);
+ mtk_rx_clean(eth, &eth->rx_ring[i]);
}
kfree(eth->scratch_head);
@@ -1723,7 +1737,9 @@ static int mtk_start_dma(struct mtk_eth
mtk_w32(eth,
MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
- MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO,
+ MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
+ MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
+ MTK_RX_BT_32DWORDS,
MTK_QDMA_GLO_CFG);
mtk_w32(eth,
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -484,6 +484,7 @@ struct mtk_tx_ring {
enum mtk_rx_flags {
MTK_RX_FLAGS_NORMAL = 0,
MTK_RX_FLAGS_HWLRO,
+ MTK_RX_FLAGS_QDMA,
};
/* struct mtk_rx_ring - This struct holds info describing a RX ring
@@ -527,6 +528,7 @@ struct mtk_rx_ring {
* @dma_refcnt: track how many netdevs are using the DMA engine
* @tx_ring: Pointer to the memory holding info about the TX ring
* @rx_ring: Pointer to the memory holding info about the RX ring
+ * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring
* @tx_napi: The TX NAPI struct
* @rx_napi: The RX NAPI struct
* @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
@@ -556,6 +558,7 @@ struct mtk_eth {
atomic_t dma_refcnt;
struct mtk_tx_ring tx_ring;
struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM];
+ struct mtk_rx_ring rx_ring_qdma;
struct napi_struct tx_napi;
struct napi_struct rx_napi;
struct mtk_tx_dma *scratch_ring;

46
target/linux/mediatek/patches-4.9/0038-net-next-dsa-move-struct-dsa_device_ops-to-the-globa.patch Normal file
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@@ -0,0 +1,46 @@
From b58bf0220f666705e63fe8d361f37c913aee2d8f Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Fri, 21 Jul 2017 09:32:54 +0200
Subject: [PATCH 38/57] net-next: dsa: move struct dsa_device_ops to the global
header file
We need to access this struct from within the flow_dissector to fix
dissection for packets coming in on DSA devices.
Signed-off-by: John Crispin <john@phrozen.org>
---
include/net/dsa.h | 7 +++++++
net/dsa/dsa_priv.h | 6 ------
2 files changed, 7 insertions(+), 6 deletions(-)
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -88,6 +88,13 @@ struct dsa_platform_data {
struct packet_type;
+struct dsa_device_ops {
+ struct sk_buff *(*xmit)(struct sk_buff *skb, struct net_device *dev);
+ int sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev,
+ struct packet_type *pt,
+ struct net_device *orig_dev);
+};
+
struct dsa_switch_tree {
struct list_head list;
--- a/net/dsa/dsa_priv.h
+++ b/net/dsa/dsa_priv.h
@@ -15,12 +15,6 @@
#include <linux/netdevice.h>
#include <linux/netpoll.h>
-struct dsa_device_ops {
- struct sk_buff *(*xmit)(struct sk_buff *skb, struct net_device *dev);
- int (*rcv)(struct sk_buff *skb, struct net_device *dev,
- struct packet_type *pt, struct net_device *orig_dev);
-};
-
struct dsa_slave_priv {
struct sk_buff * (*xmit)(struct sk_buff *skb,
struct net_device *dev);

32
target/linux/mediatek/patches-4.9/0039-net-next-dsa-add-flow_dissect-callback-to-struct-dsa.patch Normal file
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@@ -0,0 +1,32 @@
From 22e8b65ea4bf8a1fa757137bdcbdefe505fa4044 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Mon, 7 Aug 2017 16:35:43 +0200
Subject: [PATCH 39/57] net-next: dsa: add flow_dissect callback to struct
dsa_device_ops
When the flow dissector first sees packets coming in on a DSA devices the
802.3 header wont be located where the code expects it to be as the tag
is still present. Adding this new callback allows a DSA device to provide a
new function that the flow_disscetor can use to get the correct offsets
for the protocol field and network header offset.
Signed-off-by: John Crispin <john@phrozen.org>
---
include/net/dsa.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -90,9 +90,11 @@ struct packet_type;
struct dsa_device_ops {
struct sk_buff *(*xmit)(struct sk_buff *skb, struct net_device *dev);
- int sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev,
+ int (*rcv)(struct sk_buff *skb, struct net_device *dev,
struct packet_type *pt,
struct net_device *orig_dev);
+ int (*flow_dissect)(const struct sk_buff *skb, __be16 *proto,
+ int *offset);
};
struct dsa_switch_tree {

39
target/linux/mediatek/patches-4.9/0040-net-next-tag_mtk-add-flow_dissect-callback-to-the-op.patch Normal file
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@@ -0,0 +1,39 @@
From 9d6806e16e5ea68a49225da1ab065ef0b5d7704b Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Mon, 7 Aug 2017 16:55:56 +0200
Subject: [PATCH 40/57] net-next: tag_mtk: add flow_dissect callback to the ops
struct
The MT7530 inserts the 4 magic header in between the 802.3 address and
protocol field. The patch implements the callback that can be called by
the flow dissector to figure out the real protocol and offset of the
network header. With this patch applied we can properly parse the packet
and thus make hashing function properly.
Signed-off-by: John Crispin <john@phrozen.org>
---
net/dsa/tag_mtk.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
--- a/net/dsa/tag_mtk.c
+++ b/net/dsa/tag_mtk.c
@@ -111,7 +111,17 @@ out:
return 0;
}
+static int mtk_tag_flow_dissect(const struct sk_buff *skb, __be16 *proto,
+ int *offset)
+{
+ *offset = 4;
+ *proto = ((__be16 *)skb->data)[1];
+
+ return 0;
+}
+
const struct dsa_device_ops mtk_netdev_ops = {
- .xmit = mtk_tag_xmit,
- .rcv = mtk_tag_rcv,
+ .xmit = mtk_tag_xmit,
+ .rcv = mtk_tag_rcv,
+ .flow_dissect = mtk_tag_flow_dissect,
};

65
target/linux/mediatek/patches-4.9/0041-net-next-dsa-fix-flow-dissection.patch Normal file
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@@ -0,0 +1,65 @@
From 04c825484d6ecdcc8ce09b350235c9077eaca6e3 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Wed, 9 Aug 2017 08:20:21 +0200
Subject: [PATCH 41/57] net-next: dsa: fix flow dissection
RPS and probably other kernel features are currently broken on some if not
all DSA devices. The root cause of this is that skb_hash will call the
flow_dissector. At this point the skb still contains the magic switch
header and the skb->protocol field is not set up to the correct 802.3
value yet. By the time the tag specific code is called, removing the header
and =roperly setting the protocol an invalid hash is already set. In the
case of the mt7530 this will result in all flows always having the same
hash.
This patch makes the flow dissector honour the nh and protocol offset
defined by the dsa tag driver thus fixing dissection, hashing and RPS.
Signed-off-by: John Crispin <john@phrozen.org>
---
net/core/flow_dissector.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
--- a/net/core/flow_dissector.c
+++ b/net/core/flow_dissector.c
@@ -4,6 +4,7 @@
#include <linux/ip.h>
#include <linux/ipv6.h>
#include <linux/if_vlan.h>
+#include <net/dsa.h>
#include <net/ip.h>
#include <net/ipv6.h>
#include <net/gre.h>
@@ -123,13 +124,23 @@ bool __skb_flow_dissect(const struct sk_
bool skip_vlan = false;
u8 ip_proto = 0;
bool ret;
-
if (!data) {
data = skb->data;
proto = skb_vlan_tag_present(skb) ?
skb->vlan_proto : skb->protocol;
nhoff = skb_network_offset(skb);
hlen = skb_headlen(skb);
+ if (unlikely(netdev_uses_dsa(skb->dev))) {
+ const struct dsa_device_ops *ops;
+ int offset;
+
+ ops = skb->dev->dsa_ptr->tag_ops;
+ if (ops->flow_dissect &&
+ !ops->flow_dissect(skb, &proto, &offset)) {
+ hlen -= offset;
+ nhoff += offset;
+ }
+ }
}
/* It is ensured by skb_flow_dissector_init() that control key will
@@ -162,6 +173,7 @@ again:
case htons(ETH_P_IP): {
const struct iphdr *iph;
struct iphdr _iph;
+
ip:
iph = __skb_header_pointer(skb, nhoff, sizeof(_iph), data, hlen, &_iph);
if (!iph || iph->ihl < 5)

50
target/linux/mediatek/patches-4.9/0042-net-next-mediatek-honour-special-tag-bit-inside-RX-D.patch Normal file
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@@ -0,0 +1,50 @@
From a306af3b97c56b9e224a2f9ee04838a2d32ff60b Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Wed, 9 Aug 2017 14:44:07 +0200
Subject: [PATCH 42/57] net-next: mediatek: honour special tag bit inside RX
DMA descriptor
For HW NAT/QoS to work the DSA driver needs to turn the special tag bit
inside the ingress control register on. This has the side effect that
the code working out which ingress gmac we have breaks. Fix this by
honouring the special tag bit inside the RX free descriptor.
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 14 ++++++++++----
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 +
2 files changed, 11 insertions(+), 4 deletions(-)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -933,10 +933,16 @@ static int mtk_poll_rx(struct napi_struc
if (!(trxd.rxd2 & RX_DMA_DONE))
break;
- /* find out which mac the packet come from. values start at 1 */
- mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
- RX_DMA_FPORT_MASK;
- mac--;
+ /* find out which mac the packet comes from. If the special tag is
+ * we can assume that the traffic is coming from the builtin mt7530
+ * and the DSA driver has loaded. FPORT will be the physical switch
+ * port in this case rather than the FE forward port id. */
+ if (!(trxd.rxd4 & RX_DMA_SP_TAG)) {
+ /* values start at 1 */
+ mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
+ RX_DMA_FPORT_MASK;
+ mac--;
+ }
netdev = eth->netdev[mac];
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -284,6 +284,7 @@
/* QDMA descriptor rxd4 */
#define RX_DMA_L4_VALID BIT(24)
+#define RX_DMA_SP_TAG BIT(22)
#define RX_DMA_FPORT_SHIFT 19
#define RX_DMA_FPORT_MASK 0x7

41
target/linux/mediatek/patches-4.9/0043-net-next-mediatek-enable-special-tag-indication-for-.patch Normal file
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@@ -0,0 +1,41 @@
From 53e3d9af39805a7e1ba81a047a9ab433be0e82f5 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Wed, 9 Aug 2017 14:56:53 +0200
Subject: [PATCH 43/57] net-next: mediatek: enable special tag indication for
PDMA
The Ingress special tag indication was only enabled for QDMA and not PDMA.
Properly initialize the STAG bit. This broke HW NAT and Qos from working
for traffic coming in via a DSA device. The PPE failed to properly parse
the traffic as it was not expecting the special tag.
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 ++
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++++
2 files changed, 6 insertions(+)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1894,6 +1894,8 @@ static int mtk_hw_init(struct mtk_eth *e
*/
val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
+ val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
+ mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
/* Enable RX VLan Offloading */
if (MTK_HW_FEATURES & NETIF_F_HW_VLAN_CTAG_RX)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -76,6 +76,10 @@
#define MTK_CDMQ_IG_CTRL 0x1400
#define MTK_CDMQ_STAG_EN BIT(0)
+/* CDMP Ingress Control Register */
+#define MTK_CDMP_IG_CTRL 0x400
+#define MTK_CDMP_STAG_EN BIT(0)
+
/* CDMP Exgress Control Register */
#define MTK_CDMP_EG_CTRL 0x404

43
target/linux/mediatek/patches-4.9/0044-net-next-dsa-mediatek-tell-GDMA-when-we-are-turning-.patch Normal file
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@@ -0,0 +1,43 @@
From 6a5932028a4f3217ed7c9d602f269611d95dd8ca Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Wed, 9 Aug 2017 15:13:19 +0200
Subject: [PATCH 44/57] net-next: dsa: mediatek: tell GDMA when we are turning
on the special tag
Enabling this bit will make the RX DMA descriptor enable the SP bit for all
ingress traffic inside the return descriptor. The PPE needs this to know
that a SP is present.
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/dsa/mt7530.c | 5 +++++
drivers/net/dsa/mt7530.h | 4 ++++
2 files changed, 9 insertions(+)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -742,6 +742,11 @@ mt7530_cpu_port_enable(struct mt7530_pri
mt7530_write(priv, MT7530_PVC_P(port),
PORT_SPEC_TAG);
+ /* Enable Mediatek header mode on the GMAC that the cpu port
+ * connects to */
+ regmap_write_bits(priv->ethernet, MTK_GDMA_FWD_CFG(port),
+ GDMA_SPEC_TAG, GDMA_SPEC_TAG);
+
/* Setup the MAC by default for the cpu port */
mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK);
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -22,6 +22,10 @@
#define TRGMII_BASE(x) (0x10000 + (x))
+/* Registers for GDMA configuration access */
+#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
+#define GDMA_SPEC_TAG BIT(24)
+
/* Registers to ethsys access */
#define ETHSYS_CLKCFG0 0x2c
#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)

79
target/linux/mediatek/patches-4.9/0045-net-dsa-mediatek-turn-into-platform-driver.patch Normal file
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@@ -0,0 +1,79 @@
From 1e33784f665cb95c2af5481d3e776d2d3099921b Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 15:57:17 +0200
Subject: [PATCH 45/57] net: dsa: mediatek: turn into platform driver
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/dsa/mt7530.c | 23 +++++++++++++++--------
1 file changed, 15 insertions(+), 8 deletions(-)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -1035,10 +1035,10 @@ static struct dsa_switch_ops mt7530_swit
};
static int
-mt7530_probe(struct mdio_device *mdiodev)
+mt7530_probe(struct platform_device *mdiodev)
{
struct mt7530_priv *priv;
- struct device_node *dn;
+ struct device_node *dn, *mdio;
dn = mdiodev->dev.of_node;
@@ -1086,7 +1086,12 @@ mt7530_probe(struct mdio_device *mdiodev
}
}
- priv->bus = mdiodev->bus;
+ mdio = of_parse_phandle(dn, "dsa,mii-bus", 0);
+ if (!mdio)
+ return -EINVAL;
+ priv->bus = of_mdio_find_bus(mdio);
+ if (!priv->bus)
+ return -EPROBE_DEFER;
priv->dev = &mdiodev->dev;
priv->ds->priv = priv;
priv->ds->dev = &mdiodev->dev;
@@ -1098,8 +1103,8 @@ mt7530_probe(struct mdio_device *mdiodev
return dsa_register_switch(priv->ds, priv->ds->dev->of_node);
}
-static void
-mt7530_remove(struct mdio_device *mdiodev)
+static int
+mt7530_remove(struct platform_device *mdiodev)
{
struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
int ret = 0;
@@ -1116,6 +1121,8 @@ mt7530_remove(struct mdio_device *mdiode
dsa_unregister_switch(priv->ds);
mutex_destroy(&priv->reg_mutex);
+
+ return 0;
}
static const struct of_device_id mt7530_of_match[] = {
@@ -1123,16 +1130,16 @@ static const struct of_device_id mt7530_
{ /* sentinel */ },
};
-static struct mdio_driver mt7530_mdio_driver = {
+static struct platform_driver mtk_mt7530_driver = {
.probe = mt7530_probe,
.remove = mt7530_remove,
- .mdiodrv.driver = {
+ .driver = {
.name = "mt7530",
.of_match_table = mt7530_of_match,
},
};
+module_platform_driver(mtk_mt7530_driver);
-mdio_module_driver(mt7530_mdio_driver);
MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");

56
target/linux/mediatek/patches-4.9/0046-net-mediatek-add-irq-delay.patch Normal file
View File

@@ -0,0 +1,56 @@
From 6e081074df96bf3762c2e6438c383f11a56b0a7e Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 15:58:04 +0200
Subject: [PATCH 46/57] net: mediatek: add irq delay
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 7 ++++++-
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 +++++++-
2 files changed, 13 insertions(+), 2 deletions(-)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1904,8 +1904,13 @@ static int mtk_hw_init(struct mtk_eth *e
mtk_w32(eth, 0, MTK_CDMP_EG_CTRL);
/* disable delay and normal interrupt */
- mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
+#ifdef MTK_IRQ_DLY
+ mtk_w32(eth, 0x84048404, MTK_PDMA_DELAY_INT);
+ mtk_w32(eth, 0x84048404, MTK_QDMA_DELAY_INT);
+#else
mtk_w32(eth, 0, MTK_PDMA_DELAY_INT);
+ mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
+#endif
mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -12,6 +12,8 @@
* Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
*/
+#define MTK_IRQ_DLY
+
#ifndef MTK_ETH_H
#define MTK_ETH_H
@@ -220,11 +222,15 @@
#define MTK_TX_DONE_INT2 BIT(2)
#define MTK_TX_DONE_INT1 BIT(1)
#define MTK_TX_DONE_INT0 BIT(0)
+#ifdef MTK_IRQ_DLY
+#define MTK_RX_DONE_INT BIT(30)
+#define MTK_TX_DONE_INT BIT(28)
+#else
#define MTK_RX_DONE_INT (MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1 | \
MTK_RX_DONE_INT2 | MTK_RX_DONE_INT3)
#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
-
+#endif
/* QDMA Interrupt grouping registers */
#define MTK_QDMA_INT_GRP1 0x1a20
#define MTK_QDMA_INT_GRP2 0x1a24

208
target/linux/mediatek/patches-4.9/0047-net-next-mediatek-split-IRQ-register-locking-into-TX.patch Normal file
View File

@@ -0,0 +1,208 @@
From 5afceece38fa30e3c71e7ed9ac62aa70ba8cfbb1 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Fri, 16 Jun 2017 10:00:30 +0200
Subject: [PATCH 47/57] net-next: mediatek: split IRQ register locking into TX
and RX
Originally the driver only utilized the new QDMA engine. The current code
still assumes this is the case when locking the IRQ mask register. Since
RX now runs on the old style PDMA engine we can add a second lock. This
patch reduces the IRQ latency as the TX and RX path no longer need to wait
on each other under heavy load.
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 79 ++++++++++++++++++-----------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 +-
2 files changed, 54 insertions(+), 30 deletions(-)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -372,28 +372,48 @@ static void mtk_mdio_cleanup(struct mtk_
mdiobus_unregister(eth->mii_bus);
}
-static inline void mtk_irq_disable(struct mtk_eth *eth,
- unsigned reg, u32 mask)
+static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
{
unsigned long flags;
u32 val;
- spin_lock_irqsave(&eth->irq_lock, flags);
- val = mtk_r32(eth, reg);
- mtk_w32(eth, val & ~mask, reg);
- spin_unlock_irqrestore(&eth->irq_lock, flags);
+ spin_lock_irqsave(&eth->tx_irq_lock, flags);
+ val = mtk_r32(eth, MTK_QDMA_INT_MASK);
+ mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
+ spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
}
-static inline void mtk_irq_enable(struct mtk_eth *eth,
- unsigned reg, u32 mask)
+static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
{
unsigned long flags;
u32 val;
- spin_lock_irqsave(&eth->irq_lock, flags);
- val = mtk_r32(eth, reg);
- mtk_w32(eth, val | mask, reg);
- spin_unlock_irqrestore(&eth->irq_lock, flags);
+ spin_lock_irqsave(&eth->tx_irq_lock, flags);
+ val = mtk_r32(eth, MTK_QDMA_INT_MASK);
+ mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
+ spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
+}
+
+static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
+{
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&eth->rx_irq_lock, flags);
+ val = mtk_r32(eth, MTK_PDMA_INT_MASK);
+ mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK);
+ spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
+}
+
+static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
+{
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&eth->rx_irq_lock, flags);
+ val = mtk_r32(eth, MTK_PDMA_INT_MASK);
+ mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK);
+ spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
}
static int mtk_set_mac_address(struct net_device *dev, void *p)
@@ -1116,7 +1136,7 @@ static int mtk_napi_tx(struct napi_struc
return budget;
napi_complete(napi);
- mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
+ mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
return tx_done;
}
@@ -1150,7 +1170,7 @@ poll_again:
goto poll_again;
}
napi_complete(napi);
- mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
+ mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
return rx_done + budget - remain_budget;
}
@@ -1699,7 +1719,7 @@ static irqreturn_t mtk_handle_irq_rx(int
if (likely(napi_schedule_prep(&eth->rx_napi))) {
__napi_schedule(&eth->rx_napi);
- mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
+ mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
}
return IRQ_HANDLED;
@@ -1711,7 +1731,7 @@ static irqreturn_t mtk_handle_irq_tx(int
if (likely(napi_schedule_prep(&eth->tx_napi))) {
__napi_schedule(&eth->tx_napi);
- mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
+ mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
}
return IRQ_HANDLED;
@@ -1723,11 +1743,11 @@ static void mtk_poll_controller(struct n
struct mtk_mac *mac = netdev_priv(dev);
struct mtk_eth *eth = mac->hw;
- mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
- mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
+ mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
+ mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
mtk_handle_irq_rx(eth->irq[2], dev);
- mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
- mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
+ mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
+ mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
}
#endif
@@ -1770,8 +1790,8 @@ static int mtk_open(struct net_device *d
napi_enable(&eth->tx_napi);
napi_enable(&eth->rx_napi);
- mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
- mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
+ mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
+ mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
}
atomic_inc(&eth->dma_refcnt);
@@ -1816,8 +1836,8 @@ static int mtk_stop(struct net_device *d
if (!atomic_dec_and_test(&eth->dma_refcnt))
return 0;
- mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
- mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
+ mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
+ mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
napi_disable(&eth->tx_napi);
napi_disable(&eth->rx_napi);
@@ -1911,8 +1931,8 @@ static int mtk_hw_init(struct mtk_eth *e
mtk_w32(eth, 0, MTK_PDMA_DELAY_INT);
mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
#endif
- mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
- mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
+ mtk_tx_irq_disable(eth, ~0);
+ mtk_rx_irq_disable(eth, ~0);
mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
mtk_w32(eth, 0, MTK_RST_GL);
@@ -1983,8 +2003,8 @@ static void mtk_uninit(struct net_device
phy_disconnect(dev->phydev);
if (of_phy_is_fixed_link(mac->of_node))
of_phy_deregister_fixed_link(mac->of_node);
- mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
- mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
+ mtk_tx_irq_disable(eth, ~0);
+ mtk_rx_irq_disable(eth, ~0);
}
static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
@@ -2442,7 +2462,8 @@ static int mtk_probe(struct platform_dev
return PTR_ERR(eth->base);
spin_lock_init(&eth->page_lock);
- spin_lock_init(&eth->irq_lock);
+ spin_lock_init(&eth->tx_irq_lock);
+ spin_lock_init(&eth->rx_irq_lock);
eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
"mediatek,ethsys");
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -526,6 +526,8 @@ struct mtk_rx_ring {
* @dev: The device pointer
* @base: The mapped register i/o base
* @page_lock: Make sure that register operations are atomic
+ * @tx_irq__lock: Make sure that IRQ register operations are atomic
+ * @rx_irq__lock: Make sure that IRQ register operations are atomic
* @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
* dummy for NAPI to work
* @netdev: The netdev instances
@@ -555,7 +557,8 @@ struct mtk_eth {
struct device *dev;
void __iomem *base;
spinlock_t page_lock;
- spinlock_t irq_lock;
+ spinlock_t tx_irq_lock;
+ spinlock_t rx_irq_lock;
struct net_device dummy_dev;
struct net_device *netdev[MTK_MAX_DEVS];
struct mtk_mac *mac[MTK_MAX_DEVS];

90
target/linux/mediatek/patches-4.9/0048-net-core-add-RPS-balancer.patch Normal file
View File

@@ -0,0 +1,90 @@
From 3e969c9695b45e1a052d43b367096ec99f2f0aac Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 15:58:29 +0200
Subject: [PATCH 48/57] net: core: add RPS balancer
Signed-off-by: John Crispin <john@phrozen.org>
---
net/core/dev.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -3547,6 +3547,58 @@ set_rps_cpu(struct net_device *dev, stru
return rflow;
}
+#define RPS_TBL_SIZE_SHIFT 10
+#define RPS_TBL_SIZE (1 << RPS_TBL_SIZE_SHIFT)
+struct rps_table {
+ int core;
+ struct timer_list expire;
+};
+static struct rps_table rps_table[RPS_TBL_SIZE];
+static int rps_table_last_core;
+
+static void rps_table_expire(unsigned long data)
+{
+ struct rps_table *entry = (struct rps_table *) data;
+
+ entry->core = -1;
+}
+
+static int rps_table_core(struct rps_map *map)
+{
+ int i;
+
+ for (i = 0; i < map->len; i++) {
+ int cpu = map->cpus[(rps_table_last_core + i + 1) % map->len];
+ if (cpu_online(cpu)) {
+ rps_table_last_core = cpu;
+ return cpu;
+ }
+ }
+ return map->cpus[0];
+}
+
+static int rps_table_lookup(struct rps_map *map, u32 hash)
+{
+ int bucket = hash & 0x3ff;
+
+ if (rps_table[bucket].core < 0)
+ rps_table[bucket].core = rps_table_core(map);
+ mod_timer(&rps_table[bucket].expire, jiffies + HZ);
+
+ return rps_table[bucket].core;
+}
+
+static void rps_table_init(void)
+{
+ int i;
+
+ for (i = 0; i < RPS_TBL_SIZE; i++) {
+ rps_table[i].core = -1;
+ setup_timer(&rps_table[i].expire, rps_table_expire,
+ (unsigned long) &rps_table[i]);
+ }
+}
+
/*
* get_rps_cpu is called from netif_receive_skb and returns the target
* CPU from the RPS map of the receiving queue for a given skb.
@@ -3636,7 +3688,7 @@ static int get_rps_cpu(struct net_device
try_rps:
if (map) {
- tcpu = map->cpus[reciprocal_scale(hash, map->len)];
+ tcpu = rps_table_lookup(map, hash);
if (cpu_online(tcpu)) {
cpu = tcpu;
goto done;
@@ -8426,6 +8478,9 @@ static int __init net_dev_init(void)
sd->backlog.weight = weight_p;
}
+ if (IS_ENABLED(CONFIG_RPS))
+ rps_table_init();
+
dev_boot_phase = 0;
/* The loopback device is special if any other network devices

20
target/linux/mediatek/patches-4.9/0049-net-mediatek-add-rx-queue.patch Normal file
View File

@@ -0,0 +1,20 @@
From 066b30a76a0d13cbd2c0d463f9a1e87efc352679 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 15:58:46 +0200
Subject: [PATCH 49/57] net: mediatek: add rx queue
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1009,6 +1009,7 @@ static int mtk_poll_rx(struct napi_struc
RX_DMA_VID(trxd.rxd3))
__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
RX_DMA_VID(trxd.rxd3));
+ skb_record_rx_queue(skb, 0);
napi_gro_receive(napi, skb);
ring->data[idx] = new_data;

21
target/linux/mediatek/patches-4.9/0050-net-mediatek-add-trgmii-clock.patch Normal file
View File

@@ -0,0 +1,21 @@
From 67c4af99af02d86b627a8cde2e99cc4c9699d2ce Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 15:59:08 +0200
Subject: [PATCH 50/57] net: mediatek: add trgmii clock
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1873,6 +1873,8 @@ static int mtk_hw_init(struct mtk_eth *e
pm_runtime_enable(eth->dev);
pm_runtime_get_sync(eth->dev);
+ clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 250000000);
+
clk_prepare_enable(eth->clks[MTK_CLK_ETHIF]);
clk_prepare_enable(eth->clks[MTK_CLK_ESW]);
clk_prepare_enable(eth->clks[MTK_CLK_GP1]);

21
target/linux/mediatek/patches-4.9/0051-net-mediatek-increase-tx_timeout.patch Normal file
View File

@@ -0,0 +1,21 @@
From 5cbf53c7e5eac5bacc409461888789accdaf8eec Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 16:00:06 +0200
Subject: [PATCH 51/57] net: mediatek: increase tx_timeout
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -2384,7 +2384,7 @@ static int mtk_add_mac(struct mtk_eth *e
mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
SET_NETDEV_DEV(eth->netdev[id], eth->dev);
- eth->netdev[id]->watchdog_timeo = 5 * HZ;
+ eth->netdev[id]->watchdog_timeo = 30 * HZ;
eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
eth->netdev[id]->base_addr = (unsigned long)eth->base;

21
target/linux/mediatek/patches-4.9/0052-net-phy-add-FC.patch Normal file
View File

@@ -0,0 +1,21 @@
From 18b2169d84b47a3414164e5e40f23fb7e875707c Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 16:00:28 +0200
Subject: [PATCH 52/57] net: phy: add FC
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/phy/phy_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -1799,7 +1799,7 @@ static struct phy_driver genphy_driver[]
.config_init = genphy_config_init,
.features = PHY_GBIT_FEATURES | SUPPORTED_MII |
SUPPORTED_AUI | SUPPORTED_FIBRE |
- SUPPORTED_BNC,
+ SUPPORTED_BNC | SUPPORTED_Pause | SUPPORTED_Asym_Pause,
.config_aneg = genphy_config_aneg,
.aneg_done = genphy_aneg_done,
.read_status = genphy_read_status,

68
target/linux/mediatek/patches-4.9/0053-net-dsa-mediatek-add-software-phy-polling.patch Normal file
View File

@@ -0,0 +1,68 @@
From 53eec2c3580e63fdebfc25ae324f30cd8aa4403b Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 16:00:46 +0200
Subject: [PATCH 53/57] net: dsa: mediatek: add software phy polling
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/dsa/mt7530.c | 38 ++++++++++++++++++++++++++++++++++++++
drivers/net/dsa/mt7530.h | 1 +
2 files changed, 39 insertions(+)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -728,6 +728,44 @@ static void mt7530_adjust_link(struct ds
* all finished.
*/
mt7623_pad_clk_setup(ds);
+ } else {
+ u16 lcl_adv = 0, rmt_adv = 0;
+ u8 flowctrl;
+ u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE;
+
+ switch (phydev->speed) {
+ case SPEED_1000:
+ mcr |= PMCR_FORCE_SPEED_1000;
+ break;
+ case SPEED_100:
+ mcr |= PMCR_FORCE_SPEED_100;
+ break;
+ };
+
+ if (phydev->link)
+ mcr |= PMCR_FORCE_LNK;
+
+ if (phydev->duplex) {
+ mcr |= PMCR_FORCE_FDX;
+
+ if (phydev->pause)
+ rmt_adv = LPA_PAUSE_CAP;
+ if (phydev->asym_pause)
+ rmt_adv |= LPA_PAUSE_ASYM;
+
+ if (phydev->advertising & ADVERTISED_Pause)
+ lcl_adv |= ADVERTISE_PAUSE_CAP;
+ if (phydev->advertising & ADVERTISED_Asym_Pause)
+ lcl_adv |= ADVERTISE_PAUSE_ASYM;
+
+ flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
+
+ if (flowctrl & FLOW_CTRL_TX)
+ mcr |= PMCR_TX_FC_EN;
+ if (flowctrl & FLOW_CTRL_RX)
+ mcr |= PMCR_RX_FC_EN;
+ }
+ mt7530_write(priv, MT7530_PMCR_P(port), mcr);
}
}
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -155,6 +155,7 @@ enum mt7530_stp_state {
#define PMCR_TX_FC_EN BIT(5)
#define PMCR_RX_FC_EN BIT(4)
#define PMCR_FORCE_SPEED_1000 BIT(3)
+#define PMCR_FORCE_SPEED_100 BIT(2)
#define PMCR_FORCE_FDX BIT(1)
#define PMCR_FORCE_LNK BIT(0)
#define PMCR_COMMON_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \

105
target/linux/mediatek/patches-4.9/0054-net-ethernet-mediatek-fixed-deadlock-captured-by-loc.patch Normal file
View File

@@ -0,0 +1,105 @@
From 746bf1c3e561aba396cd40e6540245646461117d Mon Sep 17 00:00:00 2001
From: Sean Wang <sean.wang@mediatek.com>
Date: Tue, 4 Jul 2017 11:17:36 +0800
Subject: [PATCH 54/57] net: ethernet: mediatek: fixed deadlock captured by
lockdep
Lockdep found an inconsistent lock state when mtk_get_stats64 is called
in user context while NAPI updates MAC statistics in softirq.
Use spin_trylock_bh/spin_unlock_bh fix following lockdep warning.
[ 81.321030] WARNING: inconsistent lock state
[ 81.325266] 4.12.0-rc1-00035-gd9dda65 #32 Not tainted
[ 81.330273] --------------------------------
[ 81.334505] inconsistent {SOFTIRQ-ON-W} -> {IN-SOFTIRQ-W} usage.
[ 81.340464] ksoftirqd/0/7 [HC0[0]:SC1[1]:HE1:SE0] takes:
[ 81.345731] (&syncp->seq#2){+.?...}, at: [<c054ba3c>] mtk_handle_status_irq.part.6+0x70/0x84
[ 81.354219] {SOFTIRQ-ON-W} state was registered at:
[ 81.359062] lock_acquire+0xfc/0x2b0
[ 81.362696] mtk_stats_update_mac+0x60/0x2c0
[ 81.367017] mtk_get_stats64+0x17c/0x18c
[ 81.370995] dev_get_stats+0x48/0xbc
[ 81.374628] rtnl_fill_stats+0x48/0x128
[ 81.378520] rtnl_fill_ifinfo+0x4ac/0xd1c
[ 81.382584] rtmsg_ifinfo_build_skb+0x7c/0xe0
[ 81.386991] rtmsg_ifinfo.part.5+0x24/0x54
[ 81.391139] rtmsg_ifinfo+0x24/0x28
[ 81.394685] __dev_notify_flags+0xa4/0xac
[ 81.398749] dev_change_flags+0x50/0x58
[ 81.402640] devinet_ioctl+0x768/0x85c
[ 81.406444] inet_ioctl+0x1a4/0x1d0
[ 81.409990] sock_ioctl+0x16c/0x33c
[ 81.413538] do_vfs_ioctl+0xb4/0xa34
[ 81.417169] SyS_ioctl+0x44/0x6c
[ 81.420458] ret_fast_syscall+0x0/0x1c
[ 81.424260] irq event stamp: 3354692
[ 81.427806] hardirqs last enabled at (3354692): [<c0678168>] net_rx_action+0xc0/0x504
[ 81.435660] hardirqs last disabled at (3354691): [<c0678134>] net_rx_action+0x8c/0x504
[ 81.443515] softirqs last enabled at (3354106): [<c0101944>] __do_softirq+0x4b4/0x614
[ 81.451370] softirqs last disabled at (3354109): [<c012f0c4>] run_ksoftirqd+0x44/0x80
[ 81.459134]
[ 81.459134] other info that might help us debug this:
[ 81.465608] Possible unsafe locking scenario:
[ 81.465608]
[ 81.471478] CPU0
[ 81.473900] ----
[ 81.476321] lock(&syncp->seq#2);
[ 81.479701] <Interrupt>
[ 81.482294] lock(&syncp->seq#2);
[ 81.485847]
[ 81.485847] *** DEADLOCK ***
[ 81.485847]
[ 81.491720] 1 lock held by ksoftirqd/0/7:
[ 81.495693] #0: (&(&mac->hw_stats->stats_lock)->rlock){+.+...}, at: [<c054ba14>] mtk_handle_status_irq.part.6+0x48/0x84
[ 81.506579]
[ 81.506579] stack backtrace:
[ 81.510904] CPU: 0 PID: 7 Comm: ksoftirqd/0 Not tainted 4.12.0-rc1-00035-gd9dda65 #32
[ 81.518668] Hardware name: Mediatek Cortex-A7 (Device Tree)
[ 81.524208] [<c0113dc4>] (unwind_backtrace) from [<c010e3f0>] (show_stack+0x20/0x24)
[ 81.531899] [<c010e3f0>] (show_stack) from [<c03f9c64>] (dump_stack+0xb4/0xe0)
[ 81.539072] [<c03f9c64>] (dump_stack) from [<c017e970>] (print_usage_bug+0x234/0x2e0)
[ 81.546846] [<c017e970>] (print_usage_bug) from [<c017f058>] (mark_lock+0x63c/0x7bc)
[ 81.554532] [<c017f058>] (mark_lock) from [<c017fe90>] (__lock_acquire+0x654/0x1bfc)
[ 81.562217] [<c017fe90>] (__lock_acquire) from [<c0181d04>] (lock_acquire+0xfc/0x2b0)
[ 81.569990] [<c0181d04>] (lock_acquire) from [<c054b76c>] (mtk_stats_update_mac+0x60/0x2c0)
[ 81.578283] [<c054b76c>] (mtk_stats_update_mac) from [<c054ba3c>] (mtk_handle_status_irq.part.6+0x70/0x84)
[ 81.587865] [<c054ba3c>] (mtk_handle_status_irq.part.6) from [<c054c2b8>] (mtk_napi_tx+0x358/0x37c)
[ 81.596845] [<c054c2b8>] (mtk_napi_tx) from [<c06782ec>] (net_rx_action+0x244/0x504)
[ 81.604533] [<c06782ec>] (net_rx_action) from [<c01015c4>] (__do_softirq+0x134/0x614)
[ 81.612306] [<c01015c4>] (__do_softirq) from [<c012f0c4>] (run_ksoftirqd+0x44/0x80)
[ 81.619907] [<c012f0c4>] (run_ksoftirqd) from [<c0154680>] (smpboot_thread_fn+0x14c/0x25c)
[ 81.628110] [<c0154680>] (smpboot_thread_fn) from [<c014f8cc>] (kthread+0x150/0x180)
[ 81.635798] [<c014f8cc>] (kthread) from [<c0109290>] (ret_from_fork+0x14/0x24)
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -493,9 +493,9 @@ static struct rtnl_link_stats64 * mtk_ge
unsigned int start;
if (netif_running(dev) && netif_device_present(dev)) {
- if (spin_trylock(&hw_stats->stats_lock)) {
+ if (spin_trylock_bh(&hw_stats->stats_lock)) {
mtk_stats_update_mac(mac);
- spin_unlock(&hw_stats->stats_lock);
+ spin_unlock_bh(&hw_stats->stats_lock);
}
}
@@ -2229,9 +2229,9 @@ static void mtk_get_ethtool_stats(struct
return;
if (netif_running(dev) && netif_device_present(dev)) {
- if (spin_trylock(&hwstats->stats_lock)) {
+ if (spin_trylock_bh(&hwstats->stats_lock)) {
mtk_stats_update_mac(mac);
- spin_unlock(&hwstats->stats_lock);
+ spin_unlock_bh(&hwstats->stats_lock);
}
}

31
target/linux/mediatek/patches-4.9/0055-net-ethernet-mediatek-avoid-potential-invalid-memory.patch Normal file
View File

@@ -0,0 +1,31 @@
From a3360b3543b9fb833ba691019e396e72293a313f Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 16:31:45 +0200
Subject: [PATCH 55/57] net: ethernet: mediatek: avoid potential invalid memory
access
Potential dangerous invalid memory might be accessed if invalid mac value
reflected from the forward port field in rxd4 caused by possible potential
hardware defects. So added a simple sanity checker to avoid the kind of
situation happening.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -964,6 +964,10 @@ static int mtk_poll_rx(struct napi_struc
mac--;
}
+ if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
+ !eth->netdev[mac]))
+ goto release_desc;
+
netdev = eth->netdev[mac];
if (unlikely(test_bit(MTK_RESETTING, &eth->state)))

119
target/linux/mediatek/patches-4.9/0056-net-mediatek-add-hw-nat-support.patch Normal file
View File

@@ -0,0 +1,119 @@
From 043efc0e619e04661be2b1889382db2fdd378145 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 16:34:36 +0200
Subject: [PATCH 56/57] net: mediatek: add hw nat support
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/ethernet/mediatek/Kconfig | 7 +++++++
drivers/net/ethernet/mediatek/Makefile | 1 +
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 13 +++++++++++++
net/netfilter/nf_conntrack_proto_tcp.c | 19 +++++++++++++++++++
4 files changed, 40 insertions(+)
--- a/drivers/net/ethernet/mediatek/Kconfig
+++ b/drivers/net/ethernet/mediatek/Kconfig
@@ -14,4 +14,11 @@ config NET_MEDIATEK_SOC
This driver supports the gigabit ethernet MACs in the
MediaTek MT2701/MT7623 chipset family.
+config NET_MEDIATEK_HNAT
+ tristate "MediaTek MT7623 hardware NAT support"
+ depends on NET_MEDIATEK_SOC && NF_CONNTRACK && NF_CONNTRACK_IPV4 && IP_NF_NAT && IP_NF_TARGET_MASQUERADE
+ ---help---
+ This driver supports the hardwaer NAT in the
+ MediaTek MT2701/MT7623 chipset family.
+
endif #NET_VENDOR_MEDIATEK
--- a/drivers/net/ethernet/mediatek/Makefile
+++ b/drivers/net/ethernet/mediatek/Makefile
@@ -3,3 +3,4 @@
#
obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth_soc.o
+obj-$(CONFIG_NET_MEDIATEK_HNAT) += mtk_hnat/
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -23,6 +23,10 @@
#include <linux/reset.h>
#include <linux/tcp.h>
+#if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE)
+#include "mtk_hnat/nf_hnat_mtk.h"
+#endif
+
#include "mtk_eth_soc.h"
static int mtk_msg_level = -1;
@@ -649,6 +653,11 @@ static int mtk_tx_map(struct sk_buff *sk
return -ENOMEM;
/* set the forward port */
+#if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE)
+ if (HNAT_SKB_CB2(skb)->magic == 0x78681415)
+ fport |= 0x4 << TX_DMA_FPORT_SHIFT;
+ else
+#endif
fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
txd4 |= fport;
@@ -1013,6 +1022,10 @@ static int mtk_poll_rx(struct napi_struc
RX_DMA_VID(trxd.rxd3))
__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
RX_DMA_VID(trxd.rxd3));
+#if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE)
+ *(u32 *)(skb->head) = trxd.rxd4;
+ skb_hnat_alg(skb) = 0;
+#endif
skb_record_rx_queue(skb, 0);
napi_gro_receive(napi, skb);
--- a/net/netfilter/nf_conntrack_proto_tcp.c
+++ b/net/netfilter/nf_conntrack_proto_tcp.c
@@ -11,6 +11,7 @@
#include <linux/types.h>
#include <linux/timer.h>
#include <linux/module.h>
+#include <linux/inetdevice.h>
#include <linux/in.h>
#include <linux/tcp.h>
#include <linux/spinlock.h>
@@ -19,6 +20,7 @@
#include <net/ip6_checksum.h>
#include <asm/unaligned.h>
+#include <net/ip.h>
#include <net/tcp.h>
#include <linux/netfilter.h>
@@ -53,6 +55,11 @@ static int nf_ct_tcp_max_retrans __read_
/* FIXME: Examine ipfilter's timeouts and conntrack transitions more
closely. They're more complex. --RR */
+#ifndef IPV4_DEVCONF_DFLT
+ #define IPV4_DEVCONF_DFLT(net, attr) \
+ IPV4_DEVCONF((*net->ipv4.devconf_dflt), attr)
+#endif
+
static const char *const tcp_conntrack_names[] = {
"NONE",
"SYN_SENT",
@@ -519,6 +526,18 @@ static bool tcp_in_window(const struct n
if (nf_ct_tcp_no_window_check)
return true;
+ if (net) {
+ if ((net->ipv4.devconf_all && net->ipv4.devconf_dflt && net->ipv6.devconf_all) &&
+ net->ipv6.devconf_dflt) {
+ if ((IPV4_DEVCONF_DFLT(net, FORWARDING) ||
+ IPV4_DEVCONF_ALL(net, FORWARDING)) ||
+ (net->ipv6.devconf_all->forwarding ||
+ net->ipv6.devconf_dflt->forwarding)) {
+ return true;
+ }
+ }
+ }
+
/*
* Get the required data from the packet.
*/

121
target/linux/mediatek/patches-4.9/0057-net-mediatek-add-HW-QoS-support.patch Normal file
View File

@@ -0,0 +1,121 @@
From 660c13dfbacbf37f090a66a2b14f0c5ce7cbec81 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 10 Aug 2017 16:38:27 +0200
Subject: [PATCH 57/57] net: mediatek: add HW QoS support
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/net/ethernet/mediatek/Kconfig | 7 ++++
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 60 ++++++++++++++++++++++++++++-
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +-
3 files changed, 66 insertions(+), 3 deletions(-)
--- a/drivers/net/ethernet/mediatek/Kconfig
+++ b/drivers/net/ethernet/mediatek/Kconfig
@@ -21,4 +21,11 @@ config NET_MEDIATEK_HNAT
This driver supports the hardwaer NAT in the
MediaTek MT2701/MT7623 chipset family.
+config NET_MEDIATEK_HW_QOS
+ tristate "MediaTek MT7623 hardware QoS support"
+ depends on NET_MEDIATEK_SOC
+ ---help---
+ This driver supports the hardware QoS in the
+ MediaTek MT2701/MT7623 chipset family.
+
endif #NET_VENDOR_MEDIATEK
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -23,6 +23,17 @@
#include <linux/reset.h>
#include <linux/tcp.h>
+#if defined(CONFIG_NET_MEDIATEK_HW_QOS)
+struct mtk_ioctl_reg {
+ unsigned int off;
+ unsigned int val;
+};
+
+#define REG_HQOS_MAX 0x3FFF
+#define RAETH_QDMA_REG_READ 0x89F8
+#define RAETH_QDMA_REG_WRITE 0x89F9
+#endif
+
#if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE)
#include "mtk_hnat/nf_hnat_mtk.h"
#endif
@@ -646,7 +657,7 @@ static int mtk_tx_map(struct sk_buff *sk
dma_addr_t mapped_addr;
unsigned int nr_frags;
int i, n_desc = 1;
- u32 txd4 = 0, fport;
+ u32 txd3 = 0, txd4 = 0, fport;
itxd = ring->next_free;
if (itxd == ring->last_free)
@@ -675,6 +686,12 @@ static int mtk_tx_map(struct sk_buff *sk
// if (skb_vlan_tag_present(skb))
// txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
+#ifdef CONFIG_NET_MEDIATEK_HW_QOS
+ txd3 |= skb->mark & 0x7;
+ if (mac->id)
+ txd3 += 8;
+#endif
+
mapped_addr = dma_map_single(eth->dev, skb->data,
skb_headlen(skb), DMA_TO_DEVICE);
if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
@@ -718,7 +735,8 @@ static int mtk_tx_map(struct sk_buff *sk
WRITE_ONCE(txd->txd1, mapped_addr);
WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
TX_DMA_PLEN0(frag_map_size) |
- last_frag * TX_DMA_LS0));
+ last_frag * TX_DMA_LS0 |
+ txd3));
WRITE_ONCE(txd->txd4, fport);
tx_buf = mtk_desc_to_tx_buf(ring, txd);
@@ -2029,7 +2047,31 @@ static void mtk_uninit(struct net_device
static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
+#if defined(CONFIG_NET_MEDIATEK_HW_QOS)
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+ struct mtk_ioctl_reg reg;
+#endif
+
switch (cmd) {
+#if defined(CONFIG_NET_MEDIATEK_HW_QOS)
+ case RAETH_QDMA_REG_READ:
+ copy_from_user(&reg, ifr->ifr_data, sizeof(reg));
+ if (reg.off > REG_HQOS_MAX)
+ return -EINVAL;
+ reg.val = mtk_r32(eth, 0x1800 + reg.off);
+// printk("read reg off:%x val:%x\n", reg.off, reg.val);
+ copy_to_user(ifr->ifr_data, &reg, sizeof(reg));
+ return 0;
+
+ case RAETH_QDMA_REG_WRITE:
+ copy_from_user(&reg, ifr->ifr_data, sizeof(reg));
+ if (reg.off > REG_HQOS_MAX)
+ return -EINVAL;
+ mtk_w32(eth, reg.val, 0x1800 + reg.off);
+// printk("write reg off:%x val:%x\n", reg.off, reg.val);
+ return 0;
+#endif
case SIOCGMIIPHY:
case SIOCGMIIREG:
case SIOCSMIIREG:
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -20,7 +20,7 @@
#define MTK_QDMA_PAGE_SIZE 2048
#define MTK_MAX_RX_LENGTH 1536
#define MTK_TX_DMA_BUF_LEN 0x3fff
-#define MTK_DMA_SIZE 256
+#define MTK_DMA_SIZE 2048
#define MTK_NAPI_WEIGHT 64
#define MTK_MAC_COUNT 2
#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)

470
target/linux/mediatek/patches-4.9/0058-pinctrl-update.patch Normal file
View File

@@ -0,0 +1,470 @@
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -15,12 +15,6 @@ config PINCTRL_MT2701
default MACH_MT2701
select PINCTRL_MTK
-config PINCTRL_MT7623
- bool "Mediatek MT7623 pin control" if COMPILE_TEST && !MACH_MT7623
- depends on OF
- default MACH_MT7623
- select PINCTRL_MTK_COMMON
-
config PINCTRL_MT8135
bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
depends on OF
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -3,7 +3,6 @@ obj-y += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
-obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
--- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
@@ -565,6 +565,7 @@ static int mt2701_pinctrl_probe(struct p
static const struct of_device_id mt2701_pctrl_match[] = {
{ .compatible = "mediatek,mt2701-pinctrl", },
+ { .compatible = "mediatek,mt7623-pinctrl", },
{}
};
MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
--- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
- * Copyright (c) 2016 John Crispin <blogic@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/regmap.h>
-
-#include "pinctrl-mtk-common.h"
-#include "pinctrl-mtk-mt7623.h"
-
-static const struct mtk_drv_group_desc mt7623_drv_grp[] = {
- /* 0E4E8SR 4/8/12/16 */
- MTK_DRV_GRP(4, 16, 1, 2, 4),
- /* 0E2E4SR 2/4/6/8 */
- MTK_DRV_GRP(2, 8, 1, 2, 2),
- /* E8E4E2 2/4/6/8/10/12/14/16 */
- MTK_DRV_GRP(2, 16, 0, 2, 2)
-};
-
-#define DRV_SEL0 0xf50
-#define DRV_SEL1 0xf60
-#define DRV_SEL2 0xf70
-#define DRV_SEL3 0xf80
-#define DRV_SEL4 0xf90
-#define DRV_SEL5 0xfa0
-#define DRV_SEL6 0xfb0
-#define DRV_SEL7 0xfe0
-#define DRV_SEL8 0xfd0
-#define DRV_SEL9 0xff0
-#define DRV_SEL10 0xf00
-
-#define MSDC0_CTRL0 0xcc0
-#define MSDC0_CTRL1 0xcd0
-#define MSDC0_CTRL2 0xce0
-#define MSDC0_CTRL3 0xcf0
-#define MSDC0_CTRL4 0xd00
-#define MSDC0_CTRL5 0xd10
-#define MSDC0_CTRL6 0xd20
-#define MSDC1_CTRL0 0xd30
-#define MSDC1_CTRL1 0xd40
-#define MSDC1_CTRL2 0xd50
-#define MSDC1_CTRL3 0xd60
-#define MSDC1_CTRL4 0xd70
-#define MSDC1_CTRL5 0xd80
-#define MSDC1_CTRL6 0xd90
-
-#define IES_EN0 0xb20
-#define IES_EN1 0xb30
-#define IES_EN2 0xb40
-
-#define SMT_EN0 0xb50
-#define SMT_EN1 0xb60
-#define SMT_EN2 0xb70
-
-static const struct mtk_pin_drv_grp mt7623_pin_drv[] = {
- MTK_PIN_DRV_GRP(0, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(1, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(2, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(3, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(4, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(5, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(6, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(7, DRV_SEL0, 4, 1),
- MTK_PIN_DRV_GRP(8, DRV_SEL0, 4, 1),
- MTK_PIN_DRV_GRP(9, DRV_SEL0, 4, 1),
- MTK_PIN_DRV_GRP(10, DRV_SEL0, 8, 1),
- MTK_PIN_DRV_GRP(11, DRV_SEL0, 8, 1),
- MTK_PIN_DRV_GRP(12, DRV_SEL0, 8, 1),
- MTK_PIN_DRV_GRP(13, DRV_SEL0, 8, 1),
- MTK_PIN_DRV_GRP(14, DRV_SEL0, 12, 0),
- MTK_PIN_DRV_GRP(15, DRV_SEL0, 12, 0),
- MTK_PIN_DRV_GRP(18, DRV_SEL1, 4, 0),
- MTK_PIN_DRV_GRP(19, DRV_SEL1, 4, 0),
- MTK_PIN_DRV_GRP(20, DRV_SEL1, 4, 0),
- MTK_PIN_DRV_GRP(21, DRV_SEL1, 4, 0),
- MTK_PIN_DRV_GRP(22, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(23, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(24, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(25, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(26, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(27, DRV_SEL1, 12, 0),
- MTK_PIN_DRV_GRP(28, DRV_SEL1, 12, 0),
- MTK_PIN_DRV_GRP(29, DRV_SEL1, 12, 0),
- MTK_PIN_DRV_GRP(33, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(34, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(35, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(36, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(37, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(39, DRV_SEL2, 8, 1),
- MTK_PIN_DRV_GRP(40, DRV_SEL2, 8, 1),
- MTK_PIN_DRV_GRP(41, DRV_SEL2, 8, 1),
- MTK_PIN_DRV_GRP(42, DRV_SEL2, 8, 1),
- MTK_PIN_DRV_GRP(43, DRV_SEL2, 12, 0),
- MTK_PIN_DRV_GRP(44, DRV_SEL2, 12, 0),
- MTK_PIN_DRV_GRP(45, DRV_SEL2, 12, 0),
- MTK_PIN_DRV_GRP(47, DRV_SEL3, 0, 0),
- MTK_PIN_DRV_GRP(48, DRV_SEL3, 0, 0),
- MTK_PIN_DRV_GRP(49, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(53, DRV_SEL3, 12, 0),
- MTK_PIN_DRV_GRP(54, DRV_SEL3, 12, 0),
- MTK_PIN_DRV_GRP(55, DRV_SEL3, 12, 0),
- MTK_PIN_DRV_GRP(56, DRV_SEL3, 12, 0),
- MTK_PIN_DRV_GRP(60, DRV_SEL4, 8, 1),
- MTK_PIN_DRV_GRP(61, DRV_SEL4, 8, 1),
- MTK_PIN_DRV_GRP(62, DRV_SEL4, 8, 1),
- MTK_PIN_DRV_GRP(63, DRV_SEL4, 12, 1),
- MTK_PIN_DRV_GRP(64, DRV_SEL4, 12, 1),
- MTK_PIN_DRV_GRP(65, DRV_SEL4, 12, 1),
- MTK_PIN_DRV_GRP(66, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(67, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(68, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(69, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(70, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(71, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(72, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(73, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(74, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(83, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(84, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(105, MSDC1_CTRL1, 0, 1),
- MTK_PIN_DRV_GRP(106, MSDC1_CTRL0, 0, 1),
- MTK_PIN_DRV_GRP(107, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(108, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(109, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(110, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(111, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(112, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(113, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(114, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(115, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(116, MSDC0_CTRL1, 0, 1),
- MTK_PIN_DRV_GRP(117, MSDC0_CTRL0, 0, 1),
- MTK_PIN_DRV_GRP(118, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(119, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(120, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(121, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(126, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(199, DRV_SEL0, 4, 1),
- MTK_PIN_DRV_GRP(200, DRV_SEL8, 0, 0),
- MTK_PIN_DRV_GRP(201, DRV_SEL8, 0, 0),
- MTK_PIN_DRV_GRP(203, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(204, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(205, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(206, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(207, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(208, DRV_SEL8, 8, 0),
- MTK_PIN_DRV_GRP(209, DRV_SEL8, 8, 0),
- MTK_PIN_DRV_GRP(236, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(237, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(238, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(239, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(240, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(241, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(242, DRV_SEL9, 8, 0),
- MTK_PIN_DRV_GRP(243, DRV_SEL9, 8, 0),
- MTK_PIN_DRV_GRP(257, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(261, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(262, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(263, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(264, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(265, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(266, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(267, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(268, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(269, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(270, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(271, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(272, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(274, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(275, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(276, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(278, DRV_SEL2, 8, 1),
-};
-
-static const struct mtk_pin_spec_pupd_set_samereg mt7623_spec_pupd[] = {
- MTK_PIN_PUPD_SPEC_SR(105, MSDC1_CTRL1, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(106, MSDC1_CTRL0, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(107, MSDC1_CTRL3, 0, 1, 2),
- MTK_PIN_PUPD_SPEC_SR(108, MSDC1_CTRL3, 4, 5, 6),
- MTK_PIN_PUPD_SPEC_SR(109, MSDC1_CTRL3, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(110, MSDC1_CTRL3, 12, 13, 14),
- MTK_PIN_PUPD_SPEC_SR(111, MSDC0_CTRL4, 12, 13, 14),
- MTK_PIN_PUPD_SPEC_SR(112, MSDC0_CTRL4, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(113, MSDC0_CTRL4, 4, 5, 6),
- MTK_PIN_PUPD_SPEC_SR(114, MSDC0_CTRL4, 0, 1, 2),
- MTK_PIN_PUPD_SPEC_SR(115, MSDC0_CTRL5, 0, 1, 2),
- MTK_PIN_PUPD_SPEC_SR(116, MSDC0_CTRL1, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(117, MSDC0_CTRL0, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(118, MSDC0_CTRL3, 12, 13, 14),
- MTK_PIN_PUPD_SPEC_SR(119, MSDC0_CTRL3, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(120, MSDC0_CTRL3, 4, 5, 6),
- MTK_PIN_PUPD_SPEC_SR(121, MSDC0_CTRL3, 0, 1, 2),
-};
-
-static int mt7623_spec_pull_set(struct regmap *regmap, unsigned int pin,
- unsigned char align, bool isup, unsigned int r1r0)
-{
- return mtk_pctrl_spec_pull_set_samereg(regmap, mt7623_spec_pupd,
- ARRAY_SIZE(mt7623_spec_pupd), pin, align, isup, r1r0);
-}
-
-static const struct mtk_pin_ies_smt_set mt7623_ies_set[] = {
- MTK_PIN_IES_SMT_SPEC(0, 6, IES_EN0, 0),
- MTK_PIN_IES_SMT_SPEC(7, 9, IES_EN0, 1),
- MTK_PIN_IES_SMT_SPEC(10, 13, IES_EN0, 2),
- MTK_PIN_IES_SMT_SPEC(14, 15, IES_EN0, 3),
- MTK_PIN_IES_SMT_SPEC(18, 21, IES_EN0, 5),
- MTK_PIN_IES_SMT_SPEC(22, 26, IES_EN0, 6),
- MTK_PIN_IES_SMT_SPEC(27, 29, IES_EN0, 7),
- MTK_PIN_IES_SMT_SPEC(33, 37, IES_EN0, 8),
- MTK_PIN_IES_SMT_SPEC(39, 42, IES_EN0, 9),
- MTK_PIN_IES_SMT_SPEC(43, 45, IES_EN0, 10),
- MTK_PIN_IES_SMT_SPEC(47, 48, IES_EN0, 11),
- MTK_PIN_IES_SMT_SPEC(49, 49, IES_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(53, 56, IES_EN0, 14),
- MTK_PIN_IES_SMT_SPEC(60, 62, IES_EN1, 0),
- MTK_PIN_IES_SMT_SPEC(63, 65, IES_EN1, 1),
- MTK_PIN_IES_SMT_SPEC(66, 71, IES_EN1, 2),
- MTK_PIN_IES_SMT_SPEC(72, 74, IES_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(75, 76, IES_EN1, 3),
- MTK_PIN_IES_SMT_SPEC(83, 84, IES_EN1, 2),
- MTK_PIN_IES_SMT_SPEC(105, 121, MSDC1_CTRL1, 4),
- MTK_PIN_IES_SMT_SPEC(122, 125, IES_EN1, 7),
- MTK_PIN_IES_SMT_SPEC(126, 126, IES_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(199, 201, IES_EN0, 1),
- MTK_PIN_IES_SMT_SPEC(203, 207, IES_EN2, 2),
- MTK_PIN_IES_SMT_SPEC(208, 209, IES_EN2, 3),
- MTK_PIN_IES_SMT_SPEC(236, 241, IES_EN2, 6),
- MTK_PIN_IES_SMT_SPEC(242, 243, IES_EN2, 7),
- MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL2, 4),
- MTK_PIN_IES_SMT_SPEC(262, 272, IES_EN2, 12),
- MTK_PIN_IES_SMT_SPEC(274, 276, IES_EN2, 12),
- MTK_PIN_IES_SMT_SPEC(278, 278, IES_EN2, 13),
-};
-
-static const struct mtk_pin_ies_smt_set mt7623_smt_set[] = {
- MTK_PIN_IES_SMT_SPEC(0, 6, SMT_EN0, 0),
- MTK_PIN_IES_SMT_SPEC(7, 9, SMT_EN0, 1),
- MTK_PIN_IES_SMT_SPEC(10, 13, SMT_EN0, 2),
- MTK_PIN_IES_SMT_SPEC(14, 15, SMT_EN0, 3),
- MTK_PIN_IES_SMT_SPEC(18, 21, SMT_EN0, 5),
- MTK_PIN_IES_SMT_SPEC(22, 26, SMT_EN0, 6),
- MTK_PIN_IES_SMT_SPEC(27, 29, SMT_EN0, 7),
- MTK_PIN_IES_SMT_SPEC(33, 37, SMT_EN0, 8),
- MTK_PIN_IES_SMT_SPEC(39, 42, SMT_EN0, 9),
- MTK_PIN_IES_SMT_SPEC(43, 45, SMT_EN0, 10),
- MTK_PIN_IES_SMT_SPEC(47, 48, SMT_EN0, 11),
- MTK_PIN_IES_SMT_SPEC(49, 49, SMT_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(53, 56, SMT_EN0, 14),
- MTK_PIN_IES_SMT_SPEC(60, 62, SMT_EN1, 0),
- MTK_PIN_IES_SMT_SPEC(63, 65, SMT_EN1, 1),
- MTK_PIN_IES_SMT_SPEC(66, 71, SMT_EN1, 2),
- MTK_PIN_IES_SMT_SPEC(72, 74, SMT_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(75, 76, SMT_EN1, 3),
- MTK_PIN_IES_SMT_SPEC(83, 84, SMT_EN1, 2),
- MTK_PIN_IES_SMT_SPEC(105, 106, MSDC1_CTRL1, 11),
- MTK_PIN_IES_SMT_SPEC(107, 107, MSDC1_CTRL3, 3),
- MTK_PIN_IES_SMT_SPEC(108, 108, MSDC1_CTRL3, 7),
- MTK_PIN_IES_SMT_SPEC(109, 109, MSDC1_CTRL3, 11),
- MTK_PIN_IES_SMT_SPEC(110, 111, MSDC1_CTRL3, 15),
- MTK_PIN_IES_SMT_SPEC(112, 112, MSDC0_CTRL4, 11),
- MTK_PIN_IES_SMT_SPEC(113, 113, MSDC0_CTRL4, 7),
- MTK_PIN_IES_SMT_SPEC(114, 115, MSDC0_CTRL4, 3),
- MTK_PIN_IES_SMT_SPEC(116, 117, MSDC0_CTRL1, 11),
- MTK_PIN_IES_SMT_SPEC(118, 118, MSDC0_CTRL3, 15),
- MTK_PIN_IES_SMT_SPEC(119, 119, MSDC0_CTRL3, 11),
- MTK_PIN_IES_SMT_SPEC(120, 120, MSDC0_CTRL3, 7),
- MTK_PIN_IES_SMT_SPEC(121, 121, MSDC0_CTRL3, 3),
- MTK_PIN_IES_SMT_SPEC(122, 125, SMT_EN1, 7),
- MTK_PIN_IES_SMT_SPEC(126, 126, SMT_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(199, 201, SMT_EN0, 1),
- MTK_PIN_IES_SMT_SPEC(203, 207, SMT_EN2, 2),
- MTK_PIN_IES_SMT_SPEC(208, 209, SMT_EN2, 3),
- MTK_PIN_IES_SMT_SPEC(236, 241, SMT_EN2, 6),
- MTK_PIN_IES_SMT_SPEC(242, 243, SMT_EN2, 7),
- MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL6, 3),
- MTK_PIN_IES_SMT_SPEC(262, 272, SMT_EN2, 12),
- MTK_PIN_IES_SMT_SPEC(274, 276, SMT_EN2, 12),
- MTK_PIN_IES_SMT_SPEC(278, 278, SMT_EN2, 13),
-};
-
-static int mt7623_ies_smt_set(struct regmap *regmap, unsigned int pin,
- unsigned char align, int value, enum pin_config_param arg)
-{
- if (arg == PIN_CONFIG_INPUT_ENABLE)
- return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_ies_set,
- ARRAY_SIZE(mt7623_ies_set), pin, align, value);
- else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
- return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_smt_set,
- ARRAY_SIZE(mt7623_smt_set), pin, align, value);
- return -EINVAL;
-}
-
-static const struct mtk_pinctrl_devdata mt7623_pinctrl_data = {
- .pins = mtk_pins_mt7623,
- .npins = ARRAY_SIZE(mtk_pins_mt7623),
- .grp_desc = mt7623_drv_grp,
- .n_grp_cls = ARRAY_SIZE(mt7623_drv_grp),
- .pin_drv_grp = mt7623_pin_drv,
- .n_pin_drv_grps = ARRAY_SIZE(mt7623_pin_drv),
- .spec_pull_set = mt7623_spec_pull_set,
- .spec_ies_smt_set = mt7623_ies_smt_set,
- .dir_offset = 0x0000,
- .pullen_offset = 0x0150,
- .pullsel_offset = 0x0280,
- .dout_offset = 0x0500,
- .din_offset = 0x0630,
- .pinmux_offset = 0x0760,
- .type1_start = 280,
- .type1_end = 280,
- .port_shf = 4,
- .port_mask = 0x1f,
- .port_align = 4,
- .eint_offsets = {
- .name = "mt7623_eint",
- .stat = 0x000,
- .ack = 0x040,
- .mask = 0x080,
- .mask_set = 0x0c0,
- .mask_clr = 0x100,
- .sens = 0x140,
- .sens_set = 0x180,
- .sens_clr = 0x1c0,
- .soft = 0x200,
- .soft_set = 0x240,
- .soft_clr = 0x280,
- .pol = 0x300,
- .pol_set = 0x340,
- .pol_clr = 0x380,
- .dom_en = 0x400,
- .dbnc_ctrl = 0x500,
- .dbnc_set = 0x600,
- .dbnc_clr = 0x700,
- .port_mask = 6,
- .ports = 6,
- },
- .ap_num = 169,
- .db_cnt = 16,
-};
-
-static int mt7623_pinctrl_probe(struct platform_device *pdev)
-{
- return mtk_pctrl_init(pdev, &mt7623_pinctrl_data, NULL);
-}
-
-static const struct of_device_id mt7623_pctrl_match[] = {
- { .compatible = "mediatek,mt7623-pinctrl", },
- {}
-};
-MODULE_DEVICE_TABLE(of, mt7623_pctrl_match);
-
-static struct platform_driver mtk_pinctrl_driver = {
- .probe = mt7623_pinctrl_probe,
- .driver = {
- .name = "mediatek-mt7623-pinctrl",
- .of_match_table = mt7623_pctrl_match,
- },
-};
-
-static int __init mtk_pinctrl_init(void)
-{
- return platform_driver_register(&mtk_pinctrl_driver);
-}
-
-arch_initcall(mtk_pinctrl_init);
--- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h
+++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
@@ -185,6 +185,12 @@
#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
+#define MT7623_PIN_57_SDA1_FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define MT7623_PIN_57_SDA1_FUNC_SDA1 (MTK_PIN_NO(57) | 1)
+
+#define MT7623_PIN_58_SCL1_FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define MT7623_PIN_58_SCL1_FUNC_SCL1 (MTK_PIN_NO(58) | 1)
+
#define MT7623_PIN_60_WB_RSTB_FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
#define MT7623_PIN_60_WB_RSTB_FUNC_WB_RSTB (MTK_PIN_NO(60) | 1)
@@ -244,6 +250,22 @@
#define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
#define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1)
+#define MT7623_PIN_79_URXD0_FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define MT7623_PIN_79_URXD0_FUNC_URXD0 (MTK_PIN_NO(79) | 1)
+#define MT7623_PIN_79_URXD0_FUNC_UTXD0 (MTK_PIN_NO(79) | 2)
+
+#define MT7623_PIN_80_UTXD0_FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define MT7623_PIN_80_UTXD0_FUNC_UTXD0 (MTK_PIN_NO(80) | 1)
+#define MT7623_PIN_80_UTXD0_FUNC_URXD0 (MTK_PIN_NO(80) | 2)
+
+#define MT7623_PIN_81_URXD1_FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define MT7623_PIN_81_URXD1_FUNC_URXD1 (MTK_PIN_NO(81) | 1)
+#define MT7623_PIN_81_URXD1_FUNC_UTXD1 (MTK_PIN_NO(81) | 2)
+
+#define MT7623_PIN_82_UTXD1_FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define MT7623_PIN_82_UTXD1_FUNC_UTXD1 (MTK_PIN_NO(82) | 1)
+#define MT7623_PIN_82_UTXD1_FUNC_URXD1 (MTK_PIN_NO(82) | 2)
+
#define MT7623_PIN_83_LCM_RST_FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
#define MT7623_PIN_83_LCM_RST_FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
@@ -351,10 +373,10 @@
#define MT7623_PIN_122_GPIO122_FUNC_SDA2 (MTK_PIN_NO(122) | 4)
#define MT7623_PIN_122_GPIO122_FUNC_URXD0 (MTK_PIN_NO(122) | 5)
-#define MT7623_PIN_123_GPIO123_FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
-#define MT7623_PIN_123_GPIO123_FUNC_TEST (MTK_PIN_NO(123) | 1)
-#define MT7623_PIN_123_GPIO123_FUNC_SCL2 (MTK_PIN_NO(123) | 4)
-#define MT7623_PIN_123_GPIO123_FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
+#define MT7623_PIN_123_HTPLG_FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT7623_PIN_123_HTPLG_FUNC_HTPLG (MTK_PIN_NO(123) | 1)
+#define MT7623_PIN_123_HTPLG_FUNC_SCL2 (MTK_PIN_NO(123) | 4)
+#define MT7623_PIN_123_HTPLG_FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
#define MT7623_PIN_124_GPIO124_FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
#define MT7623_PIN_124_GPIO124_FUNC_TEST (MTK_PIN_NO(124) | 1)

531
target/linux/mediatek/patches-4.9/0059-eth-fixes.patch Normal file
View File

@@ -0,0 +1,531 @@
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -24,6 +24,7 @@
#include <linux/tcp.h>
#if defined(CONFIG_NET_MEDIATEK_HW_QOS)
+
struct mtk_ioctl_reg {
unsigned int off;
unsigned int val;
@@ -32,6 +33,13 @@ struct mtk_ioctl_reg {
#define REG_HQOS_MAX 0x3FFF
#define RAETH_QDMA_REG_READ 0x89F8
#define RAETH_QDMA_REG_WRITE 0x89F9
+#define RAETH_QDMA_QUEUE_MAPPING 0x89FA
+
+unsigned int M2Q_table[16] = {0};
+unsigned int lan_wan_separate = 0;
+
+EXPORT_SYMBOL_GPL(M2Q_table);
+
#endif
#if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE)
@@ -225,7 +233,7 @@ static void mtk_phy_link_adjust(struct n
if (flowctrl & FLOW_CTRL_RX)
mcr |= MAC_MCR_FORCE_RX_FC;
- netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
+ netif_info(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
}
@@ -508,9 +516,9 @@ static struct rtnl_link_stats64 * mtk_ge
unsigned int start;
if (netif_running(dev) && netif_device_present(dev)) {
- if (spin_trylock_bh(&hw_stats->stats_lock)) {
+ if (spin_trylock(&hw_stats->stats_lock)) {
mtk_stats_update_mac(mac);
- spin_unlock_bh(&hw_stats->stats_lock);
+ spin_unlock(&hw_stats->stats_lock);
}
}
@@ -690,6 +698,7 @@ static int mtk_tx_map(struct sk_buff *sk
txd3 |= skb->mark & 0x7;
if (mac->id)
txd3 += 8;
+ txd3 = 0;
#endif
mapped_addr = dma_map_single(eth->dev, skb->data,
@@ -760,16 +769,7 @@ static int mtk_tx_map(struct sk_buff *sk
WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
(!nr_frags * TX_DMA_LS0)));
- /* we have a single DMA ring so BQL needs to be updated for all devices
- * sitting on this ring
- */
- for (i = 0; i < MTK_MAC_COUNT; i++) {
- if (!eth->netdev[i])
- continue;
-
- netdev_sent_queue(eth->netdev[i], skb->len);
- }
-
+ netdev_sent_queue(dev, skb->len);
skb_tx_timestamp(skb);
ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
@@ -980,20 +980,9 @@ static int mtk_poll_rx(struct napi_struc
if (!(trxd.rxd2 & RX_DMA_DONE))
break;
- /* find out which mac the packet comes from. If the special tag is
- * we can assume that the traffic is coming from the builtin mt7530
- * and the DSA driver has loaded. FPORT will be the physical switch
- * port in this case rather than the FE forward port id. */
- if (!(trxd.rxd4 & RX_DMA_SP_TAG)) {
- /* values start at 1 */
- mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
- RX_DMA_FPORT_MASK;
- mac--;
- }
-
- if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
- !eth->netdev[mac]))
- goto release_desc;
+ /* find out which mac the packet come from. values start at 1 */
+ mac = (trxd.rxd4 >> 22) & 0x1;
+ mac = (mac + 1) % 2;
netdev = eth->netdev[mac];
@@ -1017,6 +1006,9 @@ static int mtk_poll_rx(struct napi_struc
}
/* receive data */
+ if (mac < 0 || mac > 2)
+ mac = 0;
+
skb = build_skb(data, ring->frag_size);
if (unlikely(!skb)) {
skb_free_frag(new_data);
@@ -1076,18 +1068,21 @@ static int mtk_poll_tx(struct mtk_eth *e
struct mtk_tx_dma *desc;
struct sk_buff *skb;
struct mtk_tx_buf *tx_buf;
- int total = 0, done = 0;
- unsigned int bytes = 0;
+ unsigned int done[MTK_MAX_DEVS];
+ unsigned int bytes[MTK_MAX_DEVS];
u32 cpu, dma;
static int condition;
- int i;
+ int total = 0, i;
+
+ memset(done, 0, sizeof(done));
+ memset(bytes, 0, sizeof(bytes));
cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
desc = mtk_qdma_phys_to_virt(ring, cpu);
- while ((cpu != dma) && done < budget) {
+ while ((cpu != dma) && budget) {
u32 next_cpu = desc->txd2;
int mac = 0;
@@ -1106,8 +1101,9 @@ static int mtk_poll_tx(struct mtk_eth *e
}
if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
- bytes += skb->len;
- done++;
+ bytes[mac] += skb->len;
+ done[mac]++;
+ budget--;
}
mtk_tx_unmap(eth, tx_buf);
@@ -1119,13 +1115,11 @@ static int mtk_poll_tx(struct mtk_eth *e
mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
- /* we have a single DMA ring so BQL needs to be updated for all devices
- * sitting on this ring
- */
for (i = 0; i < MTK_MAC_COUNT; i++) {
- if (!eth->netdev[i])
+ if (!eth->netdev[i] || !done[i])
continue;
- netdev_completed_queue(eth->netdev[i], done, bytes);
+ netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
+ total += done[i];
}
if (mtk_queue_stopped(eth) &&
@@ -1286,21 +1280,11 @@ static void mtk_tx_clean(struct mtk_eth
static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
{
- struct mtk_rx_ring *ring;
+ struct mtk_rx_ring *ring = &eth->rx_ring[ring_no];
int rx_data_len, rx_dma_size;
int i;
- u32 offset = 0;
-
- if (rx_flag & MTK_RX_FLAGS_QDMA) {
- if (ring_no)
- return -EINVAL;
- ring = &eth->rx_ring_qdma;
- offset = 0x1000;
- } else {
- ring = &eth->rx_ring[ring_no];
- }
- if (rx_flag & MTK_RX_FLAGS_HWLRO) {
+ if (rx_flag == MTK_RX_FLAGS_HWLRO) {
rx_data_len = MTK_MAX_LRO_RX_LENGTH;
rx_dma_size = MTK_HW_LRO_DMA_SIZE;
} else {
@@ -1348,16 +1332,104 @@ static int mtk_rx_alloc(struct mtk_eth *
*/
wmb();
- mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
- mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
- mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
- mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
+ mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no));
+ mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no));
+ mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
+ mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX);
return 0;
}
-static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
+static int mtk_rx_alloc_qdma(struct mtk_eth *eth, int rx_flag)
{
+ struct mtk_rx_ring *ring = &eth->rx_ring_qdma;
+ int rx_data_len, rx_dma_size;
+ int i;
+
+ rx_data_len = ETH_DATA_LEN;
+ rx_dma_size = MTK_DMA_SIZE;
+
+ ring->frag_size = mtk_max_frag_size(rx_data_len);
+ ring->buf_size = mtk_max_buf_size(ring->frag_size);
+ ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
+ GFP_KERNEL);
+ if (!ring->data)
+ return -ENOMEM;
+
+ for (i = 0; i < rx_dma_size; i++) {
+ ring->data[i] = netdev_alloc_frag(ring->frag_size);
+ if (!ring->data[i])
+ return -ENOMEM;
+ }
+
+ ring->dma = dma_alloc_coherent(eth->dev,
+ rx_dma_size * sizeof(*ring->dma),
+ &ring->phys,
+ GFP_ATOMIC | __GFP_ZERO);
+ if (!ring->dma)
+ return -ENOMEM;
+
+ for (i = 0; i < rx_dma_size; i++) {
+ dma_addr_t dma_addr = dma_map_single(eth->dev,
+ ring->data[i] + NET_SKB_PAD,
+ ring->buf_size,
+ DMA_FROM_DEVICE);
+ if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
+ return -ENOMEM;
+ ring->dma[i].rxd1 = (unsigned int)dma_addr;
+
+ ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
+ }
+ ring->dma_size = rx_dma_size;
+ ring->calc_idx_update = false;
+ ring->calc_idx = rx_dma_size - 1;
+ ring->crx_idx_reg = MTK_QRX_CRX_IDX_CFG(0);
+ /* make sure that all changes to the dma ring are flushed before we
+ * continue
+ */
+ wmb();
+
+ mtk_w32(eth, ring->phys, MTK_QRX_BASE_PTR_CFG(0));
+ mtk_w32(eth, rx_dma_size, MTK_QRX_MAX_CNT_CFG(0));
+ mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
+ mtk_w32(eth, MTK_PST_DRX_IDX_CFG(0), MTK_QDMA_RST_IDX);
+
+ return 0;
+}
+
+static void mtk_rx_clean(struct mtk_eth *eth, int ring_no)
+{
+ struct mtk_rx_ring *ring = &eth->rx_ring[ring_no];
+ int i;
+
+ if (ring->data && ring->dma) {
+ for (i = 0; i < ring->dma_size; i++) {
+ if (!ring->data[i])
+ continue;
+ if (!ring->dma[i].rxd1)
+ continue;
+ dma_unmap_single(eth->dev,
+ ring->dma[i].rxd1,
+ ring->buf_size,
+ DMA_FROM_DEVICE);
+ skb_free_frag(ring->data[i]);
+ }
+ kfree(ring->data);
+ ring->data = NULL;
+ }
+
+ if (ring->dma) {
+ dma_free_coherent(eth->dev,
+ ring->dma_size * sizeof(*ring->dma),
+ ring->dma,
+ ring->phys);
+ ring->dma = NULL;
+ }
+}
+
+static void mtk_rx_clean_qdma(struct mtk_eth *eth)
+{
+ struct mtk_rx_ring *ring = &eth->rx_ring_qdma;
int i;
if (ring->data && ring->dma) {
@@ -1683,7 +1755,7 @@ static int mtk_dma_init(struct mtk_eth *
if (err)
return err;
- err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
+ err = mtk_rx_alloc_qdma(eth, MTK_RX_FLAGS_NORMAL);
if (err)
return err;
@@ -1702,6 +1774,7 @@ static int mtk_dma_init(struct mtk_eth *
return err;
}
+
/* Enable random early drop and set drop threshold automatically */
mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
MTK_QDMA_FC_THRES);
@@ -1726,13 +1799,13 @@ static void mtk_dma_free(struct mtk_eth
eth->phy_scratch_ring = 0;
}
mtk_tx_clean(eth);
- mtk_rx_clean(eth, &eth->rx_ring[0]);
- mtk_rx_clean(eth, &eth->rx_ring_qdma);
+ mtk_rx_clean(eth, 0);
+ mtk_rx_clean_qdma(eth);
if (eth->hwlro) {
mtk_hwlro_rx_uninit(eth);
for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
- mtk_rx_clean(eth, &eth->rx_ring[i]);
+ mtk_rx_clean(eth, i);
}
kfree(eth->scratch_head);
@@ -1947,20 +2020,14 @@ static int mtk_hw_init(struct mtk_eth *e
val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
- /* Indicates CDM to parse the MTK special tag from CPU
- * which also is working out for untag packets.
- */
- val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
- mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
- val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
- mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
-
/* Enable RX VLan Offloading */
if (MTK_HW_FEATURES & NETIF_F_HW_VLAN_CTAG_RX)
mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
else
mtk_w32(eth, 0, MTK_CDMP_EG_CTRL);
+ mtk_w32(eth, 0x81000001, MTK_CDMP_IG_CTRL);
+
/* disable delay and normal interrupt */
#ifdef MTK_IRQ_DLY
mtk_w32(eth, 0x84048404, MTK_PDMA_DELAY_INT);
@@ -1990,6 +2057,9 @@ static int mtk_hw_init(struct mtk_eth *e
/* Enable RX checksum */
val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
+ if (!i)
+ val |= BIT(24);
+
/* setup the mac dma */
mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
}
@@ -2069,7 +2139,18 @@ static int mtk_do_ioctl(struct net_devic
if (reg.off > REG_HQOS_MAX)
return -EINVAL;
mtk_w32(eth, reg.val, 0x1800 + reg.off);
-// printk("write reg off:%x val:%x\n", reg.off, reg.val);
+ printk("write reg off:%x val:%x\n", reg.off, reg.val);
+ return 0;
+
+ case RAETH_QDMA_QUEUE_MAPPING:
+ copy_from_user(&reg, ifr->ifr_data, sizeof(reg));
+ if ((reg.off & 0x100) == 0x100) {
+ lan_wan_separate = 1;
+ reg.off &= 0xff;
+ } else {
+ lan_wan_separate = 0;
+ }
+ M2Q_table[reg.off] = reg.val;
return 0;
#endif
case SIOCGMIIPHY:
@@ -2288,9 +2369,9 @@ static void mtk_get_ethtool_stats(struct
return;
if (netif_running(dev) && netif_device_present(dev)) {
- if (spin_trylock_bh(&hwstats->stats_lock)) {
+ if (spin_trylock(&hwstats->stats_lock)) {
mtk_stats_update_mac(mac);
- spin_unlock_bh(&hwstats->stats_lock);
+ spin_unlock(&hwstats->stats_lock);
}
}
@@ -2443,7 +2524,7 @@ static int mtk_add_mac(struct mtk_eth *e
mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
SET_NETDEV_DEV(eth->netdev[id], eth->dev);
- eth->netdev[id]->watchdog_timeo = 30 * HZ;
+ eth->netdev[id]->watchdog_timeo = 15 * HZ;
eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
eth->netdev[id]->base_addr = (unsigned long)eth->base;
@@ -2584,15 +2665,19 @@ static int mtk_probe(struct platform_dev
goto err_deinit_hw;
}
+ cpumask_set_cpu(1, &eth->affinity_mask[1]);
+ cpumask_set_cpu(0, &eth->affinity_mask[2]);
err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
dev_name(eth->dev), eth);
if (err)
goto err_free_dev;
+ irq_set_affinity_hint(eth->irq[1], &eth->affinity_mask[1]);
err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
dev_name(eth->dev), eth);
if (err)
goto err_free_dev;
+ irq_set_affinity_hint(eth->irq[2], &eth->affinity_mask[2]);
err = mtk_mdio_init(eth);
if (err)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -80,7 +80,6 @@
/* CDMP Ingress Control Register */
#define MTK_CDMP_IG_CTRL 0x400
-#define MTK_CDMP_STAG_EN BIT(0)
/* CDMP Exgress Control Register */
#define MTK_CDMP_EG_CTRL 0x404
@@ -91,12 +90,27 @@
#define MTK_GDMA_TCS_EN BIT(21)
#define MTK_GDMA_UCS_EN BIT(20)
+/* GDMA Ingress Control Register */
+#define MTK_GDMA1_IG_CTRL(x) (0x500 + (x * 0x1000))
+
/* Unicast Filter MAC Address Register - Low */
#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
/* Unicast Filter MAC Address Register - High */
#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
+/* QDMA RX Base Pointer Register */
+#define MTK_QRX_BASE_PTR0 0x1900
+#define MTK_QRX_BASE_PTR_CFG(x) (MTK_QRX_BASE_PTR0 + (x * 0x10))
+
+/* QDMA RX Maximum Count Register */
+#define MTK_QRX_MAX_CNT0 0x1904
+#define MTK_QRX_MAX_CNT_CFG(x) (MTK_QRX_MAX_CNT0 + (x * 0x10))
+
+/* QDMA RX CPU Pointer Register */
+#define MTK_QRX_CRX_IDX0 0x1908
+#define MTK_QRX_CRX_IDX_CFG(x) (MTK_QRX_CRX_IDX0 + (x * 0x10))
+
/* PDMA RX Base Pointer Register */
#define MTK_PRX_BASE_PTR0 0x900
#define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))
@@ -240,7 +254,10 @@
#define MTK_QDMA_INT_MASK 0x1A1C
/* QDMA Interrupt Mask Register */
+#define MTK_QDMA_HRED1 0x1A40
#define MTK_QDMA_HRED2 0x1A44
+#define MTK_QDMA_SRED1 0x1A48
+#define MTK_QDMA_SRED2 0x1A4c
/* QDMA TX Forward CPU Pointer Register */
#define MTK_QTX_CTX_PTR 0x1B00
@@ -275,6 +292,7 @@
#define TX_DMA_TSO BIT(28)
#define TX_DMA_FPORT_SHIFT 25
#define TX_DMA_FPORT_MASK 0x7
+#define TX_DMA_VQID0 BIT(17)
#define TX_DMA_INS_VLAN BIT(16)
/* QDMA descriptor txd3 */
@@ -294,7 +312,6 @@
/* QDMA descriptor rxd4 */
#define RX_DMA_L4_VALID BIT(24)
-#define RX_DMA_SP_TAG BIT(22)
#define RX_DMA_FPORT_SHIFT 19
#define RX_DMA_FPORT_MASK 0x7
@@ -310,6 +327,7 @@
/* Mac control registers */
#define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
+#define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
#define MAC_MCR_MAX_RX_1536 BIT(24)
#define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
#define MAC_MCR_FORCE_MODE BIT(15)
@@ -495,7 +513,6 @@ struct mtk_tx_ring {
enum mtk_rx_flags {
MTK_RX_FLAGS_NORMAL = 0,
MTK_RX_FLAGS_HWLRO,
- MTK_RX_FLAGS_QDMA,
};
/* struct mtk_rx_ring - This struct holds info describing a RX ring
@@ -539,9 +556,9 @@ struct mtk_rx_ring {
* @pctl: The register map pointing at the range used to setup
* GMAC port drive/slew values
* @dma_refcnt: track how many netdevs are using the DMA engine
- * @tx_ring: Pointer to the memory holding info about the TX ring
- * @rx_ring: Pointer to the memory holding info about the RX ring
- * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring
+ * @tx_ring: Pointer to the memore holding info about the TX ring
+ * @rx_ring: Pointer to the memore holding info about the RX ring
+ * @rx_ring_qdma: Pointer to the memore holding info about the RX ring (QDMA)
* @tx_napi: The TX NAPI struct
* @rx_napi: The RX NAPI struct
* @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
@@ -563,6 +580,7 @@ struct mtk_eth {
struct net_device *netdev[MTK_MAX_DEVS];
struct mtk_mac *mac[MTK_MAX_DEVS];
int irq[3];
+ cpumask_t affinity_mask[3];
u32 msg_enable;
unsigned long sysclk;
struct regmap *ethsys;
@@ -615,4 +633,6 @@ void mtk_stats_update_mac(struct mtk_mac
void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
+extern unsigned int M2Q_table[16];
+
#endif /* MTK_ETH_H */

41
target/linux/mediatek/patches-4.9/0083-mfd-led3.patch
View File

@@ -1,41 +0,0 @@
From patchwork Fri Feb 24 18:47:21 2017
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v4,4/4] mfd: mt6397: Add MT6323 LED support into MT6397 driver
From: sean.wang@mediatek.com
X-Patchwork-Id: 9591021
Message-Id: <1487962041-6548-5-git-send-email-sean.wang@mediatek.com>
To: <rpurdie@rpsys.net>, <jacek.anaszewski@gmail.com>, <lee.jones@linaro.org>,
<matthias.bgg@gmail.com>, <pavel@ucw.cz>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, keyhaede@gmail.com,
Sean Wang <sean.wang@mediatek.com>, linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org, linux-leds@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Date: Sat, 25 Feb 2017 02:47:21 +0800
From: Sean Wang <sean.wang@mediatek.com>
Add compatible string as "mt6323-led" that will make
the OF core spawn child devices for the LED subnode
of that MT6323 MFD device.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
drivers/mfd/mt6397-core.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -48,6 +48,10 @@ static const struct mfd_cell mt6323_devs
.name = "mt6323-regulator",
.of_compatible = "mediatek,mt6323-regulator"
},
+ {
+ .name = "mt6323-led",
+ .of_compatible = "mediatek,mt6323-led"
+ },
};
static const struct mfd_cell mt6397_devs[] = {

38
target/linux/mediatek/patches-4.9/0086-pmic-led1.patch
View File

@@ -1,38 +0,0 @@
From patchwork Mon Mar 20 06:47:25 2017
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v6,
2/4] dt-bindings: mfd: Add the description for LED as the sub module
From: sean.wang@mediatek.com
X-Patchwork-Id: 9633089
Message-Id: <1489992447-13007-3-git-send-email-sean.wang@mediatek.com>
To: <rpurdie@rpsys.net>, <jacek.anaszewski@gmail.com>, <lee.jones@linaro.org>,
<matthias.bgg@gmail.com>, <pavel@ucw.cz>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, keyhaede@gmail.com,
Sean Wang <sean.wang@mediatek.com>, linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org, linux-leds@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Date: Mon, 20 Mar 2017 14:47:25 +0800
From: Sean Wang <sean.wang@mediatek.com>
This patch adds description for LED as the sub-module on MT6397/MT6323
multifunction device.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
Documentation/devicetree/bindings/mfd/mt6397.txt | 1 +
1 file changed, 1 insertion(+)
--- a/Documentation/devicetree/bindings/mfd/mt6397.txt
+++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
@@ -6,6 +6,7 @@ MT6397/MT6323 is a multifunction device
- Audio codec
- GPIO
- Clock
+- LED
It is interfaced to host controller using SPI interface by a proprietary hardware
called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap.

42
target/linux/mediatek/patches-4.9/0088-pmic-led3.patch
View File

@@ -1,42 +0,0 @@
From patchwork Mon Mar 20 06:47:27 2017
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v6,
4/4] mfd: mt6397: Align the placement at which the mfd_cell of LED is
defined
From: sean.wang@mediatek.com
X-Patchwork-Id: 9633079
Message-Id: <1489992447-13007-5-git-send-email-sean.wang@mediatek.com>
To: <rpurdie@rpsys.net>, <jacek.anaszewski@gmail.com>, <lee.jones@linaro.org>,
<matthias.bgg@gmail.com>, <pavel@ucw.cz>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, keyhaede@gmail.com,
Sean Wang <sean.wang@mediatek.com>, linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org, linux-leds@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Date: Mon, 20 Mar 2017 14:47:27 +0800
From: Sean Wang <sean.wang@mediatek.com>
Align the placement as which the mfd_cell of LED is defined as the other
members done on the structure.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
---
drivers/mfd/mt6397-core.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -47,8 +47,7 @@ static const struct mfd_cell mt6323_devs
{
.name = "mt6323-regulator",
.of_compatible = "mediatek,mt6323-regulator"
- },
- {
+ }, {
.name = "mt6323-led",
.of_compatible = "mediatek,mt6323-led"
},

44
target/linux/mediatek/patches-4.9/0092-dsa4.patch
View File

@@ -1,44 +0,0 @@
From patchwork Wed Mar 29 09:38:22 2017
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [net-next, v3,
4/5] net-next: ethernet: mediatek: add device_node of GMAC pointing
into the netdev instance
From: sean.wang@mediatek.com
X-Patchwork-Id: 9651097
Message-Id: <1490780303-18598-5-git-send-email-sean.wang@mediatek.com>
To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, Landen.Chao@mediatek.com, keyhaede@gmail.com,
netdev@vger.kernel.org, sean.wang@mediatek.com,
linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org, objelf@gmail.com, davem@davemloft.net
Date: Wed, 29 Mar 2017 17:38:22 +0800
From: Sean Wang <sean.wang@mediatek.com>
the patch adds the setup of the corresponding device node of GMAC into the
netdev instance which could allow other modules such as DSA to find the
instance through the node in dt-bindings using of_find_net_device_by_node()
call.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -2333,6 +2333,8 @@ static int mtk_add_mac(struct mtk_eth *e
eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
eth->netdev[id]->irq = eth->irq[0];
+ eth->netdev[id]->dev.of_node = np;
+
return 0;
free_netdev:

36
target/linux/mediatek/patches-4.9/0094-net-affinity.patch
View File

@@ -1,36 +0,0 @@
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -2459,15 +2459,23 @@ static int mtk_probe(struct platform_dev
goto err_deinit_hw;
}
+ for (i = 0; i < 3; i++) {
+ int cpu = i % num_online_cpus();
+
+ cpumask_set_cpu(cpu, &eth->affinity_mask[i]);
+ }
+
err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
dev_name(eth->dev), eth);
if (err)
goto err_free_dev;
+ irq_set_affinity_hint(eth->irq[1], &eth->affinity_mask[1]);
err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
dev_name(eth->dev), eth);
if (err)
goto err_free_dev;
+ irq_set_affinity_hint(eth->irq[2], &eth->affinity_mask[2]);
err = mtk_mdio_init(eth);
if (err)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -539,6 +539,7 @@ struct mtk_eth {
struct net_device *netdev[MTK_MAX_DEVS];
struct mtk_mac *mac[MTK_MAX_DEVS];
int irq[3];
+ cpumask_t affinity_mask[3];
u32 msg_enable;
unsigned long sysclk;
struct regmap *ethsys;

12
target/linux/mediatek/patches-4.9/0200-devicetree.patch
View File

@@ -1,12 +0,0 @@
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -950,6 +950,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt6589-aquaris5.dtb \
mt6592-evb.dtb \
mt7623-evb.dtb \
+ mt7623-eMMC.dtb \
+ mt7623-NAND.dtb \
+ mt7623-NAND-ePHY.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb

32
target/linux/mediatek/patches-4.9/0201-block2mtd.patch
View File

@@ -1,32 +0,0 @@
--- a/drivers/mtd/devices/block2mtd.c
+++ b/drivers/mtd/devices/block2mtd.c
@@ -32,6 +32,8 @@
#include <linux/slab.h>
#include <linux/major.h>
+static const char * const block2mtd_probe_types[] = { "cmdlinepart", NULL };
+
/* Info for the block device */
struct block2mtd_dev {
struct list_head list;
@@ -227,6 +229,7 @@ static struct block2mtd_dev *add_device(
#endif
const fmode_t mode = FMODE_READ | FMODE_WRITE | FMODE_EXCL;
struct block_device *bdev = ERR_PTR(-ENODEV);
+ struct mtd_part_parser_data ppdata = { 0 };
struct block2mtd_dev *dev;
struct mtd_partition *part;
char *name;
@@ -307,11 +310,7 @@ static struct block2mtd_dev *add_device(
dev->mtd.priv = dev;
dev->mtd.owner = THIS_MODULE;
- part = kzalloc(sizeof(struct mtd_partition), GFP_KERNEL);
- part->name = name;
- part->offset = 0;
- part->size = dev->mtd.size;
- if (mtd_device_register(&dev->mtd, part, 1)) {
+ if (mtd_device_parse_register(&dev->mtd, block2mtd_probe_types, &ppdata, NULL, 0)) {
/* Device didn't get added, so free the entry */
goto err_destroy_mutex;
}