ramips: remove device tree legacy compatibility
We switched to 5.15 kernel, so we don't need to maintain 5.10 compatibility anymore. Signed-off-by: Nick Hainke <vincent@systemli.org>
This commit is contained in:
Nick Hainke
committed by
Christian Marangi
Christian Marangi
parent
047361dee4
commit
1fda304d8e
@@ -41,15 +41,6 @@
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bootargs = "console=ttyS0,57600";
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};
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#ifdef DTS_LEGACY
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pll: pll {
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compatible = "mediatek,mt7621-pll", "syscon";
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#clock-cells = <1>;
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clock-output-names = "cpu", "bus";
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};
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#endif
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sysclock: sysclock {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@@ -67,16 +58,12 @@
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#size-cells = <1>;
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sysc: syscon@0 {
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#ifdef DTS_LEGACY
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compatible = "mtk,mt7621-sysc", "syscon";
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#else
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compatible = "mediatek,mt7621-sysc", "syscon";
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#clock-cells = <1>;
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ralink,memctl = <&memc>;
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clock-output-names = "xtal", "cpu", "bus",
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"50m", "125m", "150m",
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"250m", "270m";
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#endif
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reg = <0x0 0x100>;
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};
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@@ -149,11 +136,7 @@
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};
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memc: syscon@5000 {
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#ifdef DTS_LEGACY
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compatible = "mtk,mt7621-memc", "syscon";
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#else
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compatible = "mediatek,mt7621-memc", "syscon";
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#endif
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reg = <0x5000 0x1000>;
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};
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@@ -213,11 +196,7 @@
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compatible = "ralink,mt7621-spi";
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reg = <0xb00 0x100>;
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#ifdef DTS_LEGACY
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clocks = <&pll MT7621_CLK_BUS>;
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#else
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clocks = <&sysc MT7621_CLK_BUS>;
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#endif
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resets = <&rstctrl 18>;
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reset-names = "spi";
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@@ -425,11 +404,7 @@
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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#ifdef DTS_LEGACY
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clocks = <&pll MT7621_CLK_CPU>;
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#else
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clocks = <&sysc MT7621_CLK_CPU>;
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#endif
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};
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};
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@@ -466,14 +441,9 @@
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compatible = "mediatek,mt7621-eth";
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reg = <0x1e100000 0x10000>;
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#ifdef DTS_LEGACY
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clocks = <&sysclock>;
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clock-names = "ethif";
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#else
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clocks = <&sysc MT7621_CLK_FE>,
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<&sysc MT7621_CLK_ETH>;
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clock-names = "fe", "ethif";
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#endif
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -586,36 +556,16 @@
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device_type = "pci";
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#ifdef DTS_LEGACY
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ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */
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<0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
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#else
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ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
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<0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
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#endif
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status = "disabled";
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#ifdef DTS_LEGACY
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
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GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
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GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>;
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reset-names = "pcie0", "pcie1", "pcie2";
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clocks = <&clkctrl 24>, <&clkctrl 25>, <&clkctrl 26>;
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clock-names = "pcie0", "pcie1", "pcie2";
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phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
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phy-names = "pcie-phy0", "pcie-phy2";
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#else
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xF800 0 0 0>;
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interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
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<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
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<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
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#endif
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reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
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@@ -625,7 +575,6 @@
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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#ifndef DTS_LEGACY
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
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@@ -633,7 +582,6 @@
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clocks = <&sysc MT7621_CLK_PCIE0>;
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phys = <&pcie0_phy 1>;
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phy-names = "pcie-phy0";
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#endif
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};
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pcie1: pcie@1,0 {
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@@ -642,7 +590,6 @@
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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#ifndef DTS_LEGACY
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
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@@ -650,7 +597,6 @@
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clocks = <&sysc MT7621_CLK_PCIE1>;
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phys = <&pcie0_phy 1>;
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phy-names = "pcie-phy1";
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#endif
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};
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pcie2: pcie@2,0 {
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@@ -659,7 +605,6 @@
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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#ifndef DTS_LEGACY
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
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@@ -667,25 +612,20 @@
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clocks = <&sysc MT7621_CLK_PCIE2>;
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phys = <&pcie2_phy 0>;
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phy-names = "pcie-phy2";
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#endif
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};
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};
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pcie0_phy: pcie-phy@1e149000 {
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compatible = "mediatek,mt7621-pci-phy";
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reg = <0x1e149000 0x0700>;
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#ifndef DTS_LEGACY
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clocks = <&sysc MT7621_CLK_XTAL>;
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#endif
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#phy-cells = <1>;
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};
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pcie2_phy: pcie-phy@1e14a000 {
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compatible = "mediatek,mt7621-pci-phy";
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reg = <0x1e14a000 0x0700>;
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#ifndef DTS_LEGACY
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clocks = <&sysc MT7621_CLK_XTAL>;
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#endif
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#phy-cells = <1>;
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};
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};
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@@ -9,10 +9,6 @@ DEFAULT_SOC := mt7621
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DEVICE_VARS += ELECOM_HWNAME LINKSYS_HWNAME DLINK_HWID
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ifdef CONFIG_LINUX_5_10
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DTS_CPPFLAGS += -DDTS_LEGACY
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endif
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define Build/arcadyan-trx
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echo -ne "hsqs" > $@.hsqs
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$(eval trx_magic=$(word 1,$(1)))
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