realtek: update the tree to the latest refactored version
* rename the target to realtek * add refactored DSA driver * add latest gpio driver * lots of arch cleanups * new irq driver * additional boards Signed-off-by: Bert Vermeulen <bert@biot.com> Signed-off-by: Birger Koblitz <mail@birger-koblitz.de> Signed-off-by: Sander Vanheule <sander@svanheule.net> Signed-off-by: Bjørn Mork <bjorn@mork.no> Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin
@@ -0,0 +1,34 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef RTL838X_IOREMAP_H_
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#define RTL838X_IOREMAP_H_
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
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{
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return phys_addr;
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}
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static inline int is_rtl838x_internal_registers(phys_addr_t offset)
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{
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/* IO-Block */
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if (offset >= 0xb8000000 && offset < 0xb9000000)
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return 1;
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/* Switch block */
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if (offset >= 0xbb000000 && offset < 0xbc000000)
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return 1;
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return 0;
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}
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static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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if (is_rtl838x_internal_registers(offset))
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return (void __iomem *)offset;
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return NULL;
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}
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static inline int plat_iounmap(const volatile void __iomem *addr)
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{
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return is_rtl838x_internal_registers((unsigned long)addr);
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}
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#endif
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@@ -0,0 +1,66 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#ifndef _RTL83XX_IRQ_H_
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#define _RTL83XX_IRQ_H_
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#define NR_IRQS 32
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#include_next <irq.h>
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/* Global Interrupt Mask Register */
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#define RTL83XX_ICTL_GIMR 0x00
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/* Global Interrupt Status Register */
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#define RTL83XX_ICTL_GISR 0x04
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#define RTL83XX_IRQ_CPU_BASE 0
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#define RTL83XX_IRQ_CPU_NUM 8
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#define RTL83XX_IRQ_ICTL_BASE (RTL83XX_IRQ_CPU_BASE + RTL83XX_IRQ_CPU_NUM)
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#define RTL83XX_IRQ_ICTL_NUM 32
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/* Cascaded interrupts */
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#define RTL83XX_ICTL1_IRQ (RTL83XX_IRQ_CPU_BASE + 2)
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#define RTL83XX_ICTL2_IRQ (RTL83XX_IRQ_CPU_BASE + 3)
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#define RTL83XX_ICTL3_IRQ (RTL83XX_IRQ_CPU_BASE + 4)
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#define RTL83XX_ICTL4_IRQ (RTL83XX_IRQ_CPU_BASE + 5)
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#define RTL83XX_ICTL5_IRQ (RTL83XX_IRQ_CPU_BASE + 6)
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/* Interrupt routing register */
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#define RTL83XX_IRR0 0x08
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#define RTL83XX_IRR1 0x0c
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#define RTL83XX_IRR2 0x10
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#define RTL83XX_IRR3 0x14
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/* Cascade map */
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#define UART0_CASCADE 2
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#define UART1_CASCADE 1
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#define TC0_CASCADE 5
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#define TC1_CASCADE 1
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#define OCPTO_CASCADE 1
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#define HLXTO_CASCADE 1
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#define SLXTO_CASCADE 1
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#define NIC_CASCADE 4
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#define GPIO_ABCD_CASCADE 4
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#define GPIO_EFGH_CASCADE 4
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#define RTC_CASCADE 4
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#define SWCORE_CASCADE 3
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#define WDT_IP1_CASCADE 4
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#define WDT_IP2_CASCADE 5
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/* Pack cascade map into interrupt routing registers */
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#define RTL83XX_IRR0_SETTING (\
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(UART0_CASCADE << 28) | \
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(UART1_CASCADE << 24) | \
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(TC0_CASCADE << 20) | \
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(TC1_CASCADE << 16) | \
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(OCPTO_CASCADE << 12) | \
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(HLXTO_CASCADE << 8) | \
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(SLXTO_CASCADE << 4) | \
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(NIC_CASCADE << 0))
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#define RTL83XX_IRR1_SETTING (\
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(GPIO_ABCD_CASCADE << 28) | \
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(GPIO_EFGH_CASCADE << 24) | \
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(RTC_CASCADE << 20) | \
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(SWCORE_CASCADE << 16))
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#define RTL83XX_IRR2_SETTING 0
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#define RTL83XX_IRR3_SETTING 0
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#endif /* _RTL83XX_IRQ_H_ */
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@@ -0,0 +1,458 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
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* Copyright (C) 2020 B. Koblitz
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*/
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#ifndef _MACH_RTL838X_H_
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#define _MACH_RTL838X_H_
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#include <asm/types.h>
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/*
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* Register access macros
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*/
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#define RTL838X_SW_BASE ((volatile void *) 0xBB000000)
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#define rtl83xx_r32(reg) readl(reg)
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#define rtl83xx_w32(val, reg) writel(val, reg)
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#define rtl83xx_w32_mask(clear, set, reg) rtl83xx_w32((rtl83xx_r32(reg) & ~(clear)) | (set), reg)
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#define rtl83xx_r8(reg) readb(reg)
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#define rtl83xx_w8(val, reg) writeb(val, reg)
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#define sw_r32(reg) readl(RTL838X_SW_BASE + reg)
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#define sw_w32(val, reg) writel(val, RTL838X_SW_BASE + reg)
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#define sw_w32_mask(clear, set, reg) \
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sw_w32((sw_r32(reg) & ~(clear)) | (set), reg)
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#define sw_r64(reg) ((((u64)readl(RTL838X_SW_BASE + reg)) << 32) | \
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readl(RTL838X_SW_BASE + reg + 4))
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#define sw_w64(val, reg) do { \
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writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \
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writel((u32)((val) & 0xffffffff), \
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RTL838X_SW_BASE + reg + 4); \
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} while (0)
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/*
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* SPRAM
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*/
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#define RTL838X_ISPRAM_BASE 0x0
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#define RTL838X_DSPRAM_BASE 0x0
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/*
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* IRQ Controller
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*/
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#define RTL838X_IRQ_CPU_BASE 0
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#define RTL838X_IRQ_CPU_NUM 8
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#define RTL838X_IRQ_ICTL_BASE (RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM)
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#define RTL838X_IRQ_ICTL_NUM 32
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#define RTL83XX_IRQ_UART0 31
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#define RTL83XX_IRQ_UART1 30
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#define RTL83XX_IRQ_TC0 29
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#define RTL83XX_IRQ_TC1 28
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#define RTL83XX_IRQ_OCPTO 27
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#define RTL83XX_IRQ_HLXTO 26
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#define RTL83XX_IRQ_SLXTO 25
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#define RTL83XX_IRQ_NIC 24
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#define RTL83XX_IRQ_GPIO_ABCD 23
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#define RTL83XX_IRQ_GPIO_EFGH 22
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#define RTL83XX_IRQ_RTC 21
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#define RTL83XX_IRQ_SWCORE 20
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#define RTL83XX_IRQ_WDT_IP1 19
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#define RTL83XX_IRQ_WDT_IP2 18
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/*
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* MIPS32R2 counter
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*/
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#define RTL838X_COMPARE_IRQ (RTL838X_IRQ_CPU_BASE + 7)
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/*
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* ICTL
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* Base address 0xb8003000UL
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*/
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#define RTL838X_ICTL1_IRQ (RTL838X_IRQ_CPU_BASE + 2)
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#define RTL838X_ICTL2_IRQ (RTL838X_IRQ_CPU_BASE + 3)
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#define RTL838X_ICTL3_IRQ (RTL838X_IRQ_CPU_BASE + 4)
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#define RTL838X_ICTL4_IRQ (RTL838X_IRQ_CPU_BASE + 5)
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#define RTL838X_ICTL5_IRQ (RTL838X_IRQ_CPU_BASE + 6)
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#define GIMR (0x00)
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#define UART0_IE (1 << 31)
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#define UART1_IE (1 << 30)
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#define TC0_IE (1 << 29)
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#define TC1_IE (1 << 28)
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#define OCPTO_IE (1 << 27)
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#define HLXTO_IE (1 << 26)
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#define SLXTO_IE (1 << 25)
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#define NIC_IE (1 << 24)
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#define GPIO_ABCD_IE (1 << 23)
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#define GPIO_EFGH_IE (1 << 22)
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#define RTC_IE (1 << 21)
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#define WDT_IP1_IE (1 << 19)
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#define WDT_IP2_IE (1 << 18)
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#define GISR (0x04)
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#define UART0_IP (1 << 31)
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#define UART1_IP (1 << 30)
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#define TC0_IP (1 << 29)
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#define TC1_IP (1 << 28)
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#define OCPTO_IP (1 << 27)
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#define HLXTO_IP (1 << 26)
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#define SLXTO_IP (1 << 25)
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#define NIC_IP (1 << 24)
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#define GPIO_ABCD_IP (1 << 23)
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#define GPIO_EFGH_IP (1 << 22)
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#define RTC_IP (1 << 21)
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#define WDT_IP1_IP (1 << 19)
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#define WDT_IP2_IP (1 << 18)
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#define IRR0 (0x08)
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#define IRR0_SETTING ((UART0_RS << 28) | \
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(UART1_RS << 24) | \
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(TC0_RS << 20) | \
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(TC1_RS << 16) | \
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(OCPTO_RS << 12) | \
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(HLXTO_RS << 8) | \
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(SLXTO_RS << 4) | \
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(NIC_RS << 0) \
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)
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#define IRR1 (0x0c)
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#define IRR1_SETTING_RTL838X ((GPIO_ABCD_RS << 28) | \
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(GPIO_EFGH_RS << 24) | \
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(RTC_RS << 20) | \
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(SWCORE_RS << 16) \
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)
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#define IRR1_SETTING_RTL839X ((GPIO_ABCD_RS << 28) | \
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(SWCORE_RS << 16) \
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)
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#define IRR2 (0x10)
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#define IRR2_SETTING 0
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#define IRR3 (0x14)
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#define IRR3_SETTING 0
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/* Interrupt Routing Selection */
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#define UART0_RS 2
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#define UART1_RS 1
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#define TC0_RS 5
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#define TC1_RS 1
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#define OCPTO_RS 1
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#define HLXTO_RS 1
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#define SLXTO_RS 1
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#define NIC_RS 4
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#define GPIO_ABCD_RS 4
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#define GPIO_EFGH_RS 4
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#define RTC_RS 4
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#define SWCORE_RS 3
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#define WDT_IP1_RS 4
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#define WDT_IP2_RS 5
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/* Interrupt IRQ Assignments */
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#define UART0_IRQ 31
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#define UART1_IRQ 30
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#define TC0_IRQ 29
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#define TC1_IRQ 28
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#define OCPTO_IRQ 27
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#define HLXTO_IRQ 26
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#define SLXTO_IRQ 25
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#define NIC_IRQ 24
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#define GPIO_ABCD_IRQ 23
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#define GPIO_EFGH_IRQ 22
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#define RTC_IRQ 21
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#define SWCORE_IRQ 20
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#define WDT_IP1_IRQ 19
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#define WDT_IP2_IRQ 18
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#define SYSTEM_FREQ 200000000
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#define RTL838X_UART0_BASE ((volatile void *)(0xb8002000UL))
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#define RTL838X_UART0_BAUD 38400 /* ex. 19200 or 38400 or 57600 or 115200 */
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#define RTL838X_UART0_FREQ (SYSTEM_FREQ - RTL838X_UART0_BAUD * 24)
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#define RTL838X_UART0_MAPBASE 0x18002000UL
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#define RTL838X_UART0_MAPSIZE 0x100
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#define RTL838X_UART0_IRQ UART0_IRQ
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#define RTL838X_UART1_BASE ((volatile void *)(0xb8002100UL))
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#define RTL838X_UART1_BAUD 38400 /* ex. 19200 or 38400 or 57600 or 115200 */
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#define RTL838X_UART1_FREQ (SYSTEM_FREQ - RTL838X_UART1_BAUD * 24)
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#define RTL838X_UART1_MAPBASE 0x18002100UL
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#define RTL838X_UART1_MAPSIZE 0x100
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#define RTL838X_UART1_IRQ UART1_IRQ
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#define UART0_RBR (RTL838X_UART0_BASE + 0x000)
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#define UART0_THR (RTL838X_UART0_BASE + 0x000)
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#define UART0_DLL (RTL838X_UART0_BASE + 0x000)
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#define UART0_IER (RTL838X_UART0_BASE + 0x004)
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#define UART0_DLM (RTL838X_UART0_BASE + 0x004)
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#define UART0_IIR (RTL838X_UART0_BASE + 0x008)
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#define UART0_FCR (RTL838X_UART0_BASE + 0x008)
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#define UART0_LCR (RTL838X_UART0_BASE + 0x00C)
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#define UART0_MCR (RTL838X_UART0_BASE + 0x010)
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#define UART0_LSR (RTL838X_UART0_BASE + 0x014)
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#define UART1_RBR (RTL838X_UART1_BASE + 0x000)
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#define UART1_THR (RTL838X_UART1_BASE + 0x000)
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#define UART1_DLL (RTL838X_UART1_BASE + 0x000)
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#define UART1_IER (RTL838X_UART1_BASE + 0x004)
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#define UART1_DLM (RTL838X_UART1_BASE + 0x004)
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#define UART1_IIR (RTL838X_UART1_BASE + 0x008)
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#define UART1_FCR (RTL838X_UART1_BASE + 0x008)
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#define FCR_EN 0x01
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#define FCR_RXRST 0x02
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#define XRST 0x02
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#define FCR_TXRST 0x04
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#define TXRST 0x04
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#define FCR_DMA 0x08
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#define FCR_RTRG 0xC0
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#define CHAR_TRIGGER_01 0x00
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#define CHAR_TRIGGER_04 0x40
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#define CHAR_TRIGGER_08 0x80
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#define CHAR_TRIGGER_14 0xC0
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#define UART1_LCR (RTL838X_UART1_BASE + 0x00C)
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#define LCR_WLN 0x03
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#define CHAR_LEN_5 0x00
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#define CHAR_LEN_6 0x01
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#define CHAR_LEN_7 0x02
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#define CHAR_LEN_8 0x03
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#define LCR_STB 0x04
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#define ONE_STOP 0x00
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#define TWO_STOP 0x04
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#define LCR_PEN 0x08
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#define PARITY_ENABLE 0x01
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#define PARITY_DISABLE 0x00
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#define LCR_EPS 0x30
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#define PARITY_ODD 0x00
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#define PARITY_EVEN 0x10
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#define PARITY_MARK 0x20
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#define PARITY_SPACE 0x30
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#define LCR_BRK 0x40
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#define LCR_DLAB 0x80
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#define DLAB 0x80
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#define UART1_MCR (RTL838X_UART1_BASE + 0x010)
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#define UART1_LSR (RTL838X_UART1_BASE + 0x014)
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#define LSR_DR 0x01
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#define RxCHAR_AVAIL 0x01
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#define LSR_OE 0x02
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#define LSR_PE 0x04
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#define LSR_FE 0x08
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#define LSR_BI 0x10
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#define LSR_THRE 0x20
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#define TxCHAR_AVAIL 0x00
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#define TxCHAR_EMPTY 0x20
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#define LSR_TEMT 0x40
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#define LSR_RFE 0x80
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/*
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* Timer/counter for 8390/80/28 TC & MP chip
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*/
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#define RTL838X_TIMER0_BASE ((volatile void *)(0xb8003100UL))
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#define RTL838X_TIMER0_IRQ RTL838X_TC0_EXT_IRQ
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#define RTL8390TC_TC1DATA (RTL838X_TIMER0_BASE + 0x04)
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#define RTL8390TC_TCD_OFFSET 8
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#define RTL8390TC_TC0CNT (RTL838X_TIMER0_BASE + 0x08)
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#define RTL8390TC_TC1CNT (RTL838X_TIMER0_BASE + 0x0C)
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#define RTL8390TC_TCCNR (RTL838X_TIMER0_BASE + 0x10)
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#define RTL8390TC_TC0EN (1 << 31)
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#define RTL8390TC_TC0MODE_TIMER (1 << 30)
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#define RTL8390TC_TC1EN (1 << 29)
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#define RTL8390TC_TC1MODE_TIMER (1 << 28)
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#define RTL8390TC_TCIR (RTL838X_TIMER0_BASE + 0x14)
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#define RTL8390TC_TC0IE (1 << 31)
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#define RTL8390TC_TC1IE (1 << 30)
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#define RTL8390TC_TC0IP (1 << 29)
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#define RTL8390TC_TC1IP (1 << 28)
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#define RTL8390TC_CDBR (RTL838X_TIMER0_BASE + 0x18)
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#define RTL8390TC_DIVF_OFFSET 16
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#define RTL8390TC_WDTCNR (RTL838X_TIMER0_BASE + 0x1C)
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#define RTL8390MP_TC1DATA (RTL838X_TIMER0_BASE + 0x10)
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#define RTL8390MP_TC0CNT (RTL838X_TIMER0_BASE + 0x04)
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#define RTL8390MP_TC1CNT (RTL838X_TIMER0_BASE + 0x14)
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#define RTL8390MP_TC0CTL (RTL838X_TIMER0_BASE + 0x08)
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#define RTL8390MP_TC1CTL (RTL838X_TIMER0_BASE + 0x18)
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#define RTL8390MP_TCEN (1 << 28)
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#define RTL8390MP_TCMODE_TIMER (1 << 24)
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#define RTL8390MP_TCDIV_FACTOR (0xFFFF << 0)
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#define RTL8390MP_TC0INT (RTL838X_TIMER0_BASE + 0xC)
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#define RTL8390MP_TC1INT (RTL838X_TIMER0_BASE + 0x1C)
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#define RTL8390MP_TCIE (1 << 20)
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#define RTL8390MP_TCIP (1 << 16)
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#define RTL8390MP_WDTCNR (RTL838X_TIMER0_BASE + 0x50)
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|
||||
#define RTL8380MP_TC0DATA (RTL838X_TIMER0_BASE + 0x00)
|
||||
#define RTL8380MP_TC1DATA (RTL838X_TIMER0_BASE + 0x10)
|
||||
#define RTL8380MP_TC0CNT (RTL838X_TIMER0_BASE + 0x04)
|
||||
#define RTL8380MP_TC1CNT (RTL838X_TIMER0_BASE + 0x14)
|
||||
#define RTL8380MP_TC0CTL (RTL838X_TIMER0_BASE + 0x08)
|
||||
#define RTL8380MP_TC1CTL (RTL838X_TIMER0_BASE + 0x18)
|
||||
#define RTL8380MP_TCEN (1 << 28)
|
||||
#define RTL8380MP_TCMODE_TIMER (1 << 24)
|
||||
#define RTL8380MP_TCDIV_FACTOR (0xFFFF << 0)
|
||||
#define RTL8380MP_TC0INT (RTL838X_TIMER0_BASE + 0xC)
|
||||
#define RTL8380MP_TC1INT (RTL838X_TIMER0_BASE + 0x1C)
|
||||
#define RTL8380MP_TCIE (1 << 20)
|
||||
#define RTL8380MP_TCIP (1 << 16)
|
||||
#define RTL8380MP_WDTCNR (RTL838X_TIMER0_BASE + 0x50)
|
||||
|
||||
#define DIVISOR_RTL8390 55
|
||||
#define DIVISOR_RTL8380 2500
|
||||
#define DIVISOR_MAX 16834
|
||||
|
||||
/*
|
||||
* Memory Controller
|
||||
*/
|
||||
#define MC_MCR 0xB8001000
|
||||
#define MC_MCR_VAL 0x00000000
|
||||
|
||||
#define MC_DCR 0xB8001004
|
||||
#define MC_DCR0_VAL 0x54480000
|
||||
|
||||
#define MC_DTCR 0xB8001008
|
||||
#define MC_DTCR_VAL 0xFFFF05C0
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
#define GPIO_CTRL_REG_BASE ((volatile void *) 0xb8003500)
|
||||
#define RTL838X_GPIO_PABC_CNR (GPIO_CTRL_REG_BASE + 0x0)
|
||||
#define RTL838X_GPIO_PABC_TYPE (GPIO_CTRL_REG_BASE + 0x04)
|
||||
#define RTL838X_GPIO_PABC_DIR (GPIO_CTRL_REG_BASE + 0x8)
|
||||
#define RTL838X_GPIO_PABC_DATA (GPIO_CTRL_REG_BASE + 0xc)
|
||||
#define RTL838X_GPIO_PABC_ISR (GPIO_CTRL_REG_BASE + 0x10)
|
||||
#define RTL838X_GPIO_PAB_IMR (GPIO_CTRL_REG_BASE + 0x14)
|
||||
#define RTL838X_GPIO_PC_IMR (GPIO_CTRL_REG_BASE + 0x18)
|
||||
|
||||
#define RTL838X_MODEL_NAME_INFO (0x00D4)
|
||||
#define RTL839X_MODEL_NAME_INFO (0x0FF0)
|
||||
#define RTL838X_LED_GLB_CTRL (0xA000)
|
||||
#define RTL839X_LED_GLB_CTRL (0x00E4)
|
||||
#define RTL838X_EXT_GPIO_DIR (0xA08C)
|
||||
#define RTL839X_EXT_GPIO_DIR (0x0214)
|
||||
#define RTL838X_EXT_GPIO_DATA (0xA094)
|
||||
#define RTL839X_EXT_GPIO_DATA (0x021c)
|
||||
#define RTL838X_EXT_GPIO_INDRT_ACCESS (0xA09C)
|
||||
#define RTL839X_EXT_GPIO_INDRT_ACCESS (0x0224)
|
||||
#define RTL838X_EXTRA_GPIO_CTRL (0xA0E0)
|
||||
#define RTL838X_DMY_REG5 (0x0144)
|
||||
#define RTL838X_EXTRA_GPIO_CTRL (0xA0E0)
|
||||
|
||||
#define RTL838X_GMII_INTF_SEL (0x1000)
|
||||
#define RTL838X_IO_DRIVING_ABILITY_CTRL (0x1010)
|
||||
|
||||
#define RTL838X_GPIO_A7 31
|
||||
#define RTL838X_GPIO_A6 30
|
||||
#define RTL838X_GPIO_A5 29
|
||||
#define RTL838X_GPIO_A4 28
|
||||
#define RTL838X_GPIO_A3 27
|
||||
#define RTL838X_GPIO_A2 26
|
||||
#define RTL838X_GPIO_A1 25
|
||||
#define RTL838X_GPIO_A0 24
|
||||
#define RTL838X_GPIO_B7 23
|
||||
#define RTL838X_GPIO_B6 22
|
||||
#define RTL838X_GPIO_B5 21
|
||||
#define RTL838X_GPIO_B4 20
|
||||
#define RTL838X_GPIO_B3 19
|
||||
#define RTL838X_GPIO_B2 18
|
||||
#define RTL838X_GPIO_B1 17
|
||||
#define RTL838X_GPIO_B0 16
|
||||
#define RTL838X_GPIO_C7 15
|
||||
#define RTL838X_GPIO_C6 14
|
||||
#define RTL838X_GPIO_C5 13
|
||||
#define RTL838X_GPIO_C4 12
|
||||
#define RTL838X_GPIO_C3 11
|
||||
#define RTL838X_GPIO_C2 10
|
||||
#define RTL838X_GPIO_C1 9
|
||||
#define RTL838X_GPIO_C0 8
|
||||
|
||||
#define RTL838X_INT_RW_CTRL (0x0058)
|
||||
#define RTL838X_EXT_VERSION (0x00D0)
|
||||
#define RTL838X_PLL_CML_CTRL (0x0FF8)
|
||||
#define RTL838X_STRAP_DBG (0x100C)
|
||||
|
||||
/*
|
||||
* Reset
|
||||
*/
|
||||
#define RGCR (0x1E70)
|
||||
#define RTL839X_RST_GLB_CTRL (0x0014)
|
||||
#define RTL838X_RST_GLB_CTRL_1 (0x0040)
|
||||
|
||||
/* LED control by switch */
|
||||
#define RTL838X_LED_MODE_SEL (0x1004)
|
||||
#define RTL838X_LED_MODE_CTRL (0xA004)
|
||||
#define RTL838X_LED_P_EN_CTRL (0xA008)
|
||||
|
||||
/* LED control by software */
|
||||
#define RTL838X_LED_SW_CTRL (0x0128)
|
||||
#define RTL839X_LED_SW_CTRL (0xA00C)
|
||||
#define RTL838X_LED_SW_P_EN_CTRL (0xA010)
|
||||
#define RTL839X_LED_SW_P_EN_CTRL (0x012C)
|
||||
#define RTL838X_LED0_SW_P_EN_CTRL (0xA010)
|
||||
#define RTL839X_LED0_SW_P_EN_CTRL (0x012C)
|
||||
#define RTL838X_LED1_SW_P_EN_CTRL (0xA014)
|
||||
#define RTL839X_LED1_SW_P_EN_CTRL (0x0130)
|
||||
#define RTL838X_LED2_SW_P_EN_CTRL (0xA018)
|
||||
#define RTL839X_LED2_SW_P_EN_CTRL (0x0134)
|
||||
#define RTL838X_LED_SW_P_CTRL (0xA01C)
|
||||
#define RTL839X_LED_SW_P_CTRL (0x0144)
|
||||
|
||||
#define RTL839X_MAC_EFUSE_CTRL (0x02ac)
|
||||
|
||||
/*
|
||||
* MDIO via Realtek's SMI interface
|
||||
*/
|
||||
#define RTL838X_SMI_GLB_CTRL (0xa100)
|
||||
#define RTL838X_SMI_ACCESS_PHY_CTRL_0 (0xa1b8)
|
||||
#define RTL838X_SMI_ACCESS_PHY_CTRL_1 (0xa1bc)
|
||||
#define RTL838X_SMI_ACCESS_PHY_CTRL_2 (0xa1c0)
|
||||
#define RTL838X_SMI_ACCESS_PHY_CTRL_3 (0xa1c4)
|
||||
#define RTL838X_SMI_PORT0_5_ADDR_CTRL (0xa1c8)
|
||||
#define RTL838X_SMI_POLL_CTRL (0xa17c)
|
||||
|
||||
#define RTL839X_SMI_GLB_CTRL (0x03f8)
|
||||
#define RTL839X_SMI_PORT_POLLING_CTRL (0x03fc)
|
||||
#define RTL839X_PHYREG_ACCESS_CTRL (0x03DC)
|
||||
#define RTL839X_PHYREG_CTRL (0x03E0)
|
||||
#define RTL839X_PHYREG_PORT_CTRL(p) (0x03E4 + ((p >> 5) << 2))
|
||||
#define RTL839X_PHYREG_DATA_CTRL (0x03F0)
|
||||
|
||||
/*
|
||||
* Switch interrupts
|
||||
*/
|
||||
#define RTL838X_IMR_GLB (0x1100)
|
||||
#define RTL838X_IMR_PORT_LINK_STS_CHG (0x1104)
|
||||
#define RTL838X_ISR_GLB_SRC (0x1148)
|
||||
#define RTL838X_ISR_PORT_LINK_STS_CHG (0x114C)
|
||||
#define RTL839X_IMR_GLB (0x0064)
|
||||
#define RTL839X_IMR_PORT_LINK_STS_CHG (0x0068)
|
||||
#define RTL839X_ISR_GLB_SRC (0x009c)
|
||||
#define RTL839X_ISR_PORT_LINK_STS_CHG (0x00a0)
|
||||
|
||||
/* Definition of family IDs */
|
||||
#define RTL8389_FAMILY_ID (0x8389)
|
||||
#define RTL8328_FAMILY_ID (0x8328)
|
||||
#define RTL8390_FAMILY_ID (0x8390)
|
||||
#define RTL8350_FAMILY_ID (0x8350)
|
||||
#define RTL8380_FAMILY_ID (0x8380)
|
||||
#define RTL8330_FAMILY_ID (0x8330)
|
||||
|
||||
struct rtl83xx_soc_info {
|
||||
unsigned char *name;
|
||||
unsigned int id;
|
||||
unsigned int family;
|
||||
unsigned char *compatible;
|
||||
volatile void *sw_base;
|
||||
volatile void *icu_base;
|
||||
};
|
||||
|
||||
/* rtl83xx-related functions used across subsystems */
|
||||
int rtl838x_smi_wait_op(int timeout);
|
||||
int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
|
||||
int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
|
||||
int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
|
||||
int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
|
||||
|
||||
#endif /* _MACH_RTL838X_H_ */
|
||||
@@ -0,0 +1,5 @@
|
||||
#
|
||||
# Makefile for the rtl838x specific parts of the kernel
|
||||
#
|
||||
|
||||
obj-y := setup.o prom.o irq.o
|
||||
@@ -0,0 +1,6 @@
|
||||
#
|
||||
# Realtek RTL838x SoCs
|
||||
#
|
||||
platform-$(CONFIG_RTL838X) += rtl838x/
|
||||
cflags-$(CONFIG_RTL838X) += -I$(srctree)/arch/mips/include/asm/mach-rtl838x/
|
||||
load-$(CONFIG_RTL838X) += 0xffffffff80000000
|
||||
167
target/linux/realtek/files-5.4/arch/mips/rtl838x/irq.c
Normal file
167
target/linux/realtek/files-5.4/arch/mips/rtl838x/irq.c
Normal file
@@ -0,0 +1,167 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Realtek RTL83XX architecture specific IRQ handling
|
||||
*
|
||||
* based on the original BSP
|
||||
* Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
|
||||
* Copyright (C) 2020 B. Koblitz
|
||||
* Copyright (C) 2020 Bert Vermeulen <bert@biot.com>
|
||||
* Copyright (C) 2020 John Crispin <john@phrozen.org>
|
||||
*/
|
||||
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <asm/cevt-r4k.h>
|
||||
|
||||
#include <mach-rtl83xx.h>
|
||||
#include "irq.h"
|
||||
|
||||
#define REALTEK_CPU_IRQ_SHARED0 (MIPS_CPU_IRQ_BASE + 2)
|
||||
#define REALTEK_CPU_IRQ_UART (MIPS_CPU_IRQ_BASE + 3)
|
||||
#define REALTEK_CPU_IRQ_SWITCH (MIPS_CPU_IRQ_BASE + 4)
|
||||
#define REALTEK_CPU_IRQ_SHARED1 (MIPS_CPU_IRQ_BASE + 5)
|
||||
#define REALTEK_CPU_IRQ_EXTERNAL (MIPS_CPU_IRQ_BASE + 6)
|
||||
#define REALTEK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
|
||||
|
||||
#define REG(x) (rtl83xx_ictl_base + x)
|
||||
|
||||
extern struct rtl83xx_soc_info soc_info;
|
||||
|
||||
static DEFINE_RAW_SPINLOCK(irq_lock);
|
||||
static void __iomem *rtl83xx_ictl_base;
|
||||
|
||||
static void rtl83xx_ictl_enable_irq(struct irq_data *i)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
|
||||
raw_spin_lock_irqsave(&irq_lock, flags);
|
||||
|
||||
value = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR));
|
||||
value |= BIT(i->hwirq);
|
||||
rtl83xx_w32(value, REG(RTL83XX_ICTL_GIMR));
|
||||
|
||||
raw_spin_unlock_irqrestore(&irq_lock, flags);
|
||||
}
|
||||
|
||||
static void rtl83xx_ictl_disable_irq(struct irq_data *i)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 value;
|
||||
|
||||
raw_spin_lock_irqsave(&irq_lock, flags);
|
||||
|
||||
value = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR));
|
||||
value &= ~BIT(i->hwirq);
|
||||
rtl83xx_w32(value, REG(RTL83XX_ICTL_GIMR));
|
||||
|
||||
raw_spin_unlock_irqrestore(&irq_lock, flags);
|
||||
}
|
||||
|
||||
static struct irq_chip rtl83xx_ictl_irq = {
|
||||
.name = "RTL83xx",
|
||||
.irq_enable = rtl83xx_ictl_enable_irq,
|
||||
.irq_disable = rtl83xx_ictl_disable_irq,
|
||||
.irq_ack = rtl83xx_ictl_disable_irq,
|
||||
.irq_mask = rtl83xx_ictl_disable_irq,
|
||||
.irq_unmask = rtl83xx_ictl_enable_irq,
|
||||
.irq_eoi = rtl83xx_ictl_enable_irq,
|
||||
};
|
||||
|
||||
static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
|
||||
{
|
||||
irq_set_chip_and_handler(hw, &rtl83xx_ictl_irq, handle_level_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops irq_domain_ops = {
|
||||
.map = intc_map,
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
};
|
||||
|
||||
static void rtl838x_irq_dispatch(struct irq_desc *desc)
|
||||
{
|
||||
unsigned int pending = rtl83xx_r32(REG(RTL83XX_ICTL_GIMR)) & rtl83xx_r32(REG(RTL83XX_ICTL_GISR));
|
||||
|
||||
if (pending) {
|
||||
struct irq_domain *domain = irq_desc_get_handler_data(desc);
|
||||
generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
|
||||
} else {
|
||||
spurious_interrupt();
|
||||
}
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending;
|
||||
|
||||
pending = read_c0_cause() & read_c0_status() & ST0_IM;
|
||||
|
||||
if (pending & CAUSEF_IP7)
|
||||
do_IRQ(REALTEK_CPU_IRQ_COUNTER);
|
||||
|
||||
else if (pending & CAUSEF_IP6)
|
||||
do_IRQ(REALTEK_CPU_IRQ_EXTERNAL);
|
||||
|
||||
else if (pending & CAUSEF_IP5)
|
||||
do_IRQ(REALTEK_CPU_IRQ_SHARED1);
|
||||
|
||||
else if (pending & CAUSEF_IP4)
|
||||
do_IRQ(REALTEK_CPU_IRQ_SWITCH);
|
||||
|
||||
else if (pending & CAUSEF_IP3)
|
||||
do_IRQ(REALTEK_CPU_IRQ_UART);
|
||||
|
||||
else if (pending & CAUSEF_IP2)
|
||||
do_IRQ(REALTEK_CPU_IRQ_SHARED0);
|
||||
|
||||
else
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
static void __init icu_of_init(struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
struct irq_domain *domain;
|
||||
|
||||
domain = irq_domain_add_simple(node, 32, 0,
|
||||
&irq_domain_ops, NULL);
|
||||
irq_set_chained_handler_and_data(2, rtl838x_irq_dispatch, domain);
|
||||
irq_set_chained_handler_and_data(5, rtl838x_irq_dispatch, domain);
|
||||
|
||||
rtl83xx_ictl_base = of_iomap(node, 0);
|
||||
if (!rtl83xx_ictl_base)
|
||||
return;
|
||||
|
||||
/* Disable all cascaded interrupts */
|
||||
rtl83xx_w32(0, REG(RTL83XX_ICTL_GIMR));
|
||||
|
||||
/* Set up interrupt routing */
|
||||
rtl83xx_w32(RTL83XX_IRR0_SETTING, REG(RTL83XX_IRR0));
|
||||
rtl83xx_w32(RTL83XX_IRR1_SETTING, REG(RTL83XX_IRR1));
|
||||
rtl83xx_w32(RTL83XX_IRR2_SETTING, REG(RTL83XX_IRR2));
|
||||
rtl83xx_w32(RTL83XX_IRR3_SETTING, REG(RTL83XX_IRR3));
|
||||
|
||||
/* Clear timer interrupt */
|
||||
write_c0_compare(0);
|
||||
|
||||
/* Enable all CPU interrupts */
|
||||
write_c0_status(read_c0_status() | ST0_IM);
|
||||
|
||||
/* Enable timer0 and uart0 interrupts */
|
||||
rtl83xx_w32(BIT(RTL83XX_IRQ_TC0) | BIT(RTL83XX_IRQ_UART0), REG(RTL83XX_ICTL_GIMR));
|
||||
}
|
||||
|
||||
static struct of_device_id __initdata of_irq_ids[] = {
|
||||
{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
|
||||
{ .compatible = "realtek,rt8380-intc", .data = icu_of_init },
|
||||
{},
|
||||
};
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
of_irq_init(of_irq_ids);
|
||||
}
|
||||
124
target/linux/realtek/files-5.4/arch/mips/rtl838x/prom.c
Normal file
124
target/linux/realtek/files-5.4/arch/mips/rtl838x/prom.c
Normal file
@@ -0,0 +1,124 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* prom.c
|
||||
* Early intialization code for the Realtek RTL838X SoC
|
||||
*
|
||||
* based on the original BSP by
|
||||
* Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
|
||||
* Copyright (C) 2020 B. Koblitz
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/cpu.h>
|
||||
|
||||
#include <mach-rtl83xx.h>
|
||||
|
||||
extern char arcs_cmdline[];
|
||||
extern const char __appended_dtb;
|
||||
|
||||
struct rtl83xx_soc_info soc_info;
|
||||
const void *fdt;
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return soc_info.name;
|
||||
}
|
||||
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void __init device_tree_init(void)
|
||||
{
|
||||
if (!fdt_check_header(&__appended_dtb)) {
|
||||
fdt = &__appended_dtb;
|
||||
pr_info("Using appended Device Tree.\n");
|
||||
}
|
||||
initial_boot_params = (void *)fdt;
|
||||
unflatten_and_copy_device_tree();
|
||||
}
|
||||
|
||||
static void __init prom_init_cmdline(void)
|
||||
{
|
||||
int argc = fw_arg0;
|
||||
char **argv = (char **) KSEG1ADDR(fw_arg1);
|
||||
int i;
|
||||
|
||||
arcs_cmdline[0] = '\0';
|
||||
|
||||
for (i = 0; i < argc; i++) {
|
||||
char *p = (char *) KSEG1ADDR(argv[i]);
|
||||
|
||||
if (CPHYSADDR(p) && *p) {
|
||||
strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
|
||||
strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
|
||||
}
|
||||
}
|
||||
pr_info("Kernel command line: %s\n", arcs_cmdline);
|
||||
}
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
uint32_t model;
|
||||
|
||||
/* uart0 */
|
||||
setup_8250_early_printk_port(0xb8002000, 2, 0);
|
||||
|
||||
soc_info.sw_base = RTL838X_SW_BASE;
|
||||
|
||||
model = sw_r32(RTL838X_MODEL_NAME_INFO) >> 16;
|
||||
if (model != 0x8328 && model != 0x8330 && model != 0x8332 &&
|
||||
model != 0x8380 && model != 0x8382)
|
||||
model = sw_r32(RTL839X_MODEL_NAME_INFO) >> 16;
|
||||
|
||||
soc_info.id = model;
|
||||
|
||||
switch (model) {
|
||||
case 0x8328:
|
||||
soc_info.name = "RTL8328";
|
||||
soc_info.family = RTL8328_FAMILY_ID;
|
||||
break;
|
||||
case 0x8332:
|
||||
soc_info.name = "RTL8332";
|
||||
soc_info.family = RTL8380_FAMILY_ID;
|
||||
break;
|
||||
case 0x8380:
|
||||
soc_info.name = "RTL8380";
|
||||
soc_info.family = RTL8380_FAMILY_ID;
|
||||
break;
|
||||
case 0x8382:
|
||||
soc_info.name = "RTL8382";
|
||||
soc_info.family = RTL8380_FAMILY_ID;
|
||||
break;
|
||||
case 0x8390:
|
||||
soc_info.name = "RTL8390";
|
||||
soc_info.family = RTL8390_FAMILY_ID;
|
||||
break;
|
||||
case 0x8391:
|
||||
soc_info.name = "RTL8391";
|
||||
soc_info.family = RTL8390_FAMILY_ID;
|
||||
break;
|
||||
case 0x8392:
|
||||
soc_info.name = "RTL8392";
|
||||
soc_info.family = RTL8390_FAMILY_ID;
|
||||
break;
|
||||
case 0x8393:
|
||||
soc_info.name = "RTL8393";
|
||||
soc_info.family = RTL8390_FAMILY_ID;
|
||||
break;
|
||||
default:
|
||||
soc_info.name = "DEFAULT";
|
||||
soc_info.family = 0;
|
||||
}
|
||||
pr_info("SoC Type: %s\n", get_system_type());
|
||||
prom_init_cmdline();
|
||||
}
|
||||
109
target/linux/realtek/files-5.4/arch/mips/rtl838x/setup.c
Normal file
109
target/linux/realtek/files-5.4/arch/mips/rtl838x/setup.c
Normal file
@@ -0,0 +1,109 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Setup for the Realtek RTL838X SoC:
|
||||
* Memory, Timer and Serial
|
||||
*
|
||||
* Copyright (C) 2020 B. Koblitz
|
||||
* based on the original BSP by
|
||||
* Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/console.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/time.h> /* for mips_hpt_frequency */
|
||||
#include <asm/prom.h>
|
||||
#include <asm/smp-ops.h>
|
||||
|
||||
#include "mach-rtl83xx.h"
|
||||
|
||||
extern int rtl838x_serial_init(void);
|
||||
extern struct rtl83xx_soc_info soc_info;
|
||||
|
||||
u32 pll_reset_value;
|
||||
|
||||
static void rtl838x_restart(char *command)
|
||||
{
|
||||
u32 pll = sw_r32(RTL838X_PLL_CML_CTRL);
|
||||
/* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */
|
||||
void (*f)(void) = (void *) 0xbfc00000;
|
||||
|
||||
pr_info("System restart.\n");
|
||||
if (soc_info.family == RTL8390_FAMILY_ID) {
|
||||
f();
|
||||
/* If calling reset vector fails, reset entire chip */
|
||||
sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL);
|
||||
/* If this fails, halt the CPU */
|
||||
while
|
||||
(1);
|
||||
}
|
||||
|
||||
pr_info("PLL control register: %x, applying reset value %x\n",
|
||||
pll, pll_reset_value);
|
||||
sw_w32(3, RTL838X_INT_RW_CTRL);
|
||||
sw_w32(pll_reset_value, RTL838X_PLL_CML_CTRL);
|
||||
sw_w32(0, RTL838X_INT_RW_CTRL);
|
||||
|
||||
pr_info("Resetting RTL838X SoC\n");
|
||||
/* Reset Global Control1 Register */
|
||||
sw_w32(1, RTL838X_RST_GLB_CTRL_1);
|
||||
}
|
||||
|
||||
static void rtl838x_halt(void)
|
||||
{
|
||||
pr_info("System halted.\n");
|
||||
while(1);
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
void *dtb;
|
||||
|
||||
set_io_port_base(KSEG1);
|
||||
_machine_restart = rtl838x_restart;
|
||||
_machine_halt = rtl838x_halt;
|
||||
|
||||
if (fw_passed_dtb) /* UHI interface */
|
||||
dtb = (void *)fw_passed_dtb;
|
||||
else if (__dtb_start != __dtb_end)
|
||||
dtb = (void *)__dtb_start;
|
||||
else
|
||||
panic("no dtb found");
|
||||
|
||||
/*
|
||||
* Load the devicetree. This causes the chosen node to be
|
||||
* parsed resulting in our memory appearing
|
||||
*/
|
||||
__dt_setup_arch(dtb);
|
||||
}
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
u32 freq = 500000000;
|
||||
|
||||
np = of_find_node_by_name(NULL, "cpus");
|
||||
if (!np) {
|
||||
pr_err("Missing 'cpus' DT node, using default frequency.");
|
||||
} else {
|
||||
if (of_property_read_u32(np, "frequency", &freq) < 0)
|
||||
pr_err("No 'frequency' property in DT, using default.");
|
||||
else
|
||||
pr_info("CPU frequency from device tree: %d", freq);
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
mips_hpt_frequency = freq / 2;
|
||||
|
||||
pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL);
|
||||
}
|
||||
321
target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl8231.c
Normal file
321
target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl8231.c
Normal file
@@ -0,0 +1,321 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <asm/mach-rtl838x/mach-rtl83xx.h>
|
||||
|
||||
/* RTL8231 registers for LED control */
|
||||
#define RTL8231_LED_FUNC0 0x0000
|
||||
#define RTL8231_GPIO_PIN_SEL(gpio) ((0x0002) + ((gpio) >> 4))
|
||||
#define RTL8231_GPIO_DIR(gpio) ((0x0005) + ((gpio) >> 4))
|
||||
#define RTL8231_GPIO_DATA(gpio) ((0x001C) + ((gpio) >> 4))
|
||||
|
||||
struct rtl8231_gpios {
|
||||
struct gpio_chip gc;
|
||||
struct device *dev;
|
||||
u32 id;
|
||||
int smi_bus_id;
|
||||
u16 reg_shadow[0x20];
|
||||
u32 reg_cached;
|
||||
int ext_gpio_indrt_access;
|
||||
};
|
||||
|
||||
extern struct mutex smi_lock;
|
||||
extern struct rtl83xx_soc_info soc_info;
|
||||
|
||||
static u32 rtl8231_read(struct rtl8231_gpios *gpios, u32 reg)
|
||||
{
|
||||
u32 t = 0;
|
||||
u8 bus_id = gpios->smi_bus_id;
|
||||
|
||||
reg &= 0x1f;
|
||||
bus_id &= 0x1f;
|
||||
|
||||
/* Calculate read register address */
|
||||
t = (bus_id << 2) | (reg << 7);
|
||||
|
||||
/* Set execution bit: cleared when operation completed */
|
||||
t |= 1;
|
||||
sw_w32(t, gpios->ext_gpio_indrt_access);
|
||||
do { /* TODO: Return 0x80000000 if timeout */
|
||||
t = sw_r32(gpios->ext_gpio_indrt_access);
|
||||
} while (t & 1);
|
||||
pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, (t & 0xffff0000) >> 16);
|
||||
|
||||
return (t & 0xffff0000) >> 16;
|
||||
}
|
||||
|
||||
static int rtl8231_write(struct rtl8231_gpios *gpios, u32 reg, u32 data)
|
||||
{
|
||||
u32 t = 0;
|
||||
u8 bus_id = gpios->smi_bus_id;
|
||||
|
||||
pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, data);
|
||||
reg &= 0x1f;
|
||||
bus_id &= 0x1f;
|
||||
|
||||
t = (bus_id << 2) | (reg << 7) | (data << 16);
|
||||
/* Set write bit */
|
||||
t |= 2;
|
||||
|
||||
/* Set execution bit: cleared when operation completed */
|
||||
t |= 1;
|
||||
sw_w32(t, gpios->ext_gpio_indrt_access);
|
||||
do { /* TODO: Return -1 if timeout */
|
||||
t = sw_r32(gpios->ext_gpio_indrt_access);
|
||||
} while (t & 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 rtl8231_read_cached(struct rtl8231_gpios *gpios, u32 reg)
|
||||
{
|
||||
if (reg > 0x1f)
|
||||
return 0;
|
||||
|
||||
if (gpios->reg_cached & (1 << reg))
|
||||
return gpios->reg_shadow[reg];
|
||||
|
||||
return rtl8231_read(gpios, reg);
|
||||
}
|
||||
|
||||
/* Set Direction of the RTL8231 pin:
|
||||
* dir 1: input
|
||||
* dir 0: output
|
||||
*/
|
||||
static int rtl8231_pin_dir(struct rtl8231_gpios *gpios, u32 gpio, u32 dir)
|
||||
{
|
||||
u32 v;
|
||||
int pin_sel_addr = RTL8231_GPIO_PIN_SEL(gpio);
|
||||
int pin_dir_addr = RTL8231_GPIO_DIR(gpio);
|
||||
int pin = gpio % 16;
|
||||
int dpin = pin;
|
||||
|
||||
if (gpio > 31) {
|
||||
pr_info("WARNING: HIGH pin\n");
|
||||
dpin = pin << 5;
|
||||
pin_dir_addr = pin_sel_addr;
|
||||
}
|
||||
|
||||
v = rtl8231_read_cached(gpios, pin_dir_addr);
|
||||
if (v & 0x80000000) {
|
||||
pr_err("Error reading RTL8231\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
v = (v & ~(1 << dpin)) | (dir << dpin);
|
||||
rtl8231_write(gpios, pin_dir_addr, v);
|
||||
gpios->reg_shadow[pin_dir_addr] = v;
|
||||
gpios->reg_cached |= 1 << pin_dir_addr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtl8231_pin_dir_get(struct rtl8231_gpios *gpios, u32 gpio, u32 *dir)
|
||||
{
|
||||
/* dir 1: input
|
||||
* dir 0: output
|
||||
*/
|
||||
|
||||
u32 v;
|
||||
int pin_dir_addr = RTL8231_GPIO_DIR(gpio);
|
||||
int pin = gpio % 16;
|
||||
|
||||
if (gpio > 31) {
|
||||
pin_dir_addr = RTL8231_GPIO_PIN_SEL(gpio);
|
||||
pin = pin << 5;
|
||||
}
|
||||
|
||||
v = rtl8231_read(gpios, pin_dir_addr);
|
||||
if (v & (1 << pin))
|
||||
*dir = 1;
|
||||
else
|
||||
*dir = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtl8231_pin_set(struct rtl8231_gpios *gpios, u32 gpio, u32 data)
|
||||
{
|
||||
u32 v = rtl8231_read(gpios, RTL8231_GPIO_DATA(gpio));
|
||||
|
||||
pr_debug("%s: %d to %d\n", __func__, gpio, data);
|
||||
if (v & 0x80000000) {
|
||||
pr_err("Error reading RTL8231\n");
|
||||
return -1;
|
||||
}
|
||||
v = (v & ~(1 << (gpio % 16))) | (data << (gpio % 16));
|
||||
rtl8231_write(gpios, RTL8231_GPIO_DATA(gpio), v);
|
||||
gpios->reg_shadow[RTL8231_GPIO_DATA(gpio)] = v;
|
||||
gpios->reg_cached |= 1 << RTL8231_GPIO_DATA(gpio);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtl8231_pin_get(struct rtl8231_gpios *gpios, u32 gpio, u16 *state)
|
||||
{
|
||||
u32 v = rtl8231_read(gpios, RTL8231_GPIO_DATA(gpio));
|
||||
|
||||
if (v & 0x80000000) {
|
||||
pr_err("Error reading RTL8231\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
*state = v & 0xffff;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtl8231_direction_input(struct gpio_chip *gc, unsigned int offset)
|
||||
{
|
||||
int err;
|
||||
struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
|
||||
|
||||
pr_debug("%s: %d\n", __func__, offset);
|
||||
mutex_lock(&smi_lock);
|
||||
err = rtl8231_pin_dir(gpios, offset, 1);
|
||||
mutex_unlock(&smi_lock);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int rtl8231_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
|
||||
{
|
||||
int err;
|
||||
struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
|
||||
|
||||
pr_debug("%s: %d\n", __func__, offset);
|
||||
mutex_lock(&smi_lock);
|
||||
err = rtl8231_pin_dir(gpios, offset, 0);
|
||||
mutex_unlock(&smi_lock);
|
||||
if (!err)
|
||||
err = rtl8231_pin_set(gpios, offset, value);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int rtl8231_get_direction(struct gpio_chip *gc, unsigned int offset)
|
||||
{
|
||||
u32 v = 0;
|
||||
struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
|
||||
|
||||
pr_debug("%s: %d\n", __func__, offset);
|
||||
mutex_lock(&smi_lock);
|
||||
rtl8231_pin_dir_get(gpios, offset, &v);
|
||||
mutex_unlock(&smi_lock);
|
||||
return v;
|
||||
}
|
||||
|
||||
static int rtl8231_gpio_get(struct gpio_chip *gc, unsigned int offset)
|
||||
{
|
||||
u16 state = 0;
|
||||
struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
|
||||
|
||||
mutex_lock(&smi_lock);
|
||||
rtl8231_pin_get(gpios, offset, &state);
|
||||
mutex_unlock(&smi_lock);
|
||||
if (state & (1 << (offset % 16)))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void rtl8231_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
|
||||
{
|
||||
struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
|
||||
|
||||
rtl8231_pin_set(gpios, offset, value);
|
||||
}
|
||||
|
||||
int rtl8231_init(struct rtl8231_gpios *gpios)
|
||||
{
|
||||
pr_info("%s called, MDIO bus ID: %d\n", __func__, gpios->smi_bus_id);
|
||||
|
||||
if (soc_info.family == RTL8390_FAMILY_ID) {
|
||||
sw_w32_mask(0x7 << 18, 0x4 << 18, RTL839X_LED_GLB_CTRL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Enable RTL8231 indirect access mode */
|
||||
sw_w32_mask(0, 1, RTL838X_EXTRA_GPIO_CTRL);
|
||||
sw_w32_mask(3, 1, RTL838X_DMY_REG5);
|
||||
|
||||
/* Enable RTL8231 via GPIO_A1 line
|
||||
rtl838x_w32_mask(0, 1 << RTL838X_GPIO_A1, RTL838X_GPIO_PABC_DIR);
|
||||
rtl838x_w32_mask(0, 1 << RTL838X_GPIO_A1, RTL838X_GPIO_PABC_DATA); */
|
||||
mdelay(50); /* wait 50ms for reset */
|
||||
|
||||
/*Select GPIO functionality for pins 0-15, 16-31 and 32-37 */
|
||||
rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(0), 0xffff);
|
||||
rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(16), 0xffff);
|
||||
|
||||
gpios->reg_cached = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rtl8231_gpio_of_match[] = {
|
||||
{ .compatible = "realtek,rtl8231-gpio" },
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, rtl8231_gpio_of_match);
|
||||
|
||||
static int rtl8231_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct rtl8231_gpios *gpios;
|
||||
int err;
|
||||
u8 indirect_bus_id;
|
||||
|
||||
pr_info("Probing RTL8231 GPIOs\n");
|
||||
|
||||
if (!np) {
|
||||
dev_err(&pdev->dev, "No DT found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL);
|
||||
if (!gpios)
|
||||
return -ENOMEM;
|
||||
|
||||
gpios->id = soc_info.id;
|
||||
if (soc_info.family == RTL8380_FAMILY_ID) {
|
||||
gpios->ext_gpio_indrt_access = RTL838X_EXT_GPIO_INDRT_ACCESS;
|
||||
}
|
||||
|
||||
if (soc_info.family == RTL8390_FAMILY_ID) {
|
||||
gpios->ext_gpio_indrt_access = RTL839X_EXT_GPIO_INDRT_ACCESS;
|
||||
}
|
||||
|
||||
if (!of_property_read_u8(np, "indirect-access-bus-id", &indirect_bus_id)) {
|
||||
gpios->smi_bus_id = indirect_bus_id;
|
||||
rtl8231_init(gpios);
|
||||
}
|
||||
|
||||
gpios->dev = dev;
|
||||
gpios->gc.base = 160;
|
||||
gpios->gc.ngpio = 36;
|
||||
gpios->gc.label = "rtl8231";
|
||||
gpios->gc.parent = dev;
|
||||
gpios->gc.owner = THIS_MODULE;
|
||||
gpios->gc.can_sleep = true;
|
||||
|
||||
gpios->gc.direction_input = rtl8231_direction_input;
|
||||
gpios->gc.direction_output = rtl8231_direction_output;
|
||||
gpios->gc.set = rtl8231_gpio_set;
|
||||
gpios->gc.get = rtl8231_gpio_get;
|
||||
gpios->gc.get_direction = rtl8231_get_direction;
|
||||
|
||||
err = devm_gpiochip_add_data(dev, &gpios->gc, gpios);
|
||||
return err;
|
||||
}
|
||||
|
||||
static struct platform_driver rtl8231_gpio_driver = {
|
||||
.driver = {
|
||||
.name = "rtl8231-gpio",
|
||||
.of_match_table = rtl8231_gpio_of_match,
|
||||
},
|
||||
.probe = rtl8231_gpio_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(rtl8231_gpio_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Realtek RTL8231 GPIO expansion chip support");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
425
target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl838x.c
Normal file
425
target/linux/realtek/files-5.4/drivers/gpio/gpio-rtl838x.c
Normal file
@@ -0,0 +1,425 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <asm/mach-rtl838x/mach-rtl83xx.h>
|
||||
|
||||
/* RTL8231 registers for LED control */
|
||||
#define RTL8231_LED_FUNC0 0x0000
|
||||
#define RTL8231_GPIO_PIN_SEL(gpio) ((0x0002) + ((gpio) >> 4))
|
||||
#define RTL8231_GPIO_DIR(gpio) ((0x0005) + ((gpio) >> 4))
|
||||
#define RTL8231_GPIO_DATA(gpio) ((0x001C) + ((gpio) >> 4))
|
||||
|
||||
struct rtl838x_gpios {
|
||||
struct gpio_chip gc;
|
||||
u32 id;
|
||||
struct device *dev;
|
||||
int irq;
|
||||
int num_leds;
|
||||
int min_led;
|
||||
int leds_per_port;
|
||||
u32 led_mode;
|
||||
int led_glb_ctrl;
|
||||
int led_sw_ctrl;
|
||||
int (*led_sw_p_ctrl)(int port);
|
||||
int (*led_sw_p_en_ctrl)(int port);
|
||||
int (*ext_gpio_dir)(int i);
|
||||
int (*ext_gpio_data)(int i);
|
||||
};
|
||||
|
||||
inline int rtl838x_ext_gpio_dir(int i)
|
||||
{
|
||||
return RTL838X_EXT_GPIO_DIR + ((i >>5) << 2);
|
||||
}
|
||||
|
||||
inline int rtl839x_ext_gpio_dir(int i)
|
||||
{
|
||||
return RTL839X_EXT_GPIO_DIR + ((i >>5) << 2);
|
||||
}
|
||||
|
||||
inline int rtl838x_ext_gpio_data(int i)
|
||||
{
|
||||
return RTL838X_EXT_GPIO_DATA + ((i >>5) << 2);
|
||||
}
|
||||
|
||||
inline int rtl839x_ext_gpio_data(int i)
|
||||
{
|
||||
return RTL839X_EXT_GPIO_DATA + ((i >>5) << 2);
|
||||
}
|
||||
|
||||
inline int rtl838x_led_sw_p_ctrl(int p)
|
||||
{
|
||||
return RTL838X_LED_SW_P_CTRL + (p << 2);
|
||||
}
|
||||
|
||||
inline int rtl839x_led_sw_p_ctrl(int p)
|
||||
{
|
||||
return RTL839X_LED_SW_P_CTRL + (p << 2);
|
||||
}
|
||||
|
||||
inline int rtl838x_led_sw_p_en_ctrl(int p)
|
||||
{
|
||||
return RTL838X_LED_SW_P_EN_CTRL + ((p / 10) << 2);
|
||||
}
|
||||
|
||||
inline int rtl839x_led_sw_p_en_ctrl(int p)
|
||||
{
|
||||
return RTL839X_LED_SW_P_EN_CTRL + ((p / 10) << 2);
|
||||
}
|
||||
|
||||
extern struct mutex smi_lock;
|
||||
extern struct rtl83xx_soc_info soc_info;
|
||||
|
||||
|
||||
void rtl838x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
|
||||
{
|
||||
int bit;
|
||||
struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
|
||||
|
||||
pr_debug("rtl838x_set: %d, value: %d\n", offset, value);
|
||||
/* Internal GPIO of the RTL8380 */
|
||||
if (offset < 32) {
|
||||
if (value)
|
||||
rtl83xx_w32_mask(0, BIT(offset), RTL838X_GPIO_PABC_DATA);
|
||||
else
|
||||
rtl83xx_w32_mask(BIT(offset), 0, RTL838X_GPIO_PABC_DATA);
|
||||
}
|
||||
|
||||
/* LED driver for PWR and SYS */
|
||||
if (offset >= 32 && offset < 64) {
|
||||
bit = offset - 32;
|
||||
if (value)
|
||||
sw_w32_mask(0, BIT(bit), gpios->led_glb_ctrl);
|
||||
else
|
||||
sw_w32_mask(BIT(bit), 0, gpios->led_glb_ctrl);
|
||||
return;
|
||||
}
|
||||
|
||||
bit = (offset - 64) % 32;
|
||||
/* First Port-LED */
|
||||
if (offset >= 64 && offset < 96
|
||||
&& offset >= (64 + gpios->min_led)
|
||||
&& offset < (64 + gpios->min_led + gpios->num_leds)) {
|
||||
if (value)
|
||||
sw_w32_mask(7, 5, gpios->led_sw_p_ctrl(bit));
|
||||
else
|
||||
sw_w32_mask(7, 0, gpios->led_sw_p_ctrl(bit));
|
||||
}
|
||||
if (offset >= 96 && offset < 128
|
||||
&& offset >= (96 + gpios->min_led)
|
||||
&& offset < (96 + gpios->min_led + gpios->num_leds)) {
|
||||
if (value)
|
||||
sw_w32_mask(7 << 3, 5 << 3, gpios->led_sw_p_ctrl(bit));
|
||||
else
|
||||
sw_w32_mask(7 << 3, 0, gpios->led_sw_p_ctrl(bit));
|
||||
}
|
||||
if (offset >= 128 && offset < 160
|
||||
&& offset >= (128 + gpios->min_led)
|
||||
&& offset < (128 + gpios->min_led + gpios->num_leds)) {
|
||||
if (value)
|
||||
sw_w32_mask(7 << 6, 5 << 6, gpios->led_sw_p_ctrl(bit));
|
||||
else
|
||||
sw_w32_mask(7 << 6, 0, gpios->led_sw_p_ctrl(bit));
|
||||
}
|
||||
__asm__ volatile ("sync");
|
||||
}
|
||||
|
||||
static int rtl838x_direction_input(struct gpio_chip *gc, unsigned int offset)
|
||||
{
|
||||
pr_debug("%s: %d\n", __func__, offset);
|
||||
|
||||
if (offset < 32) {
|
||||
rtl83xx_w32_mask(BIT(offset), 0, RTL838X_GPIO_PABC_DIR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Internal LED driver does not support input */
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static int rtl838x_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
|
||||
{
|
||||
pr_debug("%s: %d\n", __func__, offset);
|
||||
if (offset < 32)
|
||||
rtl83xx_w32_mask(0, BIT(offset), RTL838X_GPIO_PABC_DIR);
|
||||
rtl838x_gpio_set(gc, offset, value);
|
||||
|
||||
/* LED for PWR and SYS driver is direction output by default */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtl838x_get_direction(struct gpio_chip *gc, unsigned int offset)
|
||||
{
|
||||
u32 v = 0;
|
||||
|
||||
pr_debug("%s: %d\n", __func__, offset);
|
||||
if (offset < 32) {
|
||||
v = rtl83xx_r32(RTL838X_GPIO_PABC_DIR);
|
||||
if (v & BIT(offset))
|
||||
return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* LED driver for PWR and SYS is direction output by default */
|
||||
if (offset >= 32 && offset < 64)
|
||||
return 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtl838x_gpio_get(struct gpio_chip *gc, unsigned int offset)
|
||||
{
|
||||
u32 v;
|
||||
struct rtl838x_gpios *gpios = gpiochip_get_data(gc);
|
||||
|
||||
pr_debug("%s: %d\n", __func__, offset);
|
||||
|
||||
/* Internal GPIO of the RTL8380 */
|
||||
if (offset < 32) {
|
||||
v = rtl83xx_r32(RTL838X_GPIO_PABC_DATA);
|
||||
if (v & BIT(offset))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* LED driver for PWR and SYS */
|
||||
if (offset >= 32 && offset < 64) {
|
||||
v = sw_r32(gpios->led_glb_ctrl);
|
||||
if (v & BIT(offset-32))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* BUG:
|
||||
bit = (offset - 64) % 32;
|
||||
if (offset >= 64 && offset < 96) {
|
||||
if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & BIT(bit))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
if (offset >= 96 && offset < 128) {
|
||||
if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & BIT(bit))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
if (offset >= 128 && offset < 160) {
|
||||
if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & BIT(bit))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
void rtl8380_led_test(struct rtl838x_gpios *gpios, u32 mask)
|
||||
{
|
||||
int i;
|
||||
u32 led_gbl = sw_r32(gpios->led_glb_ctrl);
|
||||
u32 mode_sel, led_p_en;
|
||||
|
||||
if (soc_info.family == RTL8380_FAMILY_ID) {
|
||||
mode_sel = sw_r32(RTL838X_LED_MODE_SEL);
|
||||
led_p_en = sw_r32(RTL838X_LED_P_EN_CTRL);
|
||||
}
|
||||
|
||||
/* 2 Leds for ports 0-23 and 24-27, 3 would be 0x7 */
|
||||
sw_w32_mask(0x3f, 0x3 | (0x3 << 3), gpios->led_glb_ctrl);
|
||||
|
||||
if(soc_info.family == RTL8380_FAMILY_ID) {
|
||||
/* Enable all leds */
|
||||
sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL);
|
||||
}
|
||||
/* Enable software control of all leds */
|
||||
sw_w32(0xFFFFFFF, gpios->led_sw_ctrl);
|
||||
sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(0));
|
||||
sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(10));
|
||||
sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(20));
|
||||
|
||||
for (i = 0; i < 28; i++) {
|
||||
if (mask & BIT(i))
|
||||
sw_w32(5 | (5 << 3) | (5 << 6), gpios->led_sw_p_ctrl(i));
|
||||
}
|
||||
msleep(3000);
|
||||
|
||||
if (soc_info.family == RTL8380_FAMILY_ID)
|
||||
sw_w32(led_p_en, RTL838X_LED_P_EN_CTRL);
|
||||
/* Disable software control of all leds */
|
||||
sw_w32(0x0000000, gpios->led_sw_ctrl);
|
||||
sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(0));
|
||||
sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(10));
|
||||
sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(20));
|
||||
|
||||
sw_w32(led_gbl, gpios->led_glb_ctrl);
|
||||
if (soc_info.family == RTL8380_FAMILY_ID)
|
||||
sw_w32(mode_sel, RTL838X_LED_MODE_SEL);
|
||||
}
|
||||
|
||||
void take_port_leds(struct rtl838x_gpios *gpios)
|
||||
{
|
||||
int leds_per_port = gpios->leds_per_port;
|
||||
int mode = gpios->led_mode;
|
||||
|
||||
pr_info("%s, %d, %x\n", __func__, leds_per_port, mode);
|
||||
pr_debug("Bootloader settings: %x %x %x\n",
|
||||
sw_r32(gpios->led_sw_p_en_ctrl(0)),
|
||||
sw_r32(gpios->led_sw_p_en_ctrl(10)),
|
||||
sw_r32(gpios->led_sw_p_en_ctrl(20))
|
||||
);
|
||||
|
||||
if (soc_info.family == RTL8380_FAMILY_ID) {
|
||||
pr_debug("led glb: %x, sel %x\n",
|
||||
sw_r32(gpios->led_glb_ctrl), sw_r32(RTL838X_LED_MODE_SEL));
|
||||
pr_debug("RTL838X_LED_P_EN_CTRL: %x", sw_r32(RTL838X_LED_P_EN_CTRL));
|
||||
pr_debug("RTL838X_LED_MODE_CTRL: %x", sw_r32(RTL838X_LED_MODE_CTRL));
|
||||
sw_w32_mask(3, 0, RTL838X_LED_MODE_SEL);
|
||||
sw_w32(mode, RTL838X_LED_MODE_CTRL);
|
||||
}
|
||||
|
||||
/* Enable software control of all leds */
|
||||
sw_w32(0xFFFFFFF, gpios->led_sw_ctrl);
|
||||
if (soc_info.family == RTL8380_FAMILY_ID)
|
||||
sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL);
|
||||
|
||||
sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(0));
|
||||
sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(10));
|
||||
sw_w32(0x0000000, gpios->led_sw_p_en_ctrl(20));
|
||||
|
||||
sw_w32_mask(0x3f, 0, gpios->led_glb_ctrl);
|
||||
switch (leds_per_port) {
|
||||
case 3:
|
||||
sw_w32_mask(0, 0x7 | (0x7 << 3), gpios->led_glb_ctrl);
|
||||
sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(20));
|
||||
/* FALLTHRU */
|
||||
case 2:
|
||||
sw_w32_mask(0, 0x3 | (0x3 << 3), gpios->led_glb_ctrl);
|
||||
sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(10));
|
||||
/* FALLTHRU */
|
||||
case 1:
|
||||
sw_w32_mask(0, 0x1 | (0x1 << 3), gpios->led_glb_ctrl);
|
||||
sw_w32(0xFFFFFFF, gpios->led_sw_p_en_ctrl(0));
|
||||
break;
|
||||
default:
|
||||
pr_err("No LEDS configured for software control\n");
|
||||
}
|
||||
}
|
||||
|
||||
static const struct of_device_id rtl838x_gpio_of_match[] = {
|
||||
{ .compatible = "realtek,rtl838x-gpio" },
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, rtl838x_gpio_of_match);
|
||||
|
||||
static int rtl838x_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct rtl838x_gpios *gpios;
|
||||
int err;
|
||||
|
||||
pr_info("Probing RTL838X GPIOs\n");
|
||||
|
||||
if (!np) {
|
||||
dev_err(&pdev->dev, "No DT found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL);
|
||||
if (!gpios)
|
||||
return -ENOMEM;
|
||||
|
||||
gpios->id = soc_info.id;
|
||||
|
||||
switch (gpios->id) {
|
||||
case 0x8332:
|
||||
pr_debug("Found RTL8332M GPIO\n");
|
||||
break;
|
||||
case 0x8380:
|
||||
pr_debug("Found RTL8380M GPIO\n");
|
||||
break;
|
||||
case 0x8381:
|
||||
pr_debug("Found RTL8381M GPIO\n");
|
||||
break;
|
||||
case 0x8382:
|
||||
pr_debug("Found RTL8382M GPIO\n");
|
||||
break;
|
||||
case 0x8391:
|
||||
pr_debug("Found RTL8391 GPIO\n");
|
||||
break;
|
||||
case 0x8393:
|
||||
pr_debug("Found RTL8393 GPIO\n");
|
||||
break;
|
||||
default:
|
||||
pr_err("Unknown GPIO chip id (%04x)\n", gpios->id);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (soc_info.family == RTL8380_FAMILY_ID) {
|
||||
gpios->led_glb_ctrl = gpios->led_glb_ctrl;
|
||||
gpios->led_sw_ctrl = RTL838X_LED_SW_CTRL;
|
||||
gpios->led_sw_p_ctrl = rtl838x_led_sw_p_ctrl;
|
||||
gpios->led_sw_p_en_ctrl = rtl838x_led_sw_p_en_ctrl;
|
||||
gpios->ext_gpio_dir = rtl838x_ext_gpio_dir;
|
||||
gpios->ext_gpio_data = rtl838x_ext_gpio_data;
|
||||
}
|
||||
|
||||
if (soc_info.family == RTL8390_FAMILY_ID) {
|
||||
gpios->led_glb_ctrl = RTL839X_LED_GLB_CTRL;
|
||||
gpios->led_sw_ctrl = RTL839X_LED_SW_CTRL;
|
||||
gpios->led_sw_p_ctrl = rtl839x_led_sw_p_ctrl;
|
||||
gpios->led_sw_p_en_ctrl = rtl839x_led_sw_p_en_ctrl;
|
||||
gpios->ext_gpio_dir = rtl839x_ext_gpio_dir;
|
||||
gpios->ext_gpio_data = rtl839x_ext_gpio_data;
|
||||
}
|
||||
|
||||
gpios->dev = dev;
|
||||
gpios->gc.base = 0;
|
||||
/* 0-31: internal
|
||||
* 32-63, LED control register
|
||||
* 64-95: PORT-LED 0
|
||||
* 96-127: PORT-LED 1
|
||||
* 128-159: PORT-LED 2
|
||||
*/
|
||||
gpios->gc.ngpio = 160;
|
||||
gpios->gc.label = "rtl838x";
|
||||
gpios->gc.parent = dev;
|
||||
gpios->gc.owner = THIS_MODULE;
|
||||
gpios->gc.can_sleep = true;
|
||||
gpios->irq = 31;
|
||||
|
||||
gpios->gc.direction_input = rtl838x_direction_input;
|
||||
gpios->gc.direction_output = rtl838x_direction_output;
|
||||
gpios->gc.set = rtl838x_gpio_set;
|
||||
gpios->gc.get = rtl838x_gpio_get;
|
||||
gpios->gc.get_direction = rtl838x_get_direction;
|
||||
|
||||
if (of_property_read_bool(np, "take-port-leds")) {
|
||||
if (of_property_read_u32(np, "leds-per-port", &gpios->leds_per_port))
|
||||
gpios->leds_per_port = 2;
|
||||
if (of_property_read_u32(np, "led-mode", &gpios->led_mode))
|
||||
gpios->led_mode = (0x1ea << 15) | 0x1ea;
|
||||
if (of_property_read_u32(np, "num-leds", &gpios->num_leds))
|
||||
gpios->num_leds = 32;
|
||||
if (of_property_read_u32(np, "min-led", &gpios->min_led))
|
||||
gpios->min_led = 0;
|
||||
take_port_leds(gpios);
|
||||
}
|
||||
|
||||
err = devm_gpiochip_add_data(dev, &gpios->gc, gpios);
|
||||
return err;
|
||||
}
|
||||
|
||||
static struct platform_driver rtl838x_gpio_driver = {
|
||||
.driver = {
|
||||
.name = "rtl838x-gpio",
|
||||
.of_match_table = rtl838x_gpio_of_match,
|
||||
},
|
||||
.probe = rtl838x_gpio_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(rtl838x_gpio_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Realtek RTL838X GPIO API support");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
603
target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c
Normal file
603
target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c
Normal file
@@ -0,0 +1,603 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/spi-nor.h>
|
||||
|
||||
#include "rtl838x-spi.h"
|
||||
#include <asm/mach-rtl838x/mach-rtl83xx.h>
|
||||
|
||||
extern struct rtl83xx_soc_info soc_info;
|
||||
|
||||
struct rtl838x_nor {
|
||||
struct spi_nor nor;
|
||||
struct device *dev;
|
||||
volatile void __iomem *base;
|
||||
bool fourByteMode;
|
||||
u32 chipSize;
|
||||
uint32_t flags;
|
||||
uint32_t io_status;
|
||||
};
|
||||
|
||||
static uint32_t spi_prep(struct rtl838x_nor *rtl838x_nor)
|
||||
{
|
||||
/* Needed because of MMU constraints */
|
||||
SPI_WAIT_READY;
|
||||
spi_w32w(SPI_CS_INIT, SFCSR); //deactivate CS0, CS1
|
||||
spi_w32w(0, SFCSR); //activate CS0,CS1
|
||||
spi_w32w(SPI_CS_INIT, SFCSR); //deactivate CS0, CS1
|
||||
|
||||
return (CS0 & rtl838x_nor->flags) ? (SPI_eCS0 & SPI_LEN_INIT)
|
||||
: ((SPI_eCS1 & SPI_LEN_INIT) | SFCSR_CHIP_SEL);
|
||||
}
|
||||
|
||||
static uint32_t rtl838x_nor_get_SR(struct rtl838x_nor *rtl838x_nor)
|
||||
{
|
||||
uint32_t sfcsr, sfdr;
|
||||
|
||||
sfcsr = spi_prep(rtl838x_nor);
|
||||
sfdr = (SPINOR_OP_RDSR)<<24;
|
||||
|
||||
pr_debug("%s: rdid,sfcsr_val = %.8x,SFDR = %.8x\n", __func__, sfcsr, sfdr);
|
||||
pr_debug("rdid,sfcsr = %.8x\n", sfcsr | SPI_LEN4);
|
||||
spi_w32w(sfcsr, SFCSR);
|
||||
spi_w32w(sfdr, SFDR);
|
||||
spi_w32_mask(0, SPI_LEN4, SFCSR);
|
||||
SPI_WAIT_READY;
|
||||
|
||||
return spi_r32(SFDR);
|
||||
}
|
||||
|
||||
static void spi_write_disable(struct rtl838x_nor *rtl838x_nor)
|
||||
{
|
||||
uint32_t sfcsr, sfdr;
|
||||
|
||||
sfcsr = spi_prep(rtl838x_nor);
|
||||
sfdr = (SPINOR_OP_WRDI) << 24;
|
||||
spi_w32w(sfcsr, SFCSR);
|
||||
spi_w32w(sfdr, SFDR);
|
||||
pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
|
||||
|
||||
spi_prep(rtl838x_nor);
|
||||
}
|
||||
|
||||
static void spi_write_enable(struct rtl838x_nor *rtl838x_nor)
|
||||
{
|
||||
uint32_t sfcsr, sfdr;
|
||||
|
||||
sfcsr = spi_prep(rtl838x_nor);
|
||||
sfdr = (SPINOR_OP_WREN) << 24;
|
||||
spi_w32w(sfcsr, SFCSR);
|
||||
spi_w32w(sfdr, SFDR);
|
||||
pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
|
||||
|
||||
spi_prep(rtl838x_nor);
|
||||
}
|
||||
|
||||
static void spi_4b_set(struct rtl838x_nor *rtl838x_nor, bool enable)
|
||||
{
|
||||
uint32_t sfcsr, sfdr;
|
||||
|
||||
sfcsr = spi_prep(rtl838x_nor);
|
||||
if (enable)
|
||||
sfdr = (SPINOR_OP_EN4B) << 24;
|
||||
else
|
||||
sfdr = (SPINOR_OP_EX4B) << 24;
|
||||
|
||||
spi_w32w(sfcsr, SFCSR);
|
||||
spi_w32w(sfdr, SFDR);
|
||||
pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
|
||||
|
||||
spi_prep(rtl838x_nor);
|
||||
}
|
||||
|
||||
static int rtl838x_get_addr_mode(struct rtl838x_nor *rtl838x_nor)
|
||||
{
|
||||
int res = 3;
|
||||
u32 reg;
|
||||
|
||||
sw_w32(0x3, RTL838X_INT_RW_CTRL);
|
||||
if (!sw_r32(RTL838X_EXT_VERSION)) {
|
||||
if (sw_r32(RTL838X_STRAP_DBG) & (1 << 29))
|
||||
res = 4;
|
||||
} else {
|
||||
reg = sw_r32(RTL838X_PLL_CML_CTRL);
|
||||
if ((reg & (1 << 30)) && (reg & (1 << 31)))
|
||||
res = 4;
|
||||
if ((!(reg & (1 << 30)))
|
||||
&& sw_r32(RTL838X_STRAP_DBG) & (1 << 29))
|
||||
res = 4;
|
||||
}
|
||||
sw_w32(0x0, RTL838X_INT_RW_CTRL);
|
||||
return res;
|
||||
}
|
||||
|
||||
static int rtl8390_get_addr_mode(struct rtl838x_nor *rtl838x_nor)
|
||||
{
|
||||
if (spi_r32(RTL8390_SOC_SPI_MMIO_CONF) & (1 << 9))
|
||||
return 4;
|
||||
return 3;
|
||||
}
|
||||
|
||||
ssize_t rtl838x_do_read(struct rtl838x_nor *rtl838x_nor, loff_t from,
|
||||
size_t length, u_char *buffer, uint8_t command)
|
||||
{
|
||||
uint32_t sfcsr, sfdr;
|
||||
uint32_t len = length;
|
||||
|
||||
sfcsr = spi_prep(rtl838x_nor);
|
||||
sfdr = command << 24;
|
||||
|
||||
/* Perform SPINOR_OP_READ: 1 byte command & 3 byte addr*/
|
||||
sfcsr |= SPI_LEN4;
|
||||
sfdr |= from;
|
||||
|
||||
spi_w32w(sfcsr, SFCSR);
|
||||
spi_w32w(sfdr, SFDR);
|
||||
|
||||
/* Read Data, 4 bytes at a time */
|
||||
while (length >= 4) {
|
||||
SPI_WAIT_READY;
|
||||
*((uint32_t *) buffer) = spi_r32(SFDR);
|
||||
buffer += 4;
|
||||
length -= 4;
|
||||
}
|
||||
|
||||
/* The rest needs to be read 1 byte a time */
|
||||
sfcsr &= SPI_LEN_INIT|SPI_LEN1;
|
||||
SPI_WAIT_READY;
|
||||
spi_w32w(sfcsr, SFCSR);
|
||||
while (length > 0) {
|
||||
SPI_WAIT_READY;
|
||||
*(buffer) = spi_r32(SFDR) >> 24;
|
||||
buffer++;
|
||||
length--;
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
/*
|
||||
* Do fast read in 3 or 4 Byte addressing mode
|
||||
*/
|
||||
static ssize_t rtl838x_do_4bf_read(struct rtl838x_nor *rtl838x_nor, loff_t from,
|
||||
size_t length, u_char *buffer, uint8_t command)
|
||||
{
|
||||
int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
|
||||
int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
|
||||
uint32_t sfcsr;
|
||||
uint32_t len = length;
|
||||
|
||||
pr_debug("Fast read from %llx, len %x, shift %d\n",
|
||||
from, sfcsr_addr_len, sfdr_addr_shift);
|
||||
sfcsr = spi_prep(rtl838x_nor);
|
||||
|
||||
/* Send read command */
|
||||
spi_w32w(sfcsr | SPI_LEN1, SFCSR);
|
||||
spi_w32w(command << 24, SFDR);
|
||||
|
||||
/* Send address */
|
||||
spi_w32w(sfcsr | (sfcsr_addr_len << 28), SFCSR);
|
||||
spi_w32w(from << sfdr_addr_shift, SFDR);
|
||||
|
||||
/* Dummy cycles */
|
||||
spi_w32w(sfcsr | SPI_LEN1, SFCSR);
|
||||
spi_w32w(0, SFDR);
|
||||
|
||||
/* Start reading */
|
||||
spi_w32w(sfcsr | SPI_LEN4, SFCSR);
|
||||
|
||||
/* Read Data, 4 bytes at a time */
|
||||
while (length >= 4) {
|
||||
SPI_WAIT_READY;
|
||||
*((uint32_t *) buffer) = spi_r32(SFDR);
|
||||
buffer += 4;
|
||||
length -= 4;
|
||||
}
|
||||
|
||||
/* The rest needs to be read 1 byte a time */
|
||||
sfcsr &= SPI_LEN_INIT|SPI_LEN1;
|
||||
SPI_WAIT_READY;
|
||||
spi_w32w(sfcsr, SFCSR);
|
||||
while (length > 0) {
|
||||
SPI_WAIT_READY;
|
||||
*(buffer) = spi_r32(SFDR) >> 24;
|
||||
buffer++;
|
||||
length--;
|
||||
}
|
||||
return len;
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Do write (Page Programming) in 3 or 4 Byte addressing mode
|
||||
*/
|
||||
static ssize_t rtl838x_do_4b_write(struct rtl838x_nor *rtl838x_nor, loff_t to,
|
||||
size_t length, const u_char *buffer,
|
||||
uint8_t command)
|
||||
{
|
||||
int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
|
||||
int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
|
||||
uint32_t sfcsr;
|
||||
uint32_t len = length;
|
||||
|
||||
pr_debug("Write to %llx, len %x, shift %d\n",
|
||||
to, sfcsr_addr_len, sfdr_addr_shift);
|
||||
sfcsr = spi_prep(rtl838x_nor);
|
||||
|
||||
/* Send write command, command IO-width is 1 (bit 25/26) */
|
||||
spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR);
|
||||
spi_w32w(command << 24, SFDR);
|
||||
|
||||
/* Send address */
|
||||
spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR);
|
||||
spi_w32w(to << sfdr_addr_shift, SFDR);
|
||||
|
||||
/* Write Data, 1 byte at a time, if we are not 4-byte aligned */
|
||||
if (((long)buffer) % 4) {
|
||||
spi_w32w(sfcsr | SPI_LEN1, SFCSR);
|
||||
while (length > 0 && (((long)buffer) % 4)) {
|
||||
SPI_WAIT_READY;
|
||||
spi_w32(*(buffer) << 24, SFDR);
|
||||
buffer += 1;
|
||||
length -= 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Now we can write 4 bytes at a time */
|
||||
SPI_WAIT_READY;
|
||||
spi_w32w(sfcsr | SPI_LEN4, SFCSR);
|
||||
while (length >= 4) {
|
||||
SPI_WAIT_READY;
|
||||
spi_w32(*((uint32_t *)buffer), SFDR);
|
||||
buffer += 4;
|
||||
length -= 4;
|
||||
}
|
||||
|
||||
/* Final bytes might need to be written 1 byte at a time, again */
|
||||
SPI_WAIT_READY;
|
||||
spi_w32w(sfcsr | SPI_LEN1, SFCSR);
|
||||
while (length > 0) {
|
||||
SPI_WAIT_READY;
|
||||
spi_w32(*(buffer) << 24, SFDR);
|
||||
buffer++;
|
||||
length--;
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
static ssize_t rtl838x_nor_write(struct spi_nor *nor, loff_t to, size_t len,
|
||||
const u_char *buffer)
|
||||
{
|
||||
int ret = 0;
|
||||
uint32_t offset = 0;
|
||||
struct rtl838x_nor *rtl838x_nor = nor->priv;
|
||||
size_t l = len;
|
||||
uint8_t cmd = SPINOR_OP_PP;
|
||||
|
||||
/* Do write in 4-byte mode on large Macronix chips */
|
||||
if (rtl838x_nor->fourByteMode) {
|
||||
cmd = SPINOR_OP_PP_4B;
|
||||
spi_4b_set(rtl838x_nor, true);
|
||||
}
|
||||
|
||||
pr_debug("In %s %8x to: %llx\n", __func__,
|
||||
(unsigned int) rtl838x_nor, to);
|
||||
|
||||
while (l >= SPI_MAX_TRANSFER_SIZE) {
|
||||
while
|
||||
(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
|
||||
do {
|
||||
spi_write_enable(rtl838x_nor);
|
||||
} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
|
||||
ret = rtl838x_do_4b_write(rtl838x_nor, to + offset,
|
||||
SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd);
|
||||
l -= SPI_MAX_TRANSFER_SIZE;
|
||||
offset += SPI_MAX_TRANSFER_SIZE;
|
||||
}
|
||||
|
||||
if (l > 0) {
|
||||
while
|
||||
(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
|
||||
do {
|
||||
spi_write_enable(rtl838x_nor);
|
||||
} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
|
||||
ret = rtl838x_do_4b_write(rtl838x_nor, to+offset,
|
||||
len, buffer+offset, cmd);
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static ssize_t rtl838x_nor_read(struct spi_nor *nor, loff_t from,
|
||||
size_t length, u_char *buffer)
|
||||
{
|
||||
uint32_t offset = 0;
|
||||
uint8_t cmd = SPINOR_OP_READ_FAST;
|
||||
size_t l = length;
|
||||
struct rtl838x_nor *rtl838x_nor = nor->priv;
|
||||
|
||||
/* Do fast read in 3, or 4-byte mode on large Macronix chips */
|
||||
if (rtl838x_nor->fourByteMode) {
|
||||
cmd = SPINOR_OP_READ_FAST_4B;
|
||||
spi_4b_set(rtl838x_nor, true);
|
||||
}
|
||||
|
||||
/* TODO: do timeout and return error */
|
||||
pr_debug("Waiting for pending writes\n");
|
||||
while
|
||||
(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
|
||||
do {
|
||||
spi_write_enable(rtl838x_nor);
|
||||
} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
|
||||
|
||||
pr_debug("cmd is %d\n", cmd);
|
||||
pr_debug("%s: addr %.8llx to addr %.8x, cmd %.8x, size %d\n", __func__,
|
||||
from, (u32)buffer, (u32)cmd, length);
|
||||
|
||||
while (l >= SPI_MAX_TRANSFER_SIZE) {
|
||||
rtl838x_do_4bf_read(rtl838x_nor, from + offset,
|
||||
SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd);
|
||||
l -= SPI_MAX_TRANSFER_SIZE;
|
||||
offset += SPI_MAX_TRANSFER_SIZE;
|
||||
}
|
||||
|
||||
if (l > 0)
|
||||
rtl838x_do_4bf_read(rtl838x_nor, from + offset, l, buffer+offset, cmd);
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
static int rtl838x_erase(struct spi_nor *nor, loff_t offs)
|
||||
{
|
||||
struct rtl838x_nor *rtl838x_nor = nor->priv;
|
||||
int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
|
||||
int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
|
||||
uint32_t sfcsr;
|
||||
uint8_t cmd = SPINOR_OP_SE;
|
||||
|
||||
pr_debug("Erasing sector at %llx\n", offs);
|
||||
|
||||
/* Do erase in 4-byte mode on large Macronix chips */
|
||||
if (rtl838x_nor->fourByteMode) {
|
||||
cmd = SPINOR_OP_SE_4B;
|
||||
spi_4b_set(rtl838x_nor, true);
|
||||
}
|
||||
/* TODO: do timeout and return error */
|
||||
while
|
||||
(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
|
||||
do {
|
||||
spi_write_enable(rtl838x_nor);
|
||||
} while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
|
||||
|
||||
sfcsr = spi_prep(rtl838x_nor);
|
||||
|
||||
/* Send erase command, command IO-width is 1 (bit 25/26) */
|
||||
spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR);
|
||||
spi_w32w(cmd << 24, SFDR);
|
||||
|
||||
/* Send address */
|
||||
spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR);
|
||||
spi_w32w(offs << sfdr_addr_shift, SFDR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtl838x_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
|
||||
{
|
||||
int length = len;
|
||||
u8 *buffer = buf;
|
||||
uint32_t sfcsr, sfdr;
|
||||
struct rtl838x_nor *rtl838x_nor = nor->priv;
|
||||
|
||||
pr_debug("In %s: opcode %x, len %x\n", __func__, opcode, len);
|
||||
|
||||
sfcsr = spi_prep(rtl838x_nor);
|
||||
sfdr = opcode << 24;
|
||||
|
||||
sfcsr |= SPI_LEN1;
|
||||
|
||||
spi_w32w(sfcsr, SFCSR);
|
||||
spi_w32w(sfdr, SFDR);
|
||||
|
||||
while (length > 0) {
|
||||
SPI_WAIT_READY;
|
||||
*(buffer) = spi_r32(SFDR) >> 24;
|
||||
buffer++;
|
||||
length--;
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static int rtl838x_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
|
||||
{
|
||||
uint32_t sfcsr, sfdr;
|
||||
struct rtl838x_nor *rtl838x_nor = nor->priv;
|
||||
|
||||
pr_debug("In %s, opcode %x, len %x\n", __func__, opcode, len);
|
||||
sfcsr = spi_prep(rtl838x_nor);
|
||||
sfdr = opcode << 24;
|
||||
|
||||
if (len == 1) { /* SPINOR_OP_WRSR */
|
||||
sfdr |= buf[0];
|
||||
sfcsr |= SPI_LEN2;
|
||||
}
|
||||
spi_w32w(sfcsr, SFCSR);
|
||||
spi_w32w(sfdr, SFDR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_enter_sio(struct spi_nor *nor)
|
||||
{
|
||||
uint32_t sfcsr, sfcr2, sfdr;
|
||||
uint32_t ret = 0, reg = 0, size_bits;
|
||||
struct rtl838x_nor *rtl838x_nor = nor->priv;
|
||||
|
||||
pr_debug("In %s\n", __func__);
|
||||
rtl838x_nor->io_status = 0;
|
||||
sfdr = SPI_C_RSTQIO << 24;
|
||||
sfcsr = spi_prep(rtl838x_nor);
|
||||
|
||||
reg = spi_r32(SFCR2);
|
||||
pr_debug("SFCR2: %x, size %x, rdopt: %x\n", reg, SFCR2_GETSIZE(reg),
|
||||
(reg & SFCR2_RDOPT));
|
||||
size_bits = rtl838x_nor->fourByteMode ? SFCR2_SIZE(0x6) : SFCR2_SIZE(0x7);
|
||||
|
||||
sfcr2 = SFCR2_HOLD_TILL_SFDR2 | size_bits
|
||||
| (reg & SFCR2_RDOPT) | SFCR2_CMDIO(0)
|
||||
| SFCR2_ADDRIO(0) | SFCR2_DUMMYCYCLE(4)
|
||||
| SFCR2_DATAIO(0) | SFCR2_SFCMD(SPINOR_OP_READ_FAST);
|
||||
pr_debug("SFCR2: %x, size %x\n", reg, SFCR2_GETSIZE(reg));
|
||||
|
||||
SPI_WAIT_READY;
|
||||
spi_w32w(sfcr2, SFCR2);
|
||||
spi_w32w(sfcsr, SFCSR);
|
||||
spi_w32w(sfdr, SFDR);
|
||||
|
||||
spi_w32_mask(SFCR2_HOLD_TILL_SFDR2, 0, SFCR2);
|
||||
rtl838x_nor->io_status &= ~IOSTATUS_CIO_MASK;
|
||||
rtl838x_nor->io_status |= CIO1;
|
||||
|
||||
spi_prep(rtl838x_nor);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int rtl838x_spi_nor_scan(struct spi_nor *nor, const char *name)
|
||||
{
|
||||
static const struct spi_nor_hwcaps hwcaps = {
|
||||
.mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_PP
|
||||
| SNOR_HWCAPS_READ_FAST
|
||||
};
|
||||
|
||||
struct rtl838x_nor *rtl838x_nor = nor->priv;
|
||||
|
||||
pr_debug("In %s\n", __func__);
|
||||
|
||||
spi_w32_mask(0, SFCR_EnableWBO, SFCR);
|
||||
spi_w32_mask(0, SFCR_EnableRBO, SFCR);
|
||||
|
||||
rtl838x_nor->flags = CS0 | R_MODE;
|
||||
|
||||
spi_nor_scan(nor, NULL, &hwcaps);
|
||||
pr_debug("------------- Got size: %llx\n", nor->mtd.size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rtl838x_nor_init(struct rtl838x_nor *rtl838x_nor,
|
||||
struct device_node *flash_node)
|
||||
{
|
||||
int ret;
|
||||
struct spi_nor *nor;
|
||||
|
||||
pr_info("%s called\n", __func__);
|
||||
nor = &rtl838x_nor->nor;
|
||||
nor->dev = rtl838x_nor->dev;
|
||||
nor->priv = rtl838x_nor;
|
||||
spi_nor_set_flash_node(nor, flash_node);
|
||||
|
||||
nor->read_reg = rtl838x_nor_read_reg;
|
||||
nor->write_reg = rtl838x_nor_write_reg;
|
||||
nor->read = rtl838x_nor_read;
|
||||
nor->write = rtl838x_nor_write;
|
||||
nor->erase = rtl838x_erase;
|
||||
nor->mtd.name = "rtl838x_nor";
|
||||
nor->erase_opcode = rtl838x_nor->fourByteMode ? SPINOR_OP_SE_4B
|
||||
: SPINOR_OP_SE;
|
||||
/* initialized with NULL */
|
||||
ret = rtl838x_spi_nor_scan(nor, NULL);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
spi_enter_sio(nor);
|
||||
spi_write_disable(rtl838x_nor);
|
||||
|
||||
ret = mtd_device_parse_register(&nor->mtd, NULL, NULL, NULL, 0);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rtl838x_nor_drv_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *flash_np;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
struct rtl838x_nor *rtl838x_nor;
|
||||
int addrMode;
|
||||
|
||||
pr_info("Initializing rtl838x_nor_driver\n");
|
||||
if (!pdev->dev.of_node) {
|
||||
dev_err(&pdev->dev, "No DT found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rtl838x_nor = devm_kzalloc(&pdev->dev, sizeof(*rtl838x_nor), GFP_KERNEL);
|
||||
if (!rtl838x_nor)
|
||||
return -ENOMEM;
|
||||
platform_set_drvdata(pdev, rtl838x_nor);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
rtl838x_nor->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR((void *)rtl838x_nor->base))
|
||||
return PTR_ERR((void *)rtl838x_nor->base);
|
||||
|
||||
pr_info("SPI resource base is %08x\n", (u32)rtl838x_nor->base);
|
||||
rtl838x_nor->dev = &pdev->dev;
|
||||
|
||||
/* only support one attached flash */
|
||||
flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
|
||||
if (!flash_np) {
|
||||
dev_err(&pdev->dev, "no SPI flash device to configure\n");
|
||||
ret = -ENODEV;
|
||||
goto nor_free;
|
||||
}
|
||||
|
||||
/* Get the 3/4 byte address mode as configure by bootloader */
|
||||
if (soc_info.family == RTL8390_FAMILY_ID)
|
||||
addrMode = rtl8390_get_addr_mode(rtl838x_nor);
|
||||
else
|
||||
addrMode = rtl838x_get_addr_mode(rtl838x_nor);
|
||||
pr_info("Address mode is %d bytes\n", addrMode);
|
||||
if (addrMode == 4)
|
||||
rtl838x_nor->fourByteMode = true;
|
||||
|
||||
ret = rtl838x_nor_init(rtl838x_nor, flash_np);
|
||||
|
||||
nor_free:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rtl838x_nor_drv_remove(struct platform_device *pdev)
|
||||
{
|
||||
/* struct rtl8xx_nor *rtl838x_nor = platform_get_drvdata(pdev); */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rtl838x_nor_of_ids[] = {
|
||||
{ .compatible = "realtek,rtl838x-nor"},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rtl838x_nor_of_ids);
|
||||
|
||||
static struct platform_driver rtl838x_nor_driver = {
|
||||
.probe = rtl838x_nor_drv_probe,
|
||||
.remove = rtl838x_nor_drv_remove,
|
||||
.driver = {
|
||||
.name = "rtl838x-nor",
|
||||
.pm = NULL,
|
||||
.of_match_table = rtl838x_nor_of_ids,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(rtl838x_nor_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("RTL838x SPI NOR Flash Driver");
|
||||
111
target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h
Normal file
111
target/linux/realtek/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h
Normal file
@@ -0,0 +1,111 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2009 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _RTL838X_SPI_H
|
||||
#define _RTL838X_SPI_H
|
||||
|
||||
|
||||
/*
|
||||
* Register access macros
|
||||
*/
|
||||
|
||||
#define spi_r32(reg) readl(rtl838x_nor->base + reg)
|
||||
#define spi_w32(val, reg) writel(val, rtl838x_nor->base + reg)
|
||||
#define spi_w32_mask(clear, set, reg) \
|
||||
spi_w32((spi_r32(reg) & ~(clear)) | (set), reg)
|
||||
|
||||
#define SPI_WAIT_READY do { \
|
||||
} while (!(spi_r32(SFCSR) & SFCSR_SPI_RDY))
|
||||
|
||||
#define spi_w32w(val, reg) do { \
|
||||
writel(val, rtl838x_nor->base + reg); \
|
||||
SPI_WAIT_READY; \
|
||||
} while (0)
|
||||
|
||||
#define SFCR (0x00) /*SPI Flash Configuration Register*/
|
||||
#define SFCR_CLK_DIV(val) ((val)<<29)
|
||||
#define SFCR_EnableRBO (1<<28)
|
||||
#define SFCR_EnableWBO (1<<27)
|
||||
#define SFCR_SPI_TCS(val) ((val)<<23) /*4 bit, 1111 */
|
||||
|
||||
#define SFCR2 (0x04) /*For memory mapped I/O */
|
||||
#define SFCR2_SFCMD(val) ((val)<<24) /*8 bit, 1111_1111 */
|
||||
#define SFCR2_SIZE(val) ((val)<<21) /*3 bit, 111 */
|
||||
#define SFCR2_RDOPT (1<<20)
|
||||
#define SFCR2_CMDIO(val) ((val)<<18) /*2 bit, 11 */
|
||||
#define SFCR2_ADDRIO(val) ((val)<<16) /*2 bit, 11 */
|
||||
#define SFCR2_DUMMYCYCLE(val) ((val)<<13) /*3 bit, 111 */
|
||||
#define SFCR2_DATAIO(val) ((val)<<11) /*2 bit, 11 */
|
||||
#define SFCR2_HOLD_TILL_SFDR2 (1<<10)
|
||||
#define SFCR2_GETSIZE(x) (((x)&0x00E00000)>>21)
|
||||
|
||||
#define SFCSR (0x08) /*SPI Flash Control&Status Register*/
|
||||
#define SFCSR_SPI_CSB0 (1<<31)
|
||||
#define SFCSR_SPI_CSB1 (1<<30)
|
||||
#define SFCSR_LEN(val) ((val)<<28) /*2 bits*/
|
||||
#define SFCSR_SPI_RDY (1<<27)
|
||||
#define SFCSR_IO_WIDTH(val) ((val)<<25) /*2 bits*/
|
||||
#define SFCSR_CHIP_SEL (1<<24)
|
||||
#define SFCSR_CMD_BYTE(val) ((val)<<16) /*8 bit, 1111_1111 */
|
||||
|
||||
#define SFDR (0x0C) /*SPI Flash Data Register*/
|
||||
#define SFDR2 (0x10) /*SPI Flash Data Register - for post SPI bootup setting*/
|
||||
#define SPI_CS_INIT (SFCSR_SPI_CSB0 | SFCSR_SPI_CSB1 | SPI_LEN1)
|
||||
#define SPI_CS0 SFCSR_SPI_CSB0
|
||||
#define SPI_CS1 SFCSR_SPI_CSB1
|
||||
#define SPI_eCS0 ((SFCSR_SPI_CSB1)) /*and SFCSR to active CS0*/
|
||||
#define SPI_eCS1 ((SFCSR_SPI_CSB0)) /*and SFCSR to active CS1*/
|
||||
|
||||
#define SPI_WIP (1) /* Write In Progress */
|
||||
#define SPI_WEL (1<<1) /* Write Enable Latch*/
|
||||
#define SPI_SST_QIO_WIP (1<<7) /* SST QIO Flash Write In Progress */
|
||||
#define SPI_LEN_INIT 0xCFFFFFFF /* and SFCSR to init */
|
||||
#define SPI_LEN4 0x30000000 /* or SFCSR to set */
|
||||
#define SPI_LEN3 0x20000000 /* or SFCSR to set */
|
||||
#define SPI_LEN2 0x10000000 /* or SFCSR to set */
|
||||
#define SPI_LEN1 0x00000000 /* or SFCSR to set */
|
||||
#define SPI_SETLEN(val) do { \
|
||||
SPI_REG(SFCSR) &= 0xCFFFFFFF; \
|
||||
SPI_REG(SFCSR) |= (val-1)<<28; \
|
||||
} while (0)
|
||||
/*
|
||||
* SPI interface control
|
||||
*/
|
||||
#define RTL8390_SOC_SPI_MMIO_CONF (0x04)
|
||||
|
||||
#define IOSTATUS_CIO_MASK (0x00000038)
|
||||
|
||||
/* Chip select: bits 4-7*/
|
||||
#define CS0 (1<<4)
|
||||
#define R_MODE 0x04
|
||||
|
||||
/* io_status */
|
||||
#define IO1 (1<<0)
|
||||
#define IO2 (1<<1)
|
||||
#define CIO1 (1<<3)
|
||||
#define CIO2 (1<<4)
|
||||
#define CMD_IO1 (1<<6)
|
||||
#define W_ADDR_IO1 ((1)<<12)
|
||||
#define R_ADDR_IO2 ((2)<<9)
|
||||
#define R_DATA_IO2 ((2)<<15)
|
||||
#define W_DATA_IO1 ((1)<<18)
|
||||
|
||||
/* Commands */
|
||||
#define SPI_C_RSTQIO 0xFF
|
||||
|
||||
#define SPI_MAX_TRANSFER_SIZE 256
|
||||
|
||||
#endif /* _RTL838X_SPI_H */
|
||||
@@ -0,0 +1,8 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
config NET_DSA_RTL83XX
|
||||
tristate "Realtek RTL838x/RTL839x switch support"
|
||||
depends on RTL838X
|
||||
select NET_DSA_TAG_TRAILER
|
||||
---help---
|
||||
This driver adds support for Realtek RTL83xx series switching.
|
||||
|
||||
@@ -0,0 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
obj-$(CONFIG_NET_DSA_RTL83XX) += common.o dsa.o \
|
||||
rtl838x.o rtl839x.o storm.o debugfs.o
|
||||
407
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/common.c
Normal file
407
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/common.c
Normal file
@@ -0,0 +1,407 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include <linux/of_mdio.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/mach-rtl838x/mach-rtl83xx.h>
|
||||
#include "rtl83xx.h"
|
||||
|
||||
extern struct rtl83xx_soc_info soc_info;
|
||||
|
||||
extern const struct rtl838x_reg rtl838x_reg;
|
||||
extern const struct rtl838x_reg rtl839x_reg;
|
||||
extern const struct dsa_switch_ops rtl83xx_switch_ops;
|
||||
|
||||
DEFINE_MUTEX(smi_lock);
|
||||
|
||||
|
||||
// TODO: unused
|
||||
static void dump_fdb(struct rtl838x_switch_priv *priv)
|
||||
{
|
||||
struct rtl838x_l2_entry e;
|
||||
int i;
|
||||
|
||||
mutex_lock(&priv->reg_mutex);
|
||||
|
||||
for (i = 0; i < priv->fib_entries; i++) {
|
||||
priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
|
||||
|
||||
if (!e.valid) /* Check for invalid entry */
|
||||
continue;
|
||||
|
||||
pr_debug("-> port %02d: mac %pM, vid: %d, rvid: %d, MC: %d, %d\n",
|
||||
e.port, &e.mac[0], e.vid, e.rvid, e.is_ip_mc, e.is_ipv6_mc);
|
||||
}
|
||||
|
||||
mutex_unlock(&priv->reg_mutex);
|
||||
}
|
||||
|
||||
// TODO: unused
|
||||
static void rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
|
||||
{
|
||||
u32 cmd, msti = 0;
|
||||
u32 port_state[4];
|
||||
int index, bit, i;
|
||||
int pos = port;
|
||||
int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4;
|
||||
|
||||
/* CPU PORT can only be configured on RTL838x */
|
||||
if (port >= priv->cpu_port || port > 51)
|
||||
return;
|
||||
|
||||
mutex_lock(&priv->reg_mutex);
|
||||
|
||||
/* For the RTL839x, the bits are left-aligned in the 128 bit field */
|
||||
if (priv->family_id == RTL8390_FAMILY_ID)
|
||||
pos += 12;
|
||||
|
||||
index = n - (pos >> 4) - 1;
|
||||
bit = (pos << 1) % 32;
|
||||
|
||||
if (priv->family_id == RTL8380_FAMILY_ID) {
|
||||
cmd = BIT(15) /* Execute cmd */
|
||||
| BIT(14) /* Read */
|
||||
| 2 << 12 /* Table type 0b10 */
|
||||
| (msti & 0xfff);
|
||||
} else {
|
||||
cmd = BIT(16) /* Execute cmd */
|
||||
| 0 << 15 /* Read */
|
||||
| 5 << 12 /* Table type 0b101 */
|
||||
| (msti & 0xfff);
|
||||
}
|
||||
priv->r->exec_tbl0_cmd(cmd);
|
||||
|
||||
for (i = 0; i < n; i++)
|
||||
port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
|
||||
|
||||
mutex_unlock(&priv->reg_mutex);
|
||||
}
|
||||
|
||||
int rtl83xx_dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
|
||||
{
|
||||
u32 val;
|
||||
u32 offset = 0;
|
||||
struct rtl838x_switch_priv *priv = ds->priv;
|
||||
|
||||
if (phy_addr >= 24 && phy_addr <= 27
|
||||
&& priv->ports[24].phy == PHY_RTL838X_SDS) {
|
||||
if (phy_addr == 26)
|
||||
offset = 0x100;
|
||||
val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)) & 0xffff;
|
||||
return val;
|
||||
}
|
||||
|
||||
if (soc_info.family == RTL8390_FAMILY_ID)
|
||||
rtl839x_read_phy(phy_addr, 0, phy_reg, &val);
|
||||
else
|
||||
rtl838x_read_phy(phy_addr, 0, phy_reg, &val);
|
||||
return val;
|
||||
}
|
||||
|
||||
int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
|
||||
{
|
||||
u32 offset = 0;
|
||||
struct rtl838x_switch_priv *priv = ds->priv;
|
||||
|
||||
if (phy_addr >= 24 && phy_addr <= 27
|
||||
&& priv->ports[24].phy == PHY_RTL838X_SDS) {
|
||||
if (phy_addr == 26)
|
||||
offset = 0x100;
|
||||
sw_w32(val, MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2));
|
||||
return 0;
|
||||
}
|
||||
if (soc_info.family == RTL8390_FAMILY_ID)
|
||||
return rtl839x_write_phy(phy_addr, 0, phy_reg, val);
|
||||
else
|
||||
return rtl838x_write_phy(phy_addr, 0, phy_reg, val);
|
||||
}
|
||||
|
||||
static int rtl83xx_mdio_read(struct mii_bus *bus, int addr, int regnum)
|
||||
{
|
||||
int ret;
|
||||
struct rtl838x_switch_priv *priv = bus->priv;
|
||||
|
||||
ret = rtl83xx_dsa_phy_read(priv->ds, addr, regnum);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rtl83xx_mdio_write(struct mii_bus *bus, int addr, int regnum,
|
||||
u16 val)
|
||||
{
|
||||
struct rtl838x_switch_priv *priv = bus->priv;
|
||||
|
||||
return rtl83xx_dsa_phy_write(priv->ds, addr, regnum, val);
|
||||
}
|
||||
|
||||
static void rtl8380_sds_rst(int mac)
|
||||
{
|
||||
u32 offset = (mac == 24) ? 0 : 0x100;
|
||||
|
||||
sw_w32_mask(1 << 11, 0, RTL8380_SDS4_FIB_REG0 + offset);
|
||||
sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);
|
||||
sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);
|
||||
sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);
|
||||
sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);
|
||||
pr_debug("SERDES reset: %d\n", mac);
|
||||
}
|
||||
|
||||
static int __init rtl8380_sds_power(int mac, int val)
|
||||
{
|
||||
u32 mode = (val == 1) ? 0x4 : 0x9;
|
||||
u32 offset = (mac == 24) ? 5 : 0;
|
||||
|
||||
if ((mac != 24) && (mac != 26)) {
|
||||
pr_err("%s: not a fibre port: %d\n", __func__, mac);
|
||||
return -1;
|
||||
}
|
||||
|
||||
sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);
|
||||
|
||||
rtl8380_sds_rst(mac);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
|
||||
{
|
||||
struct device *dev = priv->dev;
|
||||
struct device_node *dn, *mii_np = dev->of_node;
|
||||
struct mii_bus *bus;
|
||||
int ret;
|
||||
u32 pn;
|
||||
|
||||
pr_debug("In %s\n", __func__);
|
||||
mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio");
|
||||
if (mii_np) {
|
||||
pr_debug("Found compatible MDIO node!\n");
|
||||
} else {
|
||||
dev_err(priv->dev, "no %s child node found", "mdio-bus");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
priv->mii_bus = of_mdio_find_bus(mii_np);
|
||||
if (!priv->mii_bus) {
|
||||
pr_debug("Deferring probe of mdio bus\n");
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
if (!of_device_is_available(mii_np))
|
||||
ret = -ENODEV;
|
||||
|
||||
bus = devm_mdiobus_alloc(priv->ds->dev);
|
||||
if (!bus)
|
||||
return -ENOMEM;
|
||||
|
||||
bus->name = "rtl838x slave mii";
|
||||
bus->read = &rtl83xx_mdio_read;
|
||||
bus->write = &rtl83xx_mdio_write;
|
||||
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
|
||||
bus->parent = dev;
|
||||
priv->ds->slave_mii_bus = bus;
|
||||
priv->ds->slave_mii_bus->priv = priv;
|
||||
|
||||
ret = mdiobus_register(priv->ds->slave_mii_bus);
|
||||
if (ret && mii_np) {
|
||||
of_node_put(dn);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dn = mii_np;
|
||||
for_each_node_by_name(dn, "ethernet-phy") {
|
||||
if (of_property_read_u32(dn, "reg", &pn))
|
||||
continue;
|
||||
|
||||
priv->ports[pn].dp = dsa_to_port(priv->ds, pn);
|
||||
|
||||
// Check for the integrated SerDes of the RTL8380M first
|
||||
if (of_property_read_bool(dn, "phy-is-integrated")
|
||||
&& priv->id == 0x8380 && pn >= 24) {
|
||||
pr_debug("----> FÓUND A SERDES\n");
|
||||
priv->ports[pn].phy = PHY_RTL838X_SDS;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (of_property_read_bool(dn, "phy-is-integrated")
|
||||
&& !of_property_read_bool(dn, "sfp")) {
|
||||
priv->ports[pn].phy = PHY_RTL8218B_INT;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!of_property_read_bool(dn, "phy-is-integrated")
|
||||
&& of_property_read_bool(dn, "sfp")) {
|
||||
priv->ports[pn].phy = PHY_RTL8214FC;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!of_property_read_bool(dn, "phy-is-integrated")
|
||||
&& !of_property_read_bool(dn, "sfp")) {
|
||||
priv->ports[pn].phy = PHY_RTL8218B_EXT;
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable MAC polling the PHY so that we can start configuration */
|
||||
priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
|
||||
|
||||
/* Enable PHY control via SoC */
|
||||
if (priv->family_id == RTL8380_FAMILY_ID) {
|
||||
/* Enable PHY control via SoC */
|
||||
sw_w32_mask(0, BIT(15), RTL838X_SMI_GLB_CTRL);
|
||||
} else {
|
||||
/* Disable PHY polling via SoC */
|
||||
sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
|
||||
}
|
||||
|
||||
/* Power on fibre ports and reset them if necessary */
|
||||
if (priv->ports[24].phy == PHY_RTL838X_SDS) {
|
||||
pr_debug("Powering on fibre ports & reset\n");
|
||||
rtl8380_sds_power(24, 1);
|
||||
rtl8380_sds_power(26, 1);
|
||||
}
|
||||
|
||||
pr_debug("%s done\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)
|
||||
{
|
||||
int t = sw_r32(priv->r->l2_ctrl_1);
|
||||
|
||||
t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
|
||||
|
||||
if (priv->family_id == RTL8380_FAMILY_ID)
|
||||
t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
|
||||
else
|
||||
t = (t * 3) / 5;
|
||||
|
||||
pr_debug("L2 AGING time: %d sec\n", t);
|
||||
pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out));
|
||||
return t;
|
||||
}
|
||||
|
||||
static int __init rtl83xx_sw_probe(struct platform_device *pdev)
|
||||
{
|
||||
int err = 0, i;
|
||||
struct rtl838x_switch_priv *priv;
|
||||
struct device *dev = &pdev->dev;
|
||||
u64 irq_mask;
|
||||
|
||||
pr_debug("Probing RTL838X switch device\n");
|
||||
if (!pdev->dev.of_node) {
|
||||
dev_err(dev, "No DT found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
|
||||
|
||||
if (!priv->ds)
|
||||
return -ENOMEM;
|
||||
priv->ds->dev = dev;
|
||||
priv->ds->priv = priv;
|
||||
priv->ds->ops = &rtl83xx_switch_ops;
|
||||
priv->dev = dev;
|
||||
|
||||
priv->family_id = soc_info.family;
|
||||
priv->id = soc_info.id;
|
||||
if (soc_info.family == RTL8380_FAMILY_ID) {
|
||||
priv->cpu_port = RTL838X_CPU_PORT;
|
||||
priv->port_mask = 0x1f;
|
||||
priv->r = &rtl838x_reg;
|
||||
priv->ds->num_ports = 30;
|
||||
priv->fib_entries = 8192;
|
||||
rtl8380_get_version(priv);
|
||||
} else {
|
||||
priv->cpu_port = RTL839X_CPU_PORT;
|
||||
priv->port_mask = 0x3f;
|
||||
priv->r = &rtl839x_reg;
|
||||
priv->ds->num_ports = 53;
|
||||
priv->fib_entries = 16384;
|
||||
rtl8390_get_version(priv);
|
||||
}
|
||||
pr_debug("Chip version %c\n", priv->version);
|
||||
|
||||
err = rtl83xx_mdio_probe(priv);
|
||||
if (err) {
|
||||
/* Probing fails the 1st time because of missing ethernet driver
|
||||
* initialization. Use this to disable traffic in case the bootloader left if on
|
||||
*/
|
||||
return err;
|
||||
}
|
||||
err = dsa_register_switch(priv->ds);
|
||||
if (err) {
|
||||
dev_err(dev, "Error registering switch: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Enable link and media change interrupts. Are the SERDES masks needed? */
|
||||
sw_w32_mask(0, 3, priv->r->isr_glb_src);
|
||||
/* ... for all ports */
|
||||
irq_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x0FFFFFFF : 0xFFFFFFFFFFFFFULL;
|
||||
priv->r->set_port_reg_le(irq_mask, priv->r->isr_port_link_sts_chg);
|
||||
priv->r->set_port_reg_le(irq_mask, priv->r->imr_port_link_sts_chg);
|
||||
|
||||
priv->link_state_irq = platform_get_irq(pdev, 0);;
|
||||
if (priv->family_id == RTL8380_FAMILY_ID) {
|
||||
err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
|
||||
IRQF_SHARED, "rtl838x-link-state", priv->ds);
|
||||
} else {
|
||||
err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
|
||||
IRQF_SHARED, "rtl839x-link-state", priv->ds);
|
||||
}
|
||||
if (err) {
|
||||
dev_err(dev, "Error setting up switch interrupt.\n");
|
||||
/* Need to free allocated switch here */
|
||||
}
|
||||
|
||||
/* Enable interrupts for switch */
|
||||
sw_w32(0x1, priv->r->imr_glb);
|
||||
|
||||
rtl83xx_get_l2aging(priv);
|
||||
|
||||
/*
|
||||
if (priv->family_id == RTL8380_FAMILY_ID)
|
||||
rtl83xx_storm_control_init(priv);
|
||||
*/
|
||||
|
||||
/* Clear all destination ports for mirror groups */
|
||||
for (i = 0; i < 4; i++)
|
||||
priv->mirror_group_ports[i] = -1;
|
||||
|
||||
rtl838x_dbgfs_init(priv);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int rtl83xx_sw_remove(struct platform_device *pdev)
|
||||
{
|
||||
// TODO:
|
||||
pr_debug("Removing platform driver for rtl83xx-sw\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rtl83xx_switch_of_ids[] = {
|
||||
{ .compatible = "realtek,rtl83xx-switch"},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
||||
MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids);
|
||||
|
||||
static struct platform_driver rtl83xx_switch_driver = {
|
||||
.probe = rtl83xx_sw_probe,
|
||||
.remove = rtl83xx_sw_remove,
|
||||
.driver = {
|
||||
.name = "rtl83xx-switch",
|
||||
.pm = NULL,
|
||||
.of_match_table = rtl83xx_switch_of_ids,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(rtl83xx_switch_driver);
|
||||
|
||||
MODULE_AUTHOR("B. Koblitz");
|
||||
MODULE_DESCRIPTION("RTL83XX SoC Switch Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@@ -0,0 +1,99 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include <linux/debugfs.h>
|
||||
|
||||
#include <asm/mach-rtl838x/mach-rtl83xx.h>
|
||||
#include "rtl838x.h"
|
||||
|
||||
#define RTL838X_DRIVER_NAME "rtl838x"
|
||||
|
||||
static const struct debugfs_reg32 port_ctrl_regs[] = {
|
||||
{ .name = "port_isolation", .offset = RTL838X_PORT_ISO_CTRL(0), },
|
||||
{ .name = "mac_force_mode", .offset = RTL838X_MAC_FORCE_MODE_CTRL, },
|
||||
};
|
||||
|
||||
void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv)
|
||||
{
|
||||
debugfs_remove_recursive(priv->dbgfs_dir);
|
||||
|
||||
// kfree(priv->dbgfs_entries);
|
||||
}
|
||||
|
||||
static int rtl838x_dbgfs_port_init(struct dentry *parent, struct rtl838x_switch_priv *priv,
|
||||
int port)
|
||||
{
|
||||
struct dentry *port_dir;
|
||||
struct debugfs_regset32 *port_ctrl_regset;
|
||||
|
||||
port_dir = debugfs_create_dir(priv->ports[port].dp->name, parent);
|
||||
|
||||
debugfs_create_x32("rate_uc", 0644, port_dir,
|
||||
(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_UC(port)));
|
||||
|
||||
debugfs_create_x32("rate_mc", 0644, port_dir,
|
||||
(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port)));
|
||||
|
||||
debugfs_create_x32("rate_bc", 0644, port_dir,
|
||||
(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port)));
|
||||
|
||||
debugfs_create_u32("id", 0444, port_dir, &priv->ports[port].dp->index);
|
||||
|
||||
|
||||
debugfs_create_x32("vlan_port_tag_sts_ctrl", 0644, port_dir,
|
||||
(u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_PORT_TAG_STS_CTRL(port)));
|
||||
|
||||
port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);
|
||||
if (!port_ctrl_regset)
|
||||
return -ENOMEM;
|
||||
|
||||
port_ctrl_regset->regs = port_ctrl_regs;
|
||||
port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
|
||||
port_ctrl_regset->base = RTL838X_SW_BASE + (port << 2);
|
||||
debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv)
|
||||
{
|
||||
struct dentry *rtl838x_dir;
|
||||
struct dentry *port_dir;
|
||||
struct debugfs_regset32 *port_ctrl_regset;
|
||||
int ret, i;
|
||||
|
||||
rtl838x_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL);
|
||||
if (!rtl838x_dir)
|
||||
rtl838x_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL);
|
||||
|
||||
priv->dbgfs_dir = rtl838x_dir;
|
||||
|
||||
debugfs_create_u32("soc", 0444, rtl838x_dir,
|
||||
(u32 *)(RTL838X_SW_BASE + RTL838X_MODEL_NAME_INFO));
|
||||
|
||||
/* Create one directory per port */
|
||||
for (i = 0; i < priv->cpu_port; i++) {
|
||||
if (priv->ports[i].phy) {
|
||||
pr_debug("debugfs, port %d\n", i);
|
||||
ret = rtl838x_dbgfs_port_init(rtl838x_dir, priv, i);
|
||||
if (ret)
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
/* Create directory for CPU-port */
|
||||
port_dir = debugfs_create_dir("cpu_port", rtl838x_dir); port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);
|
||||
if (!port_ctrl_regset) {
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
port_ctrl_regset->regs = port_ctrl_regs;
|
||||
port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);
|
||||
port_ctrl_regset->base = RTL838X_SW_BASE + (priv->cpu_port << 2);
|
||||
debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset);
|
||||
debugfs_create_u8("id", 0444, port_dir, &priv->cpu_port);
|
||||
|
||||
return;
|
||||
err:
|
||||
rtl838x_dbgfs_cleanup(priv);
|
||||
}
|
||||
1170
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c
Normal file
1170
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c
Normal file
File diff suppressed because it is too large
Load Diff
476
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c
Normal file
476
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c
Normal file
@@ -0,0 +1,476 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include <asm/mach-rtl838x/mach-rtl83xx.h>
|
||||
#include "rtl83xx.h"
|
||||
|
||||
extern struct mutex smi_lock;
|
||||
|
||||
|
||||
static inline void rtl838x_mask_port_reg(u64 clear, u64 set, int reg)
|
||||
{
|
||||
sw_w32_mask((u32)clear, (u32)set, reg);
|
||||
}
|
||||
|
||||
static inline void rtl838x_set_port_reg(u64 set, int reg)
|
||||
{
|
||||
sw_w32(set, reg);
|
||||
}
|
||||
|
||||
static inline u64 rtl838x_get_port_reg(int reg)
|
||||
{
|
||||
return ((u64) sw_r32(reg));
|
||||
}
|
||||
|
||||
static inline int rtl838x_stat_port_std_mib(int p)
|
||||
{
|
||||
return RTL838X_STAT_PORT_STD_MIB + (p << 8);
|
||||
}
|
||||
|
||||
static inline int rtl838x_port_iso_ctrl(int p)
|
||||
{
|
||||
return RTL838X_PORT_ISO_CTRL(p);
|
||||
}
|
||||
|
||||
static inline void rtl838x_exec_tbl0_cmd(u32 cmd)
|
||||
{
|
||||
sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0);
|
||||
do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15));
|
||||
}
|
||||
|
||||
static inline void rtl838x_exec_tbl1_cmd(u32 cmd)
|
||||
{
|
||||
sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1);
|
||||
do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15));
|
||||
}
|
||||
|
||||
static inline int rtl838x_tbl_access_data_0(int i)
|
||||
{
|
||||
return RTL838X_TBL_ACCESS_DATA_0(i);
|
||||
}
|
||||
|
||||
static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
|
||||
{
|
||||
u32 cmd, v;
|
||||
|
||||
cmd = BIT(15) /* Execute cmd */
|
||||
| BIT(14) /* Read */
|
||||
| 0 << 12 /* Table type 0b00 */
|
||||
| (vlan & 0xfff);
|
||||
rtl838x_exec_tbl0_cmd(cmd);
|
||||
info->tagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0));
|
||||
v = sw_r32(RTL838X_TBL_ACCESS_DATA_0(1));
|
||||
info->profile_id = v & 0x7;
|
||||
info->hash_mc_fid = !!(v & 0x8);
|
||||
info->hash_uc_fid = !!(v & 0x10);
|
||||
info->fid = (v >> 5) & 0x3f;
|
||||
|
||||
|
||||
cmd = BIT(15) /* Execute cmd */
|
||||
| BIT(14) /* Read */
|
||||
| 0 << 12 /* Table type 0b00 */
|
||||
| (vlan & 0xfff);
|
||||
rtl838x_exec_tbl1_cmd(cmd);
|
||||
info->untagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0));
|
||||
}
|
||||
|
||||
static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
|
||||
{
|
||||
u32 cmd = BIT(15) /* Execute cmd */
|
||||
| 0 << 14 /* Write */
|
||||
| 0 << 12 /* Table type 0b00 */
|
||||
| (vlan & 0xfff);
|
||||
u32 v;
|
||||
|
||||
sw_w32(info->tagged_ports, RTL838X_TBL_ACCESS_DATA_0(0));
|
||||
|
||||
v = info->profile_id;
|
||||
v |= info->hash_mc_fid ? 0x8 : 0;
|
||||
v |= info->hash_uc_fid ? 0x10 : 0;
|
||||
v |= ((u32)info->fid) << 5;
|
||||
|
||||
sw_w32(v, RTL838X_TBL_ACCESS_DATA_0(1));
|
||||
rtl838x_exec_tbl0_cmd(cmd);
|
||||
}
|
||||
|
||||
static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)
|
||||
{
|
||||
u32 cmd = BIT(15) /* Execute cmd */
|
||||
| 0 << 14 /* Write */
|
||||
| 0 << 12 /* Table type 0b00 */
|
||||
| (vlan & 0xfff);
|
||||
sw_w32(portmask & 0x1fffffff, RTL838X_TBL_ACCESS_DATA_1(0));
|
||||
rtl838x_exec_tbl1_cmd(cmd);
|
||||
}
|
||||
|
||||
static inline int rtl838x_mac_force_mode_ctrl(int p)
|
||||
{
|
||||
return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
|
||||
}
|
||||
|
||||
static inline int rtl838x_mac_port_ctrl(int p)
|
||||
{
|
||||
return RTL838X_MAC_PORT_CTRL(p);
|
||||
}
|
||||
|
||||
static inline int rtl838x_l2_port_new_salrn(int p)
|
||||
{
|
||||
return RTL838X_L2_PORT_NEW_SALRN(p);
|
||||
}
|
||||
|
||||
static inline int rtl838x_l2_port_new_sa_fwd(int p)
|
||||
{
|
||||
return RTL838X_L2_PORT_NEW_SA_FWD(p);
|
||||
}
|
||||
|
||||
static inline int rtl838x_mir_ctrl(int group)
|
||||
{
|
||||
return RTL838X_MIR_CTRL(group);
|
||||
}
|
||||
|
||||
static inline int rtl838x_mir_dpm(int group)
|
||||
{
|
||||
return RTL838X_MIR_DPM_CTRL(group);
|
||||
}
|
||||
|
||||
static inline int rtl838x_mir_spm(int group)
|
||||
{
|
||||
return RTL838X_MIR_SPM_CTRL(group);
|
||||
}
|
||||
|
||||
static inline int rtl838x_mac_link_spd_sts(int p)
|
||||
{
|
||||
return RTL838X_MAC_LINK_SPD_STS(p);
|
||||
}
|
||||
|
||||
static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
|
||||
{
|
||||
u64 entry;
|
||||
u32 r[3];
|
||||
|
||||
/* Search in SRAM, with hash and at position in hash bucket (0-3) */
|
||||
u32 idx = (0 << 14) | (hash << 2) | position;
|
||||
|
||||
u32 cmd = BIT(16) /* Execute cmd */
|
||||
| BIT(15) /* Read */
|
||||
| 0 << 13 /* Table type 0b00 */
|
||||
| (idx & 0x1fff);
|
||||
|
||||
sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
|
||||
do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
|
||||
r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
|
||||
r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
|
||||
r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
|
||||
|
||||
e->mac[0] = (r[1] >> 20);
|
||||
e->mac[1] = (r[1] >> 12);
|
||||
e->mac[2] = (r[1] >> 4);
|
||||
e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
|
||||
e->mac[4] = (r[2] >> 20);
|
||||
e->mac[5] = (r[2] >> 12);
|
||||
e->is_static = !!((r[0] >> 19) & 1);
|
||||
e->vid = r[0] & 0xfff;
|
||||
e->rvid = r[2] & 0xfff;
|
||||
e->port = (r[0] >> 12) & 0x1f;
|
||||
|
||||
e->valid = true;
|
||||
if (!(r[0] >> 17)) /* Check for invalid entry */
|
||||
e->valid = false;
|
||||
|
||||
if (e->valid)
|
||||
pr_debug("Found in Hash: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
|
||||
|
||||
entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff);
|
||||
return entry;
|
||||
}
|
||||
|
||||
static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e)
|
||||
{
|
||||
u64 entry;
|
||||
u32 r[3];
|
||||
|
||||
u32 cmd = BIT(16) /* Execute cmd */
|
||||
| BIT(15) /* Read */
|
||||
| BIT(13) /* Table type 0b01 */
|
||||
| (idx & 0x3f);
|
||||
sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
|
||||
do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
|
||||
r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
|
||||
r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
|
||||
r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
|
||||
|
||||
e->mac[0] = (r[1] >> 20);
|
||||
e->mac[1] = (r[1] >> 12);
|
||||
e->mac[2] = (r[1] >> 4);
|
||||
e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
|
||||
e->mac[4] = (r[2] >> 20);
|
||||
e->mac[5] = (r[2] >> 12);
|
||||
e->is_static = !!((r[0] >> 19) & 1);
|
||||
e->vid = r[0] & 0xfff;
|
||||
e->rvid = r[2] & 0xfff;
|
||||
e->port = (r[0] >> 12) & 0x1f;
|
||||
|
||||
e->valid = true;
|
||||
if (!(r[0] >> 17)) /* Check for invalid entry */
|
||||
e->valid = false;
|
||||
|
||||
if (e->valid)
|
||||
pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
|
||||
|
||||
entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff);
|
||||
return entry;
|
||||
}
|
||||
|
||||
static inline int rtl838x_vlan_profile(int profile)
|
||||
{
|
||||
return RTL838X_VLAN_PROFILE(profile);
|
||||
}
|
||||
|
||||
static inline int rtl838x_vlan_port_egr_filter(int port)
|
||||
{
|
||||
return RTL838X_VLAN_PORT_EGR_FLTR;
|
||||
}
|
||||
|
||||
static inline int rtl838x_vlan_port_igr_filter(int port)
|
||||
{
|
||||
return RTL838X_VLAN_PORT_IGR_FLTR(port);
|
||||
}
|
||||
|
||||
static inline int rtl838x_vlan_port_pb(int port)
|
||||
{
|
||||
return RTL838X_VLAN_PORT_PB_VLAN(port);
|
||||
}
|
||||
|
||||
static inline int rtl838x_vlan_port_tag_sts_ctrl(int port)
|
||||
{
|
||||
return RTL838X_VLAN_PORT_TAG_STS_CTRL(port);
|
||||
}
|
||||
|
||||
const struct rtl838x_reg rtl838x_reg = {
|
||||
.mask_port_reg_be = rtl838x_mask_port_reg,
|
||||
.set_port_reg_be = rtl838x_set_port_reg,
|
||||
.get_port_reg_be = rtl838x_get_port_reg,
|
||||
.mask_port_reg_le = rtl838x_mask_port_reg,
|
||||
.set_port_reg_le = rtl838x_set_port_reg,
|
||||
.get_port_reg_le = rtl838x_get_port_reg,
|
||||
.stat_port_rst = RTL838X_STAT_PORT_RST,
|
||||
.stat_rst = RTL838X_STAT_RST,
|
||||
.stat_port_std_mib = rtl838x_stat_port_std_mib,
|
||||
.port_iso_ctrl = rtl838x_port_iso_ctrl,
|
||||
.l2_ctrl_0 = RTL838X_L2_CTRL_0,
|
||||
.l2_ctrl_1 = RTL838X_L2_CTRL_1,
|
||||
.l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT,
|
||||
.smi_poll_ctrl = RTL838X_SMI_POLL_CTRL,
|
||||
.l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
|
||||
.exec_tbl0_cmd = rtl838x_exec_tbl0_cmd,
|
||||
.exec_tbl1_cmd = rtl838x_exec_tbl1_cmd,
|
||||
.tbl_access_data_0 = rtl838x_tbl_access_data_0,
|
||||
.isr_glb_src = RTL838X_ISR_GLB_SRC,
|
||||
.isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG,
|
||||
.imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG,
|
||||
.imr_glb = RTL838X_IMR_GLB,
|
||||
.vlan_tables_read = rtl838x_vlan_tables_read,
|
||||
.vlan_set_tagged = rtl838x_vlan_set_tagged,
|
||||
.vlan_set_untagged = rtl838x_vlan_set_untagged,
|
||||
.mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl,
|
||||
.mac_port_ctrl = rtl838x_mac_port_ctrl,
|
||||
.l2_port_new_salrn = rtl838x_l2_port_new_salrn,
|
||||
.l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd,
|
||||
.mir_ctrl = rtl838x_mir_ctrl,
|
||||
.mir_dpm = rtl838x_mir_dpm,
|
||||
.mir_spm = rtl838x_mir_spm,
|
||||
.mac_link_sts = RTL838X_MAC_LINK_STS,
|
||||
.mac_link_dup_sts = RTL838X_MAC_LINK_DUP_STS,
|
||||
.mac_link_spd_sts = rtl838x_mac_link_spd_sts,
|
||||
.mac_rx_pause_sts = RTL838X_MAC_RX_PAUSE_STS,
|
||||
.mac_tx_pause_sts = RTL838X_MAC_TX_PAUSE_STS,
|
||||
.read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash,
|
||||
.read_cam = rtl838x_read_cam,
|
||||
.vlan_profile = rtl838x_vlan_profile,
|
||||
.vlan_port_egr_filter = rtl838x_vlan_port_egr_filter,
|
||||
.vlan_port_igr_filter = rtl838x_vlan_port_igr_filter,
|
||||
.vlan_port_pb = rtl838x_vlan_port_pb,
|
||||
.vlan_port_tag_sts_ctrl = rtl838x_vlan_port_tag_sts_ctrl,
|
||||
};
|
||||
|
||||
irqreturn_t rtl838x_switch_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct dsa_switch *ds = dev_id;
|
||||
u32 status = sw_r32(RTL838X_ISR_GLB_SRC);
|
||||
u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG);
|
||||
u32 link;
|
||||
int i;
|
||||
|
||||
/* Clear status */
|
||||
sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG);
|
||||
pr_debug("RTL8380 Link change: status: %x, ports %x\n", status, ports);
|
||||
|
||||
for (i = 0; i < 28; i++) {
|
||||
if (ports & BIT(i)) {
|
||||
link = sw_r32(RTL838X_MAC_LINK_STS);
|
||||
if (link & BIT(i))
|
||||
dsa_port_phylink_mac_change(ds, i, true);
|
||||
else
|
||||
dsa_port_phylink_mac_change(ds, i, false);
|
||||
}
|
||||
}
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
int rtl838x_smi_wait_op(int timeout)
|
||||
{
|
||||
do {
|
||||
timeout--;
|
||||
udelay(10);
|
||||
} while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & 0x1) && (timeout >= 0));
|
||||
if (timeout <= 0)
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Reads a register in a page from the PHY
|
||||
*/
|
||||
int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
|
||||
{
|
||||
u32 v;
|
||||
u32 park_page;
|
||||
|
||||
if (port > 31) {
|
||||
*val = 0xffff;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (page > 4095 || reg > 31)
|
||||
return -ENOTSUPP;
|
||||
|
||||
mutex_lock(&smi_lock);
|
||||
|
||||
if (rtl838x_smi_wait_op(10000))
|
||||
goto timeout;
|
||||
|
||||
sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
|
||||
|
||||
park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
|
||||
v = reg << 20 | page << 3;
|
||||
sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
|
||||
sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
|
||||
|
||||
if (rtl838x_smi_wait_op(10000))
|
||||
goto timeout;
|
||||
|
||||
*val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
|
||||
|
||||
mutex_unlock(&smi_lock);
|
||||
return 0;
|
||||
|
||||
timeout:
|
||||
mutex_unlock(&smi_lock);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write to a register in a page of the PHY
|
||||
*/
|
||||
int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
|
||||
{
|
||||
u32 v;
|
||||
u32 park_page;
|
||||
|
||||
val &= 0xffff;
|
||||
if (port > 31 || page > 4095 || reg > 31)
|
||||
return -ENOTSUPP;
|
||||
|
||||
mutex_lock(&smi_lock);
|
||||
if (rtl838x_smi_wait_op(10000))
|
||||
goto timeout;
|
||||
|
||||
sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);
|
||||
mdelay(10);
|
||||
|
||||
sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
|
||||
|
||||
park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
|
||||
v = reg << 20 | page << 3 | 0x4;
|
||||
sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
|
||||
sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
|
||||
|
||||
if (rtl838x_smi_wait_op(10000))
|
||||
goto timeout;
|
||||
|
||||
mutex_unlock(&smi_lock);
|
||||
return 0;
|
||||
|
||||
timeout:
|
||||
mutex_unlock(&smi_lock);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
void rtl8380_get_version(struct rtl838x_switch_priv *priv)
|
||||
{
|
||||
u32 rw_save, info_save;
|
||||
u32 info;
|
||||
|
||||
rw_save = sw_r32(RTL838X_INT_RW_CTRL);
|
||||
sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL);
|
||||
|
||||
info_save = sw_r32(RTL838X_CHIP_INFO);
|
||||
sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO);
|
||||
|
||||
info = sw_r32(RTL838X_CHIP_INFO);
|
||||
sw_w32(info_save, RTL838X_CHIP_INFO);
|
||||
sw_w32(rw_save, RTL838X_INT_RW_CTRL);
|
||||
|
||||
if ((info & 0xFFFF) == 0x6275) {
|
||||
if (((info >> 16) & 0x1F) == 0x1)
|
||||
priv->version = RTL8380_VERSION_A;
|
||||
else if (((info >> 16) & 0x1F) == 0x2)
|
||||
priv->version = RTL8380_VERSION_B;
|
||||
else
|
||||
priv->version = RTL8380_VERSION_B;
|
||||
} else {
|
||||
priv->version = '-';
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Applies the same hash algorithm as the one used currently by the ASIC
|
||||
*/
|
||||
u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed)
|
||||
{
|
||||
u32 h1, h2, h3, h;
|
||||
|
||||
if (sw_r32(priv->r->l2_ctrl_0) & 1) {
|
||||
h1 = (seed >> 11) & 0x7ff;
|
||||
h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
|
||||
|
||||
h2 = (seed >> 33) & 0x7ff;
|
||||
h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f);
|
||||
|
||||
h3 = (seed >> 44) & 0x7ff;
|
||||
h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf);
|
||||
|
||||
h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff);
|
||||
h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff);
|
||||
} else {
|
||||
h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff)
|
||||
^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
|
||||
^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff);
|
||||
}
|
||||
|
||||
return h;
|
||||
}
|
||||
|
||||
void rtl838x_vlan_profile_dump(int index)
|
||||
{
|
||||
u32 profile;
|
||||
|
||||
if (index < 0 || index > 7)
|
||||
return;
|
||||
|
||||
profile = sw_r32(RTL838X_VLAN_PROFILE(index));
|
||||
|
||||
pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \
|
||||
IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x",
|
||||
index, profile & 1, (profile >> 1) & 0x1ff, (profile >> 10) & 0x1ff,
|
||||
(profile >> 19) & 0x1ff);
|
||||
}
|
||||
293
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.h
Normal file
293
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.h
Normal file
@@ -0,0 +1,293 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _RTL838X_H
|
||||
#define _RTL838X_H
|
||||
|
||||
#include <net/dsa.h>
|
||||
|
||||
/*
|
||||
* Register definition
|
||||
*/
|
||||
#define RTL838X_CPU_PORT 28
|
||||
#define RTL839X_CPU_PORT 52
|
||||
|
||||
#define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7)))
|
||||
#define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7)))
|
||||
#define RTL838X_RST_GLB_CTRL_0 (0x003c)
|
||||
#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104)
|
||||
#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc)
|
||||
|
||||
#define RTL838X_DMY_REG31 (0x3b28)
|
||||
#define RTL838X_SDS_MODE_SEL (0x0028)
|
||||
#define RTL838X_SDS_CFG_REG (0x0034)
|
||||
#define RTL838X_INT_MODE_CTRL (0x005c)
|
||||
#define RTL838X_CHIP_INFO (0x00d8)
|
||||
#define RTL839X_CHIP_INFO (0x0ff4)
|
||||
#define RTL838X_SDS4_REG28 (0xef80)
|
||||
#define RTL838X_SDS4_DUMMY0 (0xef8c)
|
||||
#define RTL838X_SDS5_EXT_REG6 (0xf18c)
|
||||
#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2))
|
||||
#define RTL839X_PORT_ISO_CTRL(port) (0x1400 + ((port) << 3))
|
||||
#define RTL8380_SDS4_FIB_REG0 (0xF800)
|
||||
#define RTL838X_STAT_PORT_STD_MIB (0x1200)
|
||||
#define RTL839X_STAT_PORT_STD_MIB (0xC000)
|
||||
#define RTL838X_STAT_RST (0x3100)
|
||||
#define RTL839X_STAT_RST (0xF504)
|
||||
#define RTL838X_STAT_PORT_RST (0x3104)
|
||||
#define RTL839X_STAT_PORT_RST (0xF508)
|
||||
#define RTL838X_STAT_CTRL (0x3108)
|
||||
#define RTL839X_STAT_CTRL (0x04cc)
|
||||
|
||||
/* Registers of the internal Serdes of the 8390 */
|
||||
#define RTL8390_SDS0_1_XSG0 (0xA000)
|
||||
#define RTL8390_SDS0_1_XSG1 (0xA100)
|
||||
#define RTL839X_SDS12_13_XSG0 (0xB800)
|
||||
#define RTL839X_SDS12_13_XSG1 (0xB900)
|
||||
#define RTL839X_SDS12_13_PWR0 (0xb880)
|
||||
#define RTL839X_SDS12_13_PWR1 (0xb980)
|
||||
|
||||
/* Registers of the internal Serdes of the 8380 */
|
||||
#define MAPLE_SDS4_REG0r RTL838X_SDS4_REG28
|
||||
#define MAPLE_SDS5_REG0r (RTL838X_SDS4_REG28 + 0x100)
|
||||
#define MAPLE_SDS4_REG3r RTL838X_SDS4_DUMMY0
|
||||
#define MAPLE_SDS5_REG3r (RTL838X_SDS4_REG28 + 0x100)
|
||||
#define MAPLE_SDS4_FIB_REG0r (RTL838X_SDS4_REG28 + 0x880)
|
||||
#define MAPLE_SDS5_FIB_REG0r (RTL838X_SDS4_REG28 + 0x980)
|
||||
|
||||
/* VLAN registers */
|
||||
#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2))
|
||||
#define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84)
|
||||
#define RTL838X_VLAN_PORT_PB_VLAN(port) (0x3C00 + ((port) << 2))
|
||||
#define RTL838X_VLAN_PORT_IGR_FLTR(port) (0x3A7C + (((port >> 4) << 2)))
|
||||
#define RTL838X_VLAN_PORT_IGR_FLTR_0 (0x3A7C)
|
||||
#define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A7C + 4)
|
||||
#define RTL838X_VLAN_PORT_TAG_STS_CTRL(port) (0xA530 + (((port) << 2)))
|
||||
#define RTL839X_VLAN_PROFILE(idx) (0x25C0 + (((idx) << 3)))
|
||||
#define RTL839X_VLAN_CTRL (0x26D4)
|
||||
#define RTL839X_VLAN_PORT_PB_VLAN(port) (0x26D8 + (((port) << 2)))
|
||||
#define RTL839X_VLAN_PORT_IGR_FLTR(port) (0x27B4 + (((port >> 4) << 2)))
|
||||
#define RTL839X_VLAN_PORT_EGR_FLTR(port) (0x27C4 + (((port >> 5) << 2)))
|
||||
#define RTL839X_VLAN_PORT_TAG_STS_CTRL(port) (0x6828 + (((port) << 2)))
|
||||
|
||||
/* Table 0/1 access registers */
|
||||
#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914)
|
||||
#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2))
|
||||
#define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8)
|
||||
#define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2))
|
||||
#define RTL839X_TBL_ACCESS_CTRL_0 (0x1190)
|
||||
#define RTL839X_TBL_ACCESS_DATA_0(idx) (0x1194 + ((idx) << 2))
|
||||
#define RTL839X_TBL_ACCESS_CTRL_1 (0x6b80)
|
||||
#define RTL839X_TBL_ACCESS_DATA_1(idx) (0x6b84 + ((idx) << 2))
|
||||
|
||||
/* MAC handling */
|
||||
#define RTL838X_MAC_LINK_STS (0xa188)
|
||||
#define RTL839X_MAC_LINK_STS (0x0390)
|
||||
#define RTL838X_MAC_LINK_SPD_STS(port) (0xa190 + (((port >> 4) << 2)))
|
||||
#define RTL839X_MAC_LINK_SPD_STS(port) (0x03a0 + (((port >> 4) << 2)))
|
||||
#define RTL838X_MAC_LINK_DUP_STS (0xa19c)
|
||||
#define RTL839X_MAC_LINK_DUP_STS (0x03b0)
|
||||
#define RTL838X_MAC_TX_PAUSE_STS (0xa1a0)
|
||||
#define RTL839X_MAC_TX_PAUSE_STS (0x03b8)
|
||||
#define RTL838X_MAC_RX_PAUSE_STS (0xa1a4)
|
||||
#define RTL839X_MAC_RX_PAUSE_STS (0x03c0)
|
||||
#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04)
|
||||
#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08)
|
||||
|
||||
#define RTL838X_DMA_IF_CTRL (0x9f58)
|
||||
|
||||
/* MAC link state bits */
|
||||
#define FORCE_EN (1 << 0)
|
||||
#define FORCE_LINK_EN (1 << 1)
|
||||
#define NWAY_EN (1 << 2)
|
||||
#define DUPLX_MODE (1 << 3)
|
||||
#define TX_PAUSE_EN (1 << 6)
|
||||
#define RX_PAUSE_EN (1 << 7)
|
||||
|
||||
/* EEE */
|
||||
#define RTL838X_MAC_EEE_ABLTY (0xa1a8)
|
||||
#define RTL838X_EEE_PORT_TX_EN (0x014c)
|
||||
#define RTL838X_EEE_PORT_RX_EN (0x0150)
|
||||
#define RTL838X_EEE_CLK_STOP_CTRL (0x0148)
|
||||
|
||||
/* L2 functionality */
|
||||
#define RTL838X_L2_CTRL_0 (0x3200)
|
||||
#define RTL839X_L2_CTRL_0 (0x3800)
|
||||
#define RTL838X_L2_CTRL_1 (0x3204)
|
||||
#define RTL839X_L2_CTRL_1 (0x3804)
|
||||
#define RTL838X_L2_PORT_AGING_OUT (0x3358)
|
||||
#define RTL839X_L2_PORT_AGING_OUT (0x3b74)
|
||||
#define RTL838X_TBL_ACCESS_L2_CTRL (0x6900)
|
||||
#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180)
|
||||
#define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2))
|
||||
#define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2))
|
||||
#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370)
|
||||
#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0)
|
||||
#define RTL838X_L2_PORT_NEW_SALRN(p) (0x328c + (((p >> 4) << 2)))
|
||||
#define RTL839X_L2_PORT_NEW_SALRN(p) (0x38F0 + (((p >> 4) << 2)))
|
||||
#define RTL838X_L2_PORT_NEW_SA_FWD(p) (0x3294 + (((p >> 4) << 2)))
|
||||
#define RTL839X_L2_PORT_NEW_SA_FWD(p) (0x3900 + (((p >> 4) << 2)))
|
||||
#define RTL838X_L2_PORT_SALRN(p) (0x328c + (((p >> 4) << 2)))
|
||||
#define RTL839X_L2_PORT_SALRN(p) (0x38F0 + (((p >> 4) << 2)))
|
||||
|
||||
/* Port Mirroring */
|
||||
#define RTL838X_MIR_CTRL(grp) (0x5D00 + (((grp) << 2)))
|
||||
#define RTL838X_MIR_DPM_CTRL(grp) (0x5D20 + (((grp) << 2)))
|
||||
#define RTL838X_MIR_SPM_CTRL(grp) (0x5D10 + (((grp) << 2)))
|
||||
#define RTL839X_MIR_CTRL(grp) (0x2500 + (((grp) << 2)))
|
||||
#define RTL839X_MIR_DPM_CTRL(grp) (0x2530 + (((grp) << 2)))
|
||||
#define RTL839X_MIR_SPM_CTRL(grp) (0x2510 + (((grp) << 2)))
|
||||
|
||||
/* Storm control */
|
||||
#define RTL838X_STORM_CTRL (0x4700)
|
||||
#define RTL839X_STORM_CTRL (0x1800)
|
||||
#define RTL838X_STORM_CTRL_LB_CTRL(p) (0x4884 + (((p) << 2)))
|
||||
#define RTL838X_STORM_CTRL_BURST_PPS_0 (0x4874)
|
||||
#define RTL838X_STORM_CTRL_BURST_PPS_1 (0x4878)
|
||||
#define RTL838X_STORM_CTRL_BURST_0 (0x487c)
|
||||
#define RTL838X_STORM_CTRL_BURST_1 (0x4880)
|
||||
#define RTL838X_SCHED_CTRL (0xB980)
|
||||
#define RTL838X_SCHED_LB_TICK_TKN_CTRL_0 (0xAD58)
|
||||
#define RTL838X_SCHED_LB_TICK_TKN_CTRL_1 (0xAD5C)
|
||||
#define RTL839X_SCHED_LB_TICK_TKN_CTRL_0 (0x1804)
|
||||
#define RTL839X_SCHED_LB_TICK_TKN_CTRL_1 (0x1808)
|
||||
#define RTL838X_SCHED_LB_THR (0xB984)
|
||||
#define RTL838X_STORM_CTRL_PORT_BC_EXCEED (0x470C)
|
||||
#define RTL838X_STORM_CTRL_PORT_MC_EXCEED (0x4710)
|
||||
#define RTL838X_STORM_CTRL_PORT_UC_EXCEED (0x4714)
|
||||
#define RTL839X_STORM_CTRL_PORT_BC_EXCEED(p) (0x180c + (((p >> 5) << 2)))
|
||||
#define RTL839X_STORM_CTRL_PORT_MC_EXCEED(p) (0x1814 + (((p >> 5) << 2)))
|
||||
#define RTL839X_STORM_CTRL_PORT_UC_EXCEED(p) (0x181c + (((p >> 5) << 2)))
|
||||
#define RTL838X_STORM_CTRL_PORT_UC(p) (0x4718 + (((p) << 2)))
|
||||
#define RTL838X_STORM_CTRL_PORT_MC(p) (0x478c + (((p) << 2)))
|
||||
#define RTL838X_STORM_CTRL_PORT_BC(p) (0x4800 + (((p) << 2)))
|
||||
|
||||
/* Attack prevention */
|
||||
#define RTL838X_ATK_PRVNT_PORT_EN (0x5B00)
|
||||
#define RTL838X_ATK_PRVNT_CTRL (0x5B04)
|
||||
#define RTL838X_ATK_PRVNT_ACT (0x5B08)
|
||||
#define RTL838X_ATK_PRVNT_STS (0x5B1C)
|
||||
|
||||
enum phy_type {
|
||||
PHY_NONE = 0,
|
||||
PHY_RTL838X_SDS = 1,
|
||||
PHY_RTL8218B_INT = 2,
|
||||
PHY_RTL8218B_EXT = 3,
|
||||
PHY_RTL8214FC = 4,
|
||||
PHY_RTL839X_SDS = 5,
|
||||
};
|
||||
|
||||
struct rtl838x_port {
|
||||
bool enable;
|
||||
u64 pm;
|
||||
u16 pvid;
|
||||
bool eee_enabled;
|
||||
enum phy_type phy;
|
||||
const struct dsa_port *dp;
|
||||
};
|
||||
|
||||
struct rtl838x_vlan_info {
|
||||
u64 untagged_ports;
|
||||
u64 tagged_ports;
|
||||
u8 profile_id;
|
||||
bool hash_mc_fid;
|
||||
bool hash_uc_fid;
|
||||
u8 fid;
|
||||
};
|
||||
|
||||
enum l2_entry_type {
|
||||
L2_INVALID = 0,
|
||||
L2_UNICAST = 1,
|
||||
L2_MULTICAST = 2,
|
||||
IP4_MULTICAST = 3,
|
||||
IP6_MULTICAST = 4,
|
||||
};
|
||||
|
||||
struct rtl838x_l2_entry {
|
||||
u8 mac[6];
|
||||
u16 vid;
|
||||
u16 rvid;
|
||||
u8 port;
|
||||
bool valid;
|
||||
enum l2_entry_type type;
|
||||
bool is_static;
|
||||
bool is_ip_mc;
|
||||
bool is_ipv6_mc;
|
||||
bool block_da;
|
||||
bool block_sa;
|
||||
bool suspended;
|
||||
bool next_hop;
|
||||
int age;
|
||||
u16 mc_portmask_index;
|
||||
};
|
||||
|
||||
struct rtl838x_switch_priv;
|
||||
|
||||
struct rtl838x_reg {
|
||||
void (*mask_port_reg_be)(u64 clear, u64 set, int reg);
|
||||
void (*set_port_reg_be)(u64 set, int reg);
|
||||
u64 (*get_port_reg_be)(int reg);
|
||||
void (*mask_port_reg_le)(u64 clear, u64 set, int reg);
|
||||
void (*set_port_reg_le)(u64 set, int reg);
|
||||
u64 (*get_port_reg_le)(int reg);
|
||||
int stat_port_rst;
|
||||
int stat_rst;
|
||||
int (*stat_port_std_mib)(int p);
|
||||
int (*port_iso_ctrl)(int p);
|
||||
int l2_ctrl_0;
|
||||
int l2_ctrl_1;
|
||||
int l2_port_aging_out;
|
||||
int smi_poll_ctrl;
|
||||
int l2_tbl_flush_ctrl;
|
||||
void (*exec_tbl0_cmd)(u32 cmd);
|
||||
void (*exec_tbl1_cmd)(u32 cmd);
|
||||
int (*tbl_access_data_0)(int i);
|
||||
int isr_glb_src;
|
||||
int isr_port_link_sts_chg;
|
||||
int imr_port_link_sts_chg;
|
||||
int imr_glb;
|
||||
void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
|
||||
void (*vlan_set_tagged)(u32 vlan, struct rtl838x_vlan_info *info);
|
||||
void (*vlan_set_untagged)(u32 vlan, u64 portmask);
|
||||
int (*mac_force_mode_ctrl)(int port);
|
||||
int (*mac_port_ctrl)(int port);
|
||||
int (*l2_port_new_salrn)(int port);
|
||||
int (*l2_port_new_sa_fwd)(int port);
|
||||
int (*mir_ctrl)(int group);
|
||||
int (*mir_dpm)(int group);
|
||||
int (*mir_spm)(int group);
|
||||
int mac_link_sts;
|
||||
int mac_link_dup_sts;
|
||||
int (*mac_link_spd_sts)(int port);
|
||||
int mac_rx_pause_sts;
|
||||
int mac_tx_pause_sts;
|
||||
u64 (*read_l2_entry_using_hash)(u32 hash, u32 position, struct rtl838x_l2_entry *e);
|
||||
u64 (*read_cam)(int idx, struct rtl838x_l2_entry *e);
|
||||
int (*vlan_profile)(int profile);
|
||||
int (*vlan_port_egr_filter)(int port);
|
||||
int (*vlan_port_igr_filter)(int port);
|
||||
int (*vlan_port_pb)(int port);
|
||||
int (*vlan_port_tag_sts_ctrl)(int port);
|
||||
};
|
||||
|
||||
struct rtl838x_switch_priv {
|
||||
/* Switch operation */
|
||||
struct dsa_switch *ds;
|
||||
struct device *dev;
|
||||
u16 id;
|
||||
u16 family_id;
|
||||
char version;
|
||||
struct rtl838x_port ports[54]; /* TODO: correct size! */
|
||||
struct mutex reg_mutex;
|
||||
int link_state_irq;
|
||||
int mirror_group_ports[4];
|
||||
struct mii_bus *mii_bus;
|
||||
const struct rtl838x_reg *r;
|
||||
u8 cpu_port;
|
||||
u8 port_mask;
|
||||
u32 fib_entries;
|
||||
struct dentry *dbgfs_dir;
|
||||
};
|
||||
|
||||
void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv);
|
||||
|
||||
#endif /* _RTL838X_H */
|
||||
514
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c
Normal file
514
target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c
Normal file
@@ -0,0 +1,514 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include <asm/mach-rtl838x/mach-rtl83xx.h>
|
||||
#include "rtl83xx.h"
|
||||
|
||||
extern struct mutex smi_lock;
|
||||
|
||||
|
||||
static inline void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg)
|
||||
{
|
||||
sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg);
|
||||
sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4);
|
||||
}
|
||||
|
||||
static inline u64 rtl839x_get_port_reg_be(int reg)
|
||||
{
|
||||
u64 v = sw_r32(reg);
|
||||
|
||||
v <<= 32;
|
||||
v |= sw_r32(reg + 4);
|
||||
return v;
|
||||
}
|
||||
|
||||
static inline void rtl839x_set_port_reg_be(u64 set, int reg)
|
||||
{
|
||||
sw_w32(set >> 32, reg);
|
||||
sw_w32(set & 0xffffffff, reg + 4);
|
||||
}
|
||||
|
||||
static inline void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg)
|
||||
{
|
||||
sw_w32_mask((u32)clear, (u32)set, reg);
|
||||
sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4);
|
||||
}
|
||||
|
||||
static inline void rtl839x_set_port_reg_le(u64 set, int reg)
|
||||
{
|
||||
sw_w32(set, reg);
|
||||
sw_w32(set >> 32, reg + 4);
|
||||
}
|
||||
|
||||
static inline u64 rtl839x_get_port_reg_le(int reg)
|
||||
{
|
||||
u64 v = sw_r32(reg + 4);
|
||||
|
||||
v <<= 32;
|
||||
v |= sw_r32(reg);
|
||||
return v;
|
||||
}
|
||||
|
||||
static inline int rtl839x_stat_port_std_mib(int p)
|
||||
{
|
||||
return RTL839X_STAT_PORT_STD_MIB + (p << 8);
|
||||
}
|
||||
|
||||
static inline int rtl839x_port_iso_ctrl(int p)
|
||||
{
|
||||
return RTL839X_PORT_ISO_CTRL(p);
|
||||
}
|
||||
|
||||
static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
|
||||
{
|
||||
sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
|
||||
do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
|
||||
}
|
||||
|
||||
static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
|
||||
{
|
||||
sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
|
||||
do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
|
||||
}
|
||||
|
||||
static inline int rtl839x_tbl_access_data_0(int i)
|
||||
{
|
||||
return RTL839X_TBL_ACCESS_DATA_0(i);
|
||||
}
|
||||
|
||||
static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
|
||||
{
|
||||
u32 cmd;
|
||||
u64 v;
|
||||
u32 u, w;
|
||||
|
||||
cmd = BIT(16) /* Execute cmd */
|
||||
| 0 << 15 /* Read */
|
||||
| 0 << 12 /* Table type 0b000 */
|
||||
| (vlan & 0xfff);
|
||||
rtl839x_exec_tbl0_cmd(cmd);
|
||||
|
||||
v = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0));
|
||||
v <<= 32;
|
||||
u = sw_r32(RTL838X_TBL_ACCESS_DATA_0(1));
|
||||
v |= u;
|
||||
info->tagged_ports = v >> 11;
|
||||
|
||||
w = sw_r32(RTL838X_TBL_ACCESS_DATA_0(2));
|
||||
|
||||
info->profile_id = w >> 30 | ((u & 1) << 2);
|
||||
info->hash_mc_fid = !!(u & 2);
|
||||
info->hash_uc_fid = !!(u & 4);
|
||||
info->fid = (u >> 3) & 0xff;
|
||||
|
||||
cmd = BIT(16) /* Execute cmd */
|
||||
| 0 << 15 /* Read */
|
||||
| 0 << 12 /* Table type 0b000 */
|
||||
| (vlan & 0xfff);
|
||||
rtl839x_exec_tbl1_cmd(cmd);
|
||||
v = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0));
|
||||
v <<= 32;
|
||||
v |= sw_r32(RTL838X_TBL_ACCESS_DATA_1(1));
|
||||
info->untagged_ports = v >> 11;
|
||||
}
|
||||
|
||||
static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
|
||||
{
|
||||
u32 cmd = BIT(16) /* Execute cmd */
|
||||
| BIT(15) /* Write */
|
||||
| 0 << 12 /* Table type 0b00 */
|
||||
| (vlan & 0xfff);
|
||||
u32 w;
|
||||
u64 v = info->tagged_ports << 11;
|
||||
|
||||
v |= info->profile_id >> 2;
|
||||
v |= info->hash_mc_fid ? 2 : 0;
|
||||
v |= info->hash_uc_fid ? 4 : 0;
|
||||
v |= ((u32)info->fid) << 3;
|
||||
rtl839x_set_port_reg_be(v, RTL838X_TBL_ACCESS_DATA_0(0));
|
||||
|
||||
w = info->profile_id;
|
||||
sw_w32(w << 30, RTL838X_TBL_ACCESS_DATA_0(2));
|
||||
rtl839x_exec_tbl0_cmd(cmd);
|
||||
}
|
||||
|
||||
static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
|
||||
{
|
||||
u32 cmd = BIT(16) /* Execute cmd */
|
||||
| BIT(15) /* Write */
|
||||
| 0 << 12 /* Table type 0b00 */
|
||||
| (vlan & 0xfff);
|
||||
rtl839x_set_port_reg_be(portmask << 11, RTL838X_TBL_ACCESS_DATA_1(0));
|
||||
rtl839x_exec_tbl1_cmd(cmd);
|
||||
}
|
||||
|
||||
static inline int rtl839x_mac_force_mode_ctrl(int p)
|
||||
{
|
||||
return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
|
||||
}
|
||||
|
||||
static inline int rtl839x_mac_port_ctrl(int p)
|
||||
{
|
||||
return RTL839X_MAC_PORT_CTRL(p);
|
||||
}
|
||||
|
||||
static inline int rtl839x_l2_port_new_salrn(int p)
|
||||
{
|
||||
return RTL839X_L2_PORT_NEW_SALRN(p);
|
||||
}
|
||||
|
||||
static inline int rtl839x_l2_port_new_sa_fwd(int p)
|
||||
{
|
||||
return RTL839X_L2_PORT_NEW_SA_FWD(p);
|
||||
}
|
||||
|
||||
static inline int rtl839x_mir_ctrl(int group)
|
||||
{
|
||||
return RTL839X_MIR_CTRL(group);
|
||||
}
|
||||
|
||||
static inline int rtl839x_mir_dpm(int group)
|
||||
{
|
||||
return RTL839X_MIR_DPM_CTRL(group);
|
||||
}
|
||||
|
||||
static inline int rtl839x_mir_spm(int group)
|
||||
{
|
||||
return RTL839X_MIR_SPM_CTRL(group);
|
||||
}
|
||||
|
||||
static inline int rtl839x_mac_link_spd_sts(int p)
|
||||
{
|
||||
return RTL839X_MAC_LINK_SPD_STS(p);
|
||||
}
|
||||
|
||||
static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
|
||||
{
|
||||
u64 entry;
|
||||
u32 r[3];
|
||||
|
||||
/* Search in SRAM, with hash and at position in hash bucket (0-3) */
|
||||
u32 idx = (0 << 14) | (hash << 2) | position;
|
||||
|
||||
u32 cmd = BIT(17) /* Execute cmd */
|
||||
| 0 << 16 /* Read */
|
||||
| 0 << 14 /* Table type 0b00 */
|
||||
| (idx & 0x3fff);
|
||||
|
||||
sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
|
||||
do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & BIT(17));
|
||||
r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
|
||||
r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
|
||||
r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
|
||||
|
||||
/* Table contains different entry types, we need to identify the right one:
|
||||
* Check for MC entries, first
|
||||
*/
|
||||
e->is_ip_mc = !!(r[2] & BIT(31));
|
||||
e->is_ipv6_mc = !!(r[2] & BIT(30));
|
||||
e->type = L2_INVALID;
|
||||
if (!e->is_ip_mc) {
|
||||
e->mac[0] = (r[0] >> 12);
|
||||
e->mac[1] = (r[0] >> 4);
|
||||
e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
|
||||
e->mac[3] = (r[1] >> 20);
|
||||
e->mac[4] = (r[1] >> 12);
|
||||
e->mac[5] = (r[1] >> 4);
|
||||
|
||||
/* Is it a unicast entry? check multicast bit */
|
||||
if (!(e->mac[0] & 1)) {
|
||||
e->is_static = !!((r[2] >> 18) & 1);
|
||||
e->vid = (r[2] >> 4) & 0xfff;
|
||||
e->rvid = (r[0] >> 20) & 0xfff;
|
||||
e->port = (r[2] >> 24) & 0x3f;
|
||||
e->block_da = !!(r[2] & BIT(19));
|
||||
e->block_sa = !!(r[2] & BIT(20));
|
||||
e->suspended = !!(r[2] & BIT(17));
|
||||
e->next_hop = !!(r[2] & BIT(16));
|
||||
if (e->next_hop)
|
||||
pr_debug("Found next hop entry, need to read data\n");
|
||||
e->age = (r[2] >> 21) & 3;
|
||||
e->valid = true;
|
||||
if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
|
||||
e->valid = false;
|
||||
else
|
||||
e->type = L2_UNICAST;
|
||||
} else {
|
||||
e->valid = true;
|
||||
e->type = L2_MULTICAST;
|
||||
e->mc_portmask_index = (r[2]>>6) & 0xfff;
|
||||
}
|
||||
}
|
||||
if (e->is_ip_mc) {
|
||||
e->valid = true;
|
||||
e->type = IP4_MULTICAST;
|
||||
}
|
||||
if (e->is_ipv6_mc) {
|
||||
e->valid = true;
|
||||
e->type = IP6_MULTICAST;
|
||||
}
|
||||
|
||||
entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
|
||||
return entry;
|
||||
}
|
||||
|
||||
static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
|
||||
{
|
||||
u64 entry;
|
||||
u32 r[3];
|
||||
|
||||
u32 cmd = BIT(17) /* Execute cmd */
|
||||
| 0 << 16 /* Read */
|
||||
| BIT(14) /* Table type 0b01 */
|
||||
| (idx & 0x3f);
|
||||
sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
|
||||
do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & BIT(17));
|
||||
r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
|
||||
r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
|
||||
r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
|
||||
|
||||
e->mac[0] = (r[0] >> 12);
|
||||
e->mac[1] = (r[0] >> 4);
|
||||
e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
|
||||
e->mac[3] = (r[1] >> 20);
|
||||
e->mac[4] = (r[1] >> 12);
|
||||
e->mac[5] = (r[1] >> 4);
|
||||
e->is_static = !!((r[2] >> 18) & 1);
|
||||
e->vid = (r[2] >> 4) & 0xfff;
|
||||
e->rvid = (r[0] >> 20) & 0xfff;
|
||||
e->port = (r[2] >> 24) & 0x3f;
|
||||
|
||||
e->valid = true;
|
||||
if (!(r[2] & 0x10fd0000)) /* Check for invalid entry */
|
||||
e->valid = false;
|
||||
|
||||
if (e->valid)
|
||||
pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
|
||||
|
||||
entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
|
||||
return entry;
|
||||
}
|
||||
|
||||
static inline int rtl839x_vlan_profile(int profile)
|
||||
{
|
||||
return RTL839X_VLAN_PROFILE(profile);
|
||||
}
|
||||
|
||||
static inline int rtl839x_vlan_port_egr_filter(int port)
|
||||
{
|
||||
return RTL839X_VLAN_PORT_EGR_FLTR(port);
|
||||
}
|
||||
|
||||
static inline int rtl839x_vlan_port_igr_filter(int port)
|
||||
{
|
||||
return RTL839X_VLAN_PORT_IGR_FLTR(port);
|
||||
}
|
||||
|
||||
static inline int rtl839x_vlan_port_pb(int port)
|
||||
{
|
||||
return RTL839X_VLAN_PORT_PB_VLAN(port);
|
||||
}
|
||||
|
||||
static inline int rtl839x_vlan_port_tag_sts_ctrl(int port)
|
||||
{
|
||||
return RTL839X_VLAN_PORT_TAG_STS_CTRL(port);
|
||||
}
|
||||
|
||||
const struct rtl838x_reg rtl839x_reg = {
|
||||
.mask_port_reg_be = rtl839x_mask_port_reg_be,
|
||||
.set_port_reg_be = rtl839x_set_port_reg_be,
|
||||
.get_port_reg_be = rtl839x_get_port_reg_be,
|
||||
.mask_port_reg_le = rtl839x_mask_port_reg_le,
|
||||
.set_port_reg_le = rtl839x_set_port_reg_le,
|
||||
.get_port_reg_le = rtl839x_get_port_reg_le,
|
||||
.stat_port_rst = RTL839X_STAT_PORT_RST,
|
||||
.stat_rst = RTL839X_STAT_RST,
|
||||
.stat_port_std_mib = rtl839x_stat_port_std_mib,
|
||||
.port_iso_ctrl = rtl839x_port_iso_ctrl,
|
||||
.l2_ctrl_0 = RTL839X_L2_CTRL_0,
|
||||
.l2_ctrl_1 = RTL839X_L2_CTRL_1,
|
||||
.l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
|
||||
.smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
|
||||
.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
|
||||
.exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
|
||||
.exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
|
||||
.tbl_access_data_0 = rtl839x_tbl_access_data_0,
|
||||
.isr_glb_src = RTL839X_ISR_GLB_SRC,
|
||||
.isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
|
||||
.imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
|
||||
.imr_glb = RTL839X_IMR_GLB,
|
||||
.vlan_tables_read = rtl839x_vlan_tables_read,
|
||||
.vlan_set_tagged = rtl839x_vlan_set_tagged,
|
||||
.vlan_set_untagged = rtl839x_vlan_set_untagged,
|
||||
.mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
|
||||
.mac_port_ctrl = rtl839x_mac_port_ctrl,
|
||||
.l2_port_new_salrn = rtl839x_l2_port_new_salrn,
|
||||
.l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
|
||||
.mir_ctrl = rtl839x_mir_ctrl,
|
||||
.mir_dpm = rtl839x_mir_dpm,
|
||||
.mir_spm = rtl839x_mir_spm,
|
||||
.mac_link_sts = RTL839X_MAC_LINK_STS,
|
||||
.mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
|
||||
.mac_link_spd_sts = rtl839x_mac_link_spd_sts,
|
||||
.mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
|
||||
.mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
|
||||
.read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
|
||||
.read_cam = rtl839x_read_cam,
|
||||
.vlan_profile = rtl839x_vlan_profile,
|
||||
.vlan_port_egr_filter = rtl839x_vlan_port_egr_filter,
|
||||
.vlan_port_igr_filter = rtl839x_vlan_port_igr_filter,
|
||||
.vlan_port_pb = rtl839x_vlan_port_pb,
|
||||
.vlan_port_tag_sts_ctrl = rtl839x_vlan_port_tag_sts_ctrl,
|
||||
};
|
||||
|
||||
irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct dsa_switch *ds = dev_id;
|
||||
u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
|
||||
u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
|
||||
u64 link;
|
||||
int i;
|
||||
|
||||
/* Clear status */
|
||||
rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
|
||||
pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
|
||||
|
||||
for (i = 0; i < 52; i++) {
|
||||
if (ports & (1ULL << i)) {
|
||||
link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
|
||||
if (link & (1ULL << i))
|
||||
dsa_port_phylink_mac_change(ds, i, true);
|
||||
else
|
||||
dsa_port_phylink_mac_change(ds, i, false);
|
||||
}
|
||||
}
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
// TODO: unused
|
||||
int rtl8390_sds_power(int mac, int val)
|
||||
{
|
||||
u32 offset = (mac == 48) ? 0x0 : 0x100;
|
||||
u32 mode = val ? 0 : 1;
|
||||
|
||||
pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
|
||||
|
||||
if ((mac != 48) && (mac != 49)) {
|
||||
pr_err("%s: not an SFP port: %d\n", __func__, mac);
|
||||
return -1;
|
||||
}
|
||||
|
||||
// Set bit 1003. 1000 starts at 7c
|
||||
sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
if (port > 63 || page > 4095 || reg > 31)
|
||||
return -ENOTSUPP;
|
||||
|
||||
mutex_lock(&smi_lock);
|
||||
|
||||
sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
|
||||
v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
|
||||
sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
|
||||
|
||||
sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
|
||||
|
||||
v |= 1;
|
||||
sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
|
||||
|
||||
do {
|
||||
} while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
|
||||
|
||||
*val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
|
||||
|
||||
mutex_unlock(&smi_lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
|
||||
{
|
||||
u32 v;
|
||||
int err = 0;
|
||||
|
||||
val &= 0xffff;
|
||||
if (port > 63 || page > 4095 || reg > 31)
|
||||
return -ENOTSUPP;
|
||||
|
||||
mutex_lock(&smi_lock);
|
||||
/* Clear both port registers */
|
||||
sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0));
|
||||
sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0) + 4);
|
||||
sw_w32_mask(0, BIT(port), RTL839X_PHYREG_PORT_CTRL(port));
|
||||
|
||||
sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
|
||||
|
||||
v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
|
||||
sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
|
||||
|
||||
sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
|
||||
|
||||
v |= BIT(3) | 1; /* Write operation and execute */
|
||||
sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
|
||||
|
||||
do {
|
||||
} while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
|
||||
|
||||
if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
|
||||
err = -EIO;
|
||||
|
||||
mutex_unlock(&smi_lock);
|
||||
return err;
|
||||
}
|
||||
|
||||
void rtl8390_get_version(struct rtl838x_switch_priv *priv)
|
||||
{
|
||||
u32 info;
|
||||
|
||||
sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
|
||||
info = sw_r32(RTL839X_CHIP_INFO);
|
||||
pr_debug("Chip-Info: %x\n", info);
|
||||
priv->version = RTL8390_VERSION_A;
|
||||
}
|
||||
|
||||
u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed)
|
||||
{
|
||||
u32 h1, h2, h;
|
||||
|
||||
if (sw_r32(priv->r->l2_ctrl_0) & 1) {
|
||||
h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f)
|
||||
^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f)
|
||||
^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
|
||||
h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f)
|
||||
^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f)
|
||||
^ (seed & 0x3f));
|
||||
h = (h1 << 6) | h2;
|
||||
} else {
|
||||
h = (seed >> 60)
|
||||
^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f))
|
||||
^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff)
|
||||
^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
|
||||
}
|
||||
|
||||
return h;
|
||||
}
|
||||
|
||||
void rtl839x_vlan_profile_dump(int index)
|
||||
{
|
||||
u32 profile, profile1;
|
||||
|
||||
if (index < 0 || index > 7)
|
||||
return;
|
||||
|
||||
profile1 = sw_r32(RTL839X_VLAN_PROFILE(index) + 4);
|
||||
profile = sw_r32(RTL839X_VLAN_PROFILE(index));
|
||||
|
||||
pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \
|
||||
IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x",
|
||||
index, profile & 1, (profile >> 1) & 0xfff, (profile >> 13) & 0xfff,
|
||||
(profile1) & 0xfff);
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _NET_DSA_RTL83XX_H
|
||||
#define _NET_DSA_RTL83XX_H
|
||||
|
||||
#include <net/dsa.h>
|
||||
#include "rtl838x.h"
|
||||
|
||||
|
||||
#define RTL8380_VERSION_A 'A'
|
||||
#define RTL8390_VERSION_A 'A'
|
||||
#define RTL8380_VERSION_B 'B'
|
||||
|
||||
struct fdb_update_work {
|
||||
struct work_struct work;
|
||||
struct net_device *ndev;
|
||||
u64 macs[];
|
||||
};
|
||||
|
||||
#define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
|
||||
struct rtl83xx_mib_desc {
|
||||
unsigned int size;
|
||||
unsigned int offset;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
void __init rtl83xx_storm_control_init(struct rtl838x_switch_priv *priv);
|
||||
|
||||
/* RTL838x-specific */
|
||||
u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed);
|
||||
irqreturn_t rtl838x_switch_irq(int irq, void *dev_id);
|
||||
void rtl8380_get_version(struct rtl838x_switch_priv *priv);
|
||||
void rtl838x_vlan_profile_dump(int index);
|
||||
int rtl83xx_dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg);
|
||||
|
||||
/* RTL839x-specific */
|
||||
u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed);
|
||||
irqreturn_t rtl839x_switch_irq(int irq, void *dev_id);
|
||||
void rtl8390_get_version(struct rtl838x_switch_priv *priv);
|
||||
void rtl839x_vlan_profile_dump(int index);
|
||||
int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val);
|
||||
|
||||
#endif /* _NET_DSA_RTL83XX_H */
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include <asm/mach-rtl838x/mach-rtl83xx.h>
|
||||
#include "rtl83xx.h"
|
||||
|
||||
|
||||
static void rtl83xx_storm_enable(struct rtl838x_switch_priv *priv, int port, bool enable)
|
||||
{
|
||||
// Enable Storm control for that port for UC, MC, and BC
|
||||
if (enable)
|
||||
sw_w32(0x7, RTL838X_STORM_CTRL_LB_CTRL(port));
|
||||
else
|
||||
sw_w32(0x0, RTL838X_STORM_CTRL_LB_CTRL(port));
|
||||
}
|
||||
|
||||
void __init rtl83xx_storm_control_init(struct rtl838x_switch_priv *priv)
|
||||
{
|
||||
int i;
|
||||
|
||||
pr_debug("Enabling Storm control\n");
|
||||
// TICK_PERIOD_PPS
|
||||
if (priv->id == 0x8380)
|
||||
sw_w32_mask(0x3ff << 20, 434 << 20, RTL838X_SCHED_LB_TICK_TKN_CTRL_0);
|
||||
|
||||
// Set burst rate
|
||||
sw_w32(0x00008000, RTL838X_STORM_CTRL_BURST_0); // UC
|
||||
sw_w32(0x80008000, RTL838X_STORM_CTRL_BURST_1); // MC and BC
|
||||
|
||||
// Set burst Packets per Second to 32
|
||||
sw_w32(0x00000020, RTL838X_STORM_CTRL_BURST_PPS_0); // UC
|
||||
sw_w32(0x00200020, RTL838X_STORM_CTRL_BURST_PPS_1); // MC and BC
|
||||
|
||||
// Include IFG in storm control
|
||||
sw_w32_mask(0, BIT(6), RTL838X_STORM_CTRL);
|
||||
// Rate control is based on bytes/s (0 = packets)
|
||||
sw_w32_mask(0, BIT(5), RTL838X_STORM_CTRL);
|
||||
// Bandwidth control includes preamble and IFG (10 Bytes)
|
||||
sw_w32_mask(0, 1, RTL838X_SCHED_CTRL);
|
||||
|
||||
// On SoCs except RTL8382M, set burst size of port egress
|
||||
if (priv->id != 0x8382)
|
||||
sw_w32_mask(0xffff, 0x800, RTL838X_SCHED_LB_THR);
|
||||
|
||||
/* Enable storm control on all ports with a PHY and limit rates,
|
||||
* for UC and MC for both known and unknown addresses */
|
||||
for (i = 0; i < priv->cpu_port; i++) {
|
||||
if (priv->ports[i].phy) {
|
||||
sw_w32(BIT(18) | 0x8000, RTL838X_STORM_CTRL_PORT_UC(i));
|
||||
sw_w32(BIT(18) | 0x8000, RTL838X_STORM_CTRL_PORT_MC(i));
|
||||
sw_w32(0x000, RTL838X_STORM_CTRL_PORT_BC(i));
|
||||
rtl83xx_storm_enable(priv, i, true);
|
||||
}
|
||||
}
|
||||
|
||||
// Attack prevention, enable all attack prevention measures
|
||||
//sw_w32(0x1ffff, RTL838X_ATK_PRVNT_CTRL);
|
||||
/* Attack prevention, drop (bit = 0) problematic packets on all ports.
|
||||
* Setting bit = 1 means: trap to CPU
|
||||
*/
|
||||
//sw_w32(0, RTL838X_ATK_PRVNT_ACT);
|
||||
// Enable attack prevention on all ports
|
||||
//sw_w32(0x0fffffff, RTL838X_ATK_PRVNT_PORT_EN);
|
||||
}
|
||||
|
||||
1543
target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.c
Normal file
1543
target/linux/realtek/files-5.4/drivers/net/ethernet/rtl838x_eth.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,279 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _RTL838X_ETH_H
|
||||
#define _RTL838X_ETH_H
|
||||
|
||||
/*
|
||||
* Register definition
|
||||
*/
|
||||
|
||||
#define RTL838X_CPU_PORT 28
|
||||
#define RTL839X_CPU_PORT 52
|
||||
|
||||
#define RTL838X_MAC_PORT_CTRL (0xd560)
|
||||
#define RTL839X_MAC_PORT_CTRL (0x8004)
|
||||
#define RTL838X_DMA_IF_INTR_STS (0x9f54)
|
||||
#define RTL839X_DMA_IF_INTR_STS (0x7868)
|
||||
#define RTL838X_DMA_IF_INTR_MSK (0x9f50)
|
||||
#define RTL839X_DMA_IF_INTR_MSK (0x7864)
|
||||
#define RTL838X_DMA_IF_CTRL (0x9f58)
|
||||
#define RTL839X_DMA_IF_CTRL (0x786c)
|
||||
#define RTL838X_RST_GLB_CTRL_0 (0x003c)
|
||||
#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104)
|
||||
#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc)
|
||||
|
||||
/* MAC address settings */
|
||||
#define RTL838X_MAC (0xa9ec)
|
||||
#define RTL839X_MAC (0x02b4)
|
||||
#define RTL838X_MAC_ALE (0x6b04)
|
||||
#define RTL838X_MAC2 (0xa320)
|
||||
|
||||
#define RTL838X_DMA_RX_BASE (0x9f00)
|
||||
#define RTL839X_DMA_RX_BASE (0x780c)
|
||||
#define RTL838X_DMA_TX_BASE (0x9f40)
|
||||
#define RTL839X_DMA_TX_BASE (0x784c)
|
||||
#define RTL838X_DMA_IF_RX_RING_SIZE (0xB7E4)
|
||||
#define RTL839X_DMA_IF_RX_RING_SIZE (0x6038)
|
||||
#define RTL838X_DMA_IF_RX_RING_CNTR (0xB7E8)
|
||||
#define RTL839X_DMA_IF_RX_RING_CNTR (0x603c)
|
||||
#define RTL838X_DMA_IF_RX_CUR (0x9F20)
|
||||
#define RTL839X_DMA_IF_RX_CUR (0x782c)
|
||||
|
||||
#define RTL838X_DMY_REG31 (0x3b28)
|
||||
#define RTL838X_SDS_MODE_SEL (0x0028)
|
||||
#define RTL838X_SDS_CFG_REG (0x0034)
|
||||
#define RTL838X_INT_MODE_CTRL (0x005c)
|
||||
#define RTL838X_CHIP_INFO (0x00d8)
|
||||
#define RTL838X_SDS4_REG28 (0xef80)
|
||||
#define RTL838X_SDS4_DUMMY0 (0xef8c)
|
||||
#define RTL838X_SDS5_EXT_REG6 (0xf18c)
|
||||
#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2))
|
||||
#define RTL838X_STAT_PORT_STD_MIB(port) (0x1200 + (((port) << 8)))
|
||||
#define RTL838X_STAT_RST (0x3100)
|
||||
#define RTL838X_STAT_CTRL (0x3108)
|
||||
|
||||
/* Registers of the internal Serdes of the 8380 */
|
||||
#define MAPLE_SDS4_REG0r RTL838X_SDS4_REG28
|
||||
#define MAPLE_SDS5_REG0r (RTL838X_SDS4_REG28 + 0x100)
|
||||
#define MAPLE_SDS4_REG3r RTL838X_SDS4_DUMMY0
|
||||
#define MAPLE_SDS5_REG3r (RTL838X_SDS4_REG28 + 0x100)
|
||||
#define MAPLE_SDS4_FIB_REG0r (RTL838X_SDS4_REG28 + 0x880)
|
||||
#define MAPLE_SDS5_FIB_REG0r (RTL838X_SDS4_REG28 + 0x980)
|
||||
|
||||
/* VLAN registers */
|
||||
#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2))
|
||||
#define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84)
|
||||
#define RTL838X_VLAN_PORT_PB_VLAN(port) (0x3C00 + ((port) << 2))
|
||||
#define RTL838X_VLAN_PORT_IGR_FLTR_0 (0x3A7C)
|
||||
#define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A7C + 4)
|
||||
#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914)
|
||||
#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2))
|
||||
#define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8)
|
||||
#define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2))
|
||||
#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180)
|
||||
#define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2))
|
||||
/* MAC handling */
|
||||
#define RTL838X_MAC_LINK_STS (0xa188)
|
||||
#define RTL839X_MAC_LINK_STS (0x0390)
|
||||
#define RTL838X_MAC_LINK_SPD_STS (0xa190)
|
||||
#define RTL839X_MAC_LINK_SPD_STS (0x03a0)
|
||||
#define RTL838X_MAC_LINK_DUP_STS (0xa19c)
|
||||
#define RTL839X_MAC_LINK_DUP_STS (0x03b0)
|
||||
// TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ???
|
||||
#define RTL838X_MAC_TX_PAUSE_STS (0xa1a0)
|
||||
#define RTL839X_MAC_TX_PAUSE_STS (0x03b8)
|
||||
#define RTL838X_MAC_RX_PAUSE_STS (0xa1a4)
|
||||
#define RTL839X_MAC_RX_PAUSE_STS (0x03c0)
|
||||
#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04)
|
||||
#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08)
|
||||
#define RTL839X_MAC_GLB_CTRL (0x02a8)
|
||||
#define RTL839X_SCHED_LB_TICK_TKN_CTRL (0x60f8)
|
||||
|
||||
#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370)
|
||||
#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0)
|
||||
|
||||
/* MAC link state bits */
|
||||
#define FORCE_EN (1 << 0)
|
||||
#define FORCE_LINK_EN (1 << 1)
|
||||
#define NWAY_EN (1 << 2)
|
||||
#define DUPLX_MODE (1 << 3)
|
||||
#define TX_PAUSE_EN (1 << 6)
|
||||
#define RX_PAUSE_EN (1 << 7)
|
||||
|
||||
/* RTL839X L2 Notification DMA interface */
|
||||
#define RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL (0x785C)
|
||||
#define RTL839X_L2_NOTIFICATION_CTRL (0x7808)
|
||||
#define RTL838X_L2_CTRL_0 (0x3200)
|
||||
#define RTL839X_L2_CTRL_0 (0x3800)
|
||||
|
||||
/* TRAPPING to CPU-PORT */
|
||||
#define RTL838X_SPCL_TRAP_IGMP_CTRL (0x6984)
|
||||
#define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058)
|
||||
#define RTL838X_RMA_CTRL_0 (0x4300)
|
||||
#define RTL838X_RMA_CTRL_1 (0x4304)
|
||||
#define RTL839X_RMA_CTRL_0 (0x1200)
|
||||
#define RTL839X_RMA_CTRL_1 (0x1204)
|
||||
#define RTL839X_RMA_CTRL_2 (0x1208)
|
||||
#define RTL839X_RMA_CTRL_3 (0x120C)
|
||||
|
||||
/* Registers of the internal Serdes of the 8390 */
|
||||
#define RTL839X_SDS12_13_XSG0 (0xB800)
|
||||
|
||||
|
||||
inline int rtl838x_mac_port_ctrl(int p)
|
||||
{
|
||||
return RTL838X_MAC_PORT_CTRL + (p << 7);
|
||||
}
|
||||
|
||||
inline int rtl839x_mac_port_ctrl(int p)
|
||||
{
|
||||
return RTL839X_MAC_PORT_CTRL + (p << 7);
|
||||
}
|
||||
|
||||
static inline int rtl838x_mac_force_mode_ctrl(int p)
|
||||
{
|
||||
return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
|
||||
}
|
||||
|
||||
static inline int rtl839x_mac_force_mode_ctrl(int p)
|
||||
{
|
||||
return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
|
||||
}
|
||||
|
||||
inline int rtl838x_dma_rx_base(int i)
|
||||
{
|
||||
return RTL838X_DMA_RX_BASE + (i << 2);
|
||||
}
|
||||
|
||||
inline int rtl839x_dma_rx_base(int i)
|
||||
{
|
||||
return RTL839X_DMA_RX_BASE + (i << 2);
|
||||
}
|
||||
|
||||
inline int rtl838x_dma_tx_base(int i)
|
||||
{
|
||||
return RTL838X_DMA_TX_BASE + (i << 2);
|
||||
}
|
||||
|
||||
inline int rtl839x_dma_tx_base(int i)
|
||||
{
|
||||
return RTL839X_DMA_TX_BASE + (i << 2);
|
||||
}
|
||||
|
||||
inline int rtl838x_dma_if_rx_ring_size(int i)
|
||||
{
|
||||
return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
|
||||
}
|
||||
|
||||
inline int rtl839x_dma_if_rx_ring_size(int i)
|
||||
{
|
||||
return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
|
||||
}
|
||||
|
||||
inline int rtl838x_dma_if_rx_ring_cntr(int i)
|
||||
{
|
||||
return RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
|
||||
}
|
||||
|
||||
inline int rtl839x_dma_if_rx_ring_cntr(int i)
|
||||
{
|
||||
return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
|
||||
}
|
||||
|
||||
|
||||
inline int rtl838x_dma_if_rx_cur(int i)
|
||||
{
|
||||
return RTL838X_DMA_IF_RX_CUR + (i << 2);
|
||||
}
|
||||
|
||||
inline int rtl839x_dma_if_rx_cur(int i)
|
||||
{
|
||||
return RTL839X_DMA_IF_RX_CUR + (i << 2);
|
||||
}
|
||||
|
||||
inline u32 rtl838x_get_mac_link_sts(int port)
|
||||
{
|
||||
return (sw_r32(RTL838X_MAC_LINK_STS) & (1 << port));
|
||||
}
|
||||
|
||||
inline u32 rtl839x_get_mac_link_sts(int p)
|
||||
{
|
||||
return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & (1 << p));
|
||||
}
|
||||
|
||||
inline u32 rtl838x_get_mac_link_dup_sts(int port)
|
||||
{
|
||||
return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & (1 << port));
|
||||
}
|
||||
|
||||
inline u32 rtl839x_get_mac_link_dup_sts(int p)
|
||||
{
|
||||
return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & (1 << p));
|
||||
}
|
||||
|
||||
inline u32 rtl838x_get_mac_link_spd_sts(int port)
|
||||
{
|
||||
int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
|
||||
u32 speed = sw_r32(r);
|
||||
|
||||
speed >>= (port % 16) << 1;
|
||||
return (speed & 0x3);
|
||||
}
|
||||
|
||||
inline u32 rtl839x_get_mac_link_spd_sts(int port)
|
||||
{
|
||||
int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
|
||||
u32 speed = sw_r32(r);
|
||||
|
||||
speed >>= (port % 16) << 1;
|
||||
return (speed & 0x3);
|
||||
}
|
||||
|
||||
inline u32 rtl838x_get_mac_rx_pause_sts(int port)
|
||||
{
|
||||
return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port));
|
||||
}
|
||||
|
||||
inline u32 rtl839x_get_mac_rx_pause_sts(int p)
|
||||
{
|
||||
return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p));
|
||||
}
|
||||
|
||||
inline u32 rtl838x_get_mac_tx_pause_sts(int port)
|
||||
{
|
||||
return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port));
|
||||
}
|
||||
|
||||
inline u32 rtl839x_get_mac_tx_pause_sts(int p)
|
||||
{
|
||||
return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p));
|
||||
}
|
||||
|
||||
|
||||
struct rtl838x_reg {
|
||||
int (*mac_port_ctrl)(int port);
|
||||
int dma_if_intr_sts;
|
||||
int dma_if_intr_msk;
|
||||
int dma_if_ctrl;
|
||||
int (*mac_force_mode_ctrl)(int port);
|
||||
int (*dma_rx_base)(int ring);
|
||||
int (*dma_tx_base)(int ring);
|
||||
int (*dma_if_rx_ring_size)(int ring);
|
||||
int (*dma_if_rx_ring_cntr)(int ring);
|
||||
int (*dma_if_rx_cur)(int ring);
|
||||
int rst_glb_ctrl;
|
||||
u32 (*get_mac_link_sts)(int port);
|
||||
u32 (*get_mac_link_dup_sts)(int port);
|
||||
u32 (*get_mac_link_spd_sts)(int port);
|
||||
u32 (*get_mac_rx_pause_sts)(int port);
|
||||
u32 (*get_mac_tx_pause_sts)(int port);
|
||||
int mac;
|
||||
int l2_tbl_flush_ctrl;
|
||||
};
|
||||
|
||||
int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
|
||||
int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
|
||||
int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
|
||||
int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
|
||||
|
||||
#endif /* _RTL838X_ETH_H */
|
||||
1400
target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.c
Normal file
1400
target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.c
Normal file
File diff suppressed because it is too large
Load Diff
40
target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h
Normal file
40
target/linux/realtek/files-5.4/drivers/net/phy/rtl83xx-phy.h
Normal file
@@ -0,0 +1,40 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
// TODO: not really used
|
||||
struct rtl838x_phy_priv {
|
||||
char *name;
|
||||
};
|
||||
|
||||
struct __attribute__ ((__packed__)) part {
|
||||
uint16_t start;
|
||||
uint8_t wordsize;
|
||||
uint8_t words;
|
||||
};
|
||||
|
||||
struct __attribute__ ((__packed__)) fw_header {
|
||||
uint32_t magic;
|
||||
uint32_t phy;
|
||||
uint32_t checksum;
|
||||
uint32_t version;
|
||||
struct part parts[10];
|
||||
};
|
||||
|
||||
// TODO: fixed path?
|
||||
#define FIRMWARE_838X_8380_1 "rtl838x_phy/rtl838x_8380.fw"
|
||||
#define FIRMWARE_838X_8214FC_1 "rtl838x_phy/rtl838x_8214fc.fw"
|
||||
#define FIRMWARE_838X_8218b_1 "rtl838x_phy/rtl838x_8218b.fw"
|
||||
|
||||
/* External RTL8218B and RTL8214FC IDs are identical */
|
||||
#define PHY_ID_RTL8214C 0x001cc942
|
||||
#define PHY_ID_RTL8214FC 0x001cc981
|
||||
#define PHY_ID_RTL8218B_E 0x001cc981
|
||||
#define PHY_ID_RTL8218B_I 0x001cca40
|
||||
#define PHY_ID_RTL8390_GENERIC 0x001ccab0
|
||||
#define PHY_ID_RTL8393_I 0x001c8393
|
||||
|
||||
#define RTL839X_SDS12_13_XSG0 (0xB800)
|
||||
|
||||
#define RTL838X_SDS_MODE_SEL (0x0028)
|
||||
#define RTL838X_SDS_CFG_REG (0x0034)
|
||||
#define RTL838X_INT_MODE_CTRL (0x005c)
|
||||
#define RTL838X_DMY_REG31 (0x3b28)
|
||||
Reference in New Issue
Block a user