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uboot-ramips: add support for MT7621, merge into uboot-mediatek

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* Merge uboot-ramips into uboot-mediatek.
* Port support for the RAVPower RP WD009 to U-Boot 2022.07.
* Add support for MT7621 and add builds for the reference boards.
* Add builds for MT7620 and MT7628 reference boards.

This should help to make development of U-Boot-level board support for
all MediaTek targets much easier.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle
2022-07-11 21:15:32 +01:00
parent fa75a3a935
commit 2f7fb57c12
29 changed files with 7440 additions and 110 deletions
Download Patch File Download Diff File Expand all files Collapse all files

83
package/boot/uboot-mediatek/Makefile
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@@ -9,11 +9,59 @@ include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk include $(INCLUDE_DIR)/package.mk
include $(INCLUDE_DIR)/host-build.mk include $(INCLUDE_DIR)/host-build.mk
MT7621_LOWLEVEL_PRELOADER_URL:=https://raw.githubusercontent.com/mtk-openwrt/mt7621-lowlevel-preloader/master/
define Download/mt7621-stage-sram
FILE:=mt7621_stage_sram.bin
URL:=$(MT7621_LOWLEVEL_PRELOADER_URL)
HASH:=1dda68aa089f0ff262e01539b990dea478952e9fb68bcc0a8cd6f76f0135c62e
endef
ifdef CONFIG_TARGET_ramips_mt7621
$(eval $(call Download,mt7621-stage-sram))
endif
define U-Boot/Default define U-Boot/Default
BUILD_TARGET:=mediatek BUILD_TARGET:=mediatek
UBOOT_IMAGE:=u-boot-mtk.bin UBOOT_IMAGE:=u-boot-mtk.bin
endef endef
define U-Boot/mt7620_rfb
NAME:=MT7620 Reference Board
UBOOT_CONFIG:=mt7620_rfb
BUILD_DEVICES:=ralink_mt7620a-evb
BUILD_TARGET:=ramips
BUILD_SUBTARGET:=mt7620
UBOOT_IMAGE:=u-boot-with-spl.bin
endef
define U-Boot/mt7620_mt7530_rfb
NAME:=MT7620+MT7530 Reference Board
UBOOT_CONFIG:=mt7620_mt7530_rfb
BUILD_DEVICES:=ralink_mt7620a-mt7530-evb
BUILD_TARGET:=ramips
BUILD_SUBTARGET:=mt7620
UBOOT_IMAGE:=u-boot-with-spl.bin
endef
define U-Boot/mt7621_rfb
NAME:=MT7621 Reference Board
UBOOT_CONFIG:=mt7621_rfb
BUILD_DEVICES:=mediatek_mt7621-eval-board
BUILD_TARGET:=ramips
BUILD_SUBTARGET:=mt7621
UBOOT_IMAGE:=u-boot-mt7621.bin
endef
define U-Boot/mt7621_nand_rfb
NAME:=MT7621 Reference Board (NAND)
UBOOT_CONFIG:=mt7621_nand_rfb
BUILD_DEVICES:=mediatek_mt7621-eval-board
BUILD_TARGET:=ramips
BUILD_SUBTARGET:=mt7621
UBOOT_IMAGE:=u-boot-mt7621.bin
endef
define U-Boot/mt7622_rfb1 define U-Boot/mt7622_rfb1
NAME:=MT7622 Reference Board 1 NAME:=MT7622 Reference Board 1
UBOOT_CONFIG:=mt7622_rfb UBOOT_CONFIG:=mt7622_rfb
@@ -91,6 +139,24 @@ define U-Boot/mt7623n_bpir2
UBOOT_CONFIG:=mt7623n_bpir2 UBOOT_CONFIG:=mt7623n_bpir2
endef endef
define U-Boot/mt7628_rfb
NAME:=MT7628 Reference Board
BUILD_DEVICES:=mediatek_mt7628an-eval-board
BUILD_TARGET:=ramips
BUILD_SUBTARGET:=mt76x8
UBOOT_CONFIG:=mt7628_rfb
UBOOT_IMAGE:=u-boot-with-spl.bin
endef
define U-Boot/ravpower_rp-wd009
NAME:=RAVPower RP-WD009
BUILD_TARGET:=ramips
BUILD_DEVICES:=ravpower_rp-wd009
BUILD_SUBTARGET:=mt76x8
UBOOT_CONFIG:=ravpower-rp-wd009-ram
UBOOT_IMAGE:=u-boot.bin
endef
define U-Boot/mt7629_rfb define U-Boot/mt7629_rfb
NAME:=MT7629 Reference Board NAME:=MT7629 Reference Board
BUILD_SUBTARGET:=mt7629 BUILD_SUBTARGET:=mt7629
@@ -99,6 +165,10 @@ define U-Boot/mt7629_rfb
endef endef
UBOOT_TARGETS := \ UBOOT_TARGETS := \
mt7620_mt7530_rfb \
mt7620_rfb \
mt7621_nand_rfb \
mt7621_rfb \
mt7622_bananapi_bpi-r64-emmc \ mt7622_bananapi_bpi-r64-emmc \
mt7622_bananapi_bpi-r64-sdmmc \ mt7622_bananapi_bpi-r64-sdmmc \
mt7622_bananapi_bpi-r64-snand \ mt7622_bananapi_bpi-r64-snand \
@@ -107,9 +177,13 @@ UBOOT_TARGETS := \
mt7622_ubnt_unifi-6-lr \ mt7622_ubnt_unifi-6-lr \
mt7623n_bpir2 \ mt7623n_bpir2 \
mt7623a_unielec_u7623 \ mt7623a_unielec_u7623 \
mt7628_rfb \
ravpower_rp-wd009 \
mt7629_rfb mt7629_rfb
ifdef CONFIG_TARGET_mediatek
UBOOT_MAKE_FLAGS += $(UBOOT_IMAGE:.fip=.bin) UBOOT_MAKE_FLAGS += $(UBOOT_IMAGE:.fip=.bin)
endif
define Build/fip-image define Build/fip-image
$(STAGING_DIR_HOST)/bin/fiptool create \ $(STAGING_DIR_HOST)/bin/fiptool create \
@@ -118,6 +192,13 @@ define Build/fip-image
$(PKG_BUILD_DIR)/u-boot.fip $(PKG_BUILD_DIR)/u-boot.fip
endef endef
ifdef CONFIG_TARGET_ramips_mt7621
define Build/Prepare
$(call Build/Prepare/Default)
$(CP) $(DL_DIR)/mt7621_stage_sram.bin $(PKG_BUILD_DIR)/
endef
endif
define Build/Configure define Build/Configure
$(call Build/Configure/U-Boot) $(call Build/Configure/U-Boot)
sed -i 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config sed -i 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config
@@ -131,8 +212,10 @@ endif
endef endef
# don't stage files to bindir, let target/linux/mediatek/image/*.mk do that # don't stage files to bindir, let target/linux/mediatek/image/*.mk do that
ifdef CONFIG_TARGET_mediatek
define Package/u-boot/install define Package/u-boot/install
endef endef
endif
define Build/InstallDev define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE) $(INSTALL_DIR) $(STAGING_DIR_IMAGE)

169
package/boot/uboot-mediatek/patches/001-mtk-0001-mips-add-asm-mipsmtregs.h-for-MIPS-multi-threading.patch Normal file
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@@ -0,0 +1,169 @@
From 65a4a80157bacde3cf86ce8cbc9a08f5f05ad9bb Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:21:34 +0800
Subject: [PATCH 01/25] mips: add asm/mipsmtregs.h for MIPS multi-threading
To be compatible with old u-boot used by lots of MT7621 devices, the u-boot
needs to boot-up MT7621's all cores, and all VPES of each core.
This patch adds asm/mipsmtregs.h from linux kernel which is need for
boot-up VPEs.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/mips/include/asm/mipsmtregs.h | 142 +++++++++++++++++++++++++++++
1 file changed, 142 insertions(+)
create mode 100644 arch/mips/include/asm/mipsmtregs.h
diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
new file mode 100644
index 0000000000..ba82e2bd97
--- /dev/null
+++ b/arch/mips/include/asm/mipsmtregs.h
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * MT regs definitions, follows on from mipsregs.h
+ * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved.
+ * Elizabeth Clarke et. al.
+ *
+ */
+#ifndef _ASM_MIPSMTREGS_H
+#define _ASM_MIPSMTREGS_H
+
+#include <asm/mipsregs.h>
+
+/*
+ * Macros for use in assembly language code
+ */
+
+#define CP0_MVPCONTROL $0, 1
+#define CP0_MVPCONF0 $0, 2
+#define CP0_MVPCONF1 $0, 3
+#define CP0_VPECONTROL $1, 1
+#define CP0_VPECONF0 $1, 2
+#define CP0_VPECONF1 $1, 3
+#define CP0_YQMASK $1, 4
+#define CP0_VPESCHEDULE $1, 5
+#define CP0_VPESCHEFBK $1, 6
+#define CP0_TCSTATUS $2, 1
+#define CP0_TCBIND $2, 2
+#define CP0_TCRESTART $2, 3
+#define CP0_TCHALT $2, 4
+#define CP0_TCCONTEXT $2, 5
+#define CP0_TCSCHEDULE $2, 6
+#define CP0_TCSCHEFBK $2, 7
+#define CP0_SRSCONF0 $6, 1
+#define CP0_SRSCONF1 $6, 2
+#define CP0_SRSCONF2 $6, 3
+#define CP0_SRSCONF3 $6, 4
+#define CP0_SRSCONF4 $6, 5
+
+/* MVPControl fields */
+#define MVPCONTROL_EVP (_ULCAST_(1))
+
+#define MVPCONTROL_VPC_SHIFT 1
+#define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
+
+#define MVPCONTROL_STLB_SHIFT 2
+#define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
+
+/* MVPConf0 fields */
+#define MVPCONF0_PTC_SHIFT 0
+#define MVPCONF0_PTC (_ULCAST_(0xff))
+#define MVPCONF0_PVPE_SHIFT 10
+#define MVPCONF0_PVPE (_ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
+#define MVPCONF0_TCA_SHIFT 15
+#define MVPCONF0_TCA (_ULCAST_(1) << MVPCONF0_TCA_SHIFT)
+#define MVPCONF0_PTLBE_SHIFT 16
+#define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
+#define MVPCONF0_TLBS_SHIFT 29
+#define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
+#define MVPCONF0_M_SHIFT 31
+#define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
+
+/* config3 fields */
+#define CONFIG3_MT_SHIFT 2
+#define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT)
+
+/* VPEControl fields (per VPE) */
+#define VPECONTROL_TARGTC (_ULCAST_(0xff))
+
+#define VPECONTROL_TE_SHIFT 15
+#define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
+#define VPECONTROL_EXCPT_SHIFT 16
+#define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
+
+/* Thread Exception Codes for EXCPT field */
+#define THREX_TU 0
+#define THREX_TO 1
+#define THREX_IYQ 2
+#define THREX_GSX 3
+#define THREX_YSCH 4
+#define THREX_GSSCH 5
+
+#define VPECONTROL_GSI_SHIFT 20
+#define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
+#define VPECONTROL_YSI_SHIFT 21
+#define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
+
+/* VPEConf0 fields (per VPE) */
+#define VPECONF0_VPA_SHIFT 0
+#define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
+#define VPECONF0_MVP_SHIFT 1
+#define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
+#define VPECONF0_XTC_SHIFT 21
+#define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
+
+/* VPEConf1 fields (per VPE) */
+#define VPECONF1_NCP1_SHIFT 0
+#define VPECONF1_NCP1 (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT)
+#define VPECONF1_NCP2_SHIFT 10
+#define VPECONF1_NCP2 (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT)
+#define VPECONF1_NCX_SHIFT 20
+#define VPECONF1_NCX (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT)
+
+/* TCStatus fields (per TC) */
+#define TCSTATUS_TASID (_ULCAST_(0xff))
+#define TCSTATUS_IXMT_SHIFT 10
+#define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
+#define TCSTATUS_TKSU_SHIFT 11
+#define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
+#define TCSTATUS_A_SHIFT 13
+#define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT)
+#define TCSTATUS_DA_SHIFT 15
+#define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
+#define TCSTATUS_DT_SHIFT 20
+#define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
+#define TCSTATUS_TDS_SHIFT 21
+#define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
+#define TCSTATUS_TSST_SHIFT 22
+#define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
+#define TCSTATUS_RNST_SHIFT 23
+#define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
+/* Codes for RNST */
+#define TC_RUNNING 0
+#define TC_WAITING 1
+#define TC_YIELDING 2
+#define TC_GATED 3
+
+#define TCSTATUS_TMX_SHIFT 27
+#define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
+/* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
+
+/* TCBind */
+#define TCBIND_CURVPE_SHIFT 0
+#define TCBIND_CURVPE (_ULCAST_(0xf))
+
+#define TCBIND_CURTC_SHIFT 21
+
+#define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
+
+/* TCHalt */
+#define TCHALT_H (_ULCAST_(1))
+
+#endif
--
2.36.1

116
package/boot/uboot-mediatek/patches/001-mtk-0002-mips-add-more-definitions-for-asm-cm.h.patch Normal file
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@@ -0,0 +1,116 @@
From be570e7b0ce004127a7cc97bfae30037fc42a340 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:21:39 +0800
Subject: [PATCH 02/25] mips: add more definitions for asm/cm.h
This patch add more definitions needed for MT7621 initialization.
MT7621 needs to initialize GIC/CPC and other related parts.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/mips/include/asm/cm.h | 67 ++++++++++++++++++++++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h
index 99ddbccd80..5cc8c09621 100644
--- a/arch/mips/include/asm/cm.h
+++ b/arch/mips/include/asm/cm.h
@@ -8,9 +8,23 @@
#define __MIPS_ASM_CM_H__
/* Global Control Register (GCR) offsets */
+#define GCR_CONFIG 0x0000
#define GCR_BASE 0x0008
#define GCR_BASE_UPPER 0x000c
+#define GCR_CONTROL 0x0010
+#define GCR_ACCESS 0x0020
#define GCR_REV 0x0030
+#define GCR_GIC_BASE 0x0080
+#define GCR_CPC_BASE 0x0088
+#define GCR_REG0_BASE 0x0090
+#define GCR_REG0_MASK 0x0098
+#define GCR_REG1_BASE 0x00a0
+#define GCR_REG1_MASK 0x00a8
+#define GCR_REG2_BASE 0x00b0
+#define GCR_REG2_MASK 0x00b8
+#define GCR_REG3_BASE 0x00c0
+#define GCR_REG3_MASK 0x00c8
+#define GCR_CPC_STATUS 0x00f0
#define GCR_L2_CONFIG 0x0130
#define GCR_L2_TAG_ADDR 0x0600
#define GCR_L2_TAG_ADDR_UPPER 0x0604
@@ -19,10 +33,59 @@
#define GCR_L2_DATA 0x0610
#define GCR_L2_DATA_UPPER 0x0614
#define GCR_Cx_COHERENCE 0x2008
+#define GCR_Cx_OTHER 0x2018
+#define GCR_Cx_ID 0x2028
+#define GCR_CO_COHERENCE 0x4008
+
+/* GCR_CONFIG fields */
+#define GCR_CONFIG_NUM_CLUSTERS_SHIFT 23
+#define GCR_CONFIG_NUM_CLUSTERS (0x7f << 23)
+#define GCR_CONFIG_NUMIOCU_SHIFT 8
+#define GCR_CONFIG_NUMIOCU (0xff << 8)
+#define GCR_CONFIG_PCORES_SHIFT 0
+#define GCR_CONFIG_PCORES (0xff << 0)
+
+/* GCR_BASE fields */
+#define GCR_BASE_SHIFT 15
+#define CCA_DEFAULT_OVR_SHIFT 5
+#define CCA_DEFAULT_OVR_MASK (0x7 << 5)
+#define CCA_DEFAULT_OVREN (0x1 << 4)
+#define CM_DEFAULT_TARGET_SHIFT 0
+#define CM_DEFAULT_TARGET_MASK (0x3 << 0)
+
+/* GCR_CONTROL fields */
+#define GCR_CONTROL_SYNCCTL (0x1 << 16)
/* GCR_REV CM versions */
#define GCR_REV_CM3 0x0800
+/* GCR_GIC_BASE fields */
+#define GCR_GIC_BASE_ADDRMASK_SHIFT 7
+#define GCR_GIC_BASE_ADDRMASK (0x1ffffff << 7)
+#define GCR_GIC_EN (0x1 << 0)
+
+/* GCR_CPC_BASE fields */
+#define GCR_CPC_BASE_ADDRMASK_SHIFT 15
+#define GCR_CPC_BASE_ADDRMASK (0x1ffff << 15)
+#define GCR_CPC_EN (0x1 << 0)
+
+/* GCR_REGn_MASK fields */
+#define GCR_REGn_MASK_ADDRMASK_SHIFT 16
+#define GCR_REGn_MASK_ADDRMASK (0xffff << 16)
+#define GCR_REGn_MASK_CCAOVR_SHIFT 5
+#define GCR_REGn_MASK_CCAOVR (0x7 << 5)
+#define GCR_REGn_MASK_CCAOVREN (1 << 4)
+#define GCR_REGn_MASK_DROPL2 (1 << 2)
+#define GCR_REGn_MASK_CMTGT_SHIFT 0
+#define GCR_REGn_MASK_CMTGT (0x3 << 0)
+#define GCR_REGn_MASK_CMTGT_DISABLED 0x0
+#define GCR_REGn_MASK_CMTGT_MEM 0x1
+#define GCR_REGn_MASK_CMTGT_IOCU0 0x2
+#define GCR_REGn_MASK_CMTGT_IOCU1 0x3
+
+/* GCR_CPC_STATUS fields */
+#define GCR_CPC_EX (0x1 << 0)
+
/* GCR_L2_CONFIG fields */
#define GCR_L2_CONFIG_ASSOC_SHIFT 0
#define GCR_L2_CONFIG_ASSOC_BITS 8
@@ -36,6 +99,10 @@
#define GCR_Cx_COHERENCE_DOM_EN (0xff << 0)
#define GCR_Cx_COHERENCE_EN (0x1 << 0)
+/* GCR_Cx_OTHER fields */
+#define GCR_Cx_OTHER_CORENUM_SHIFT 16
+#define GCR_Cx_OTHER_CORENUM (0xffff << 16)
+
#ifndef __ASSEMBLY__
#include <asm/io.h>
--
2.36.1

40
package/boot/uboot-mediatek/patches/001-mtk-0003-mips-add-__image_copy_len-for-SPL-linker-script.patch Normal file
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@@ -0,0 +1,40 @@
From 71ebc3d25147172e219ea87bec061f751257395b Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:21:45 +0800
Subject: [PATCH 03/25] mips: add __image_copy_len for SPL linker script
This patch adds __image_copy_len needed by TPL of MT7621 SoC.
The __image_copy_len represents the binary blob size of both SPL/TPL
binaries. To achieve this, __text_start/end are added for calculation.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/mips/cpu/u-boot-spl.lds | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/cpu/u-boot-spl.lds b/arch/mips/cpu/u-boot-spl.lds
index 28ea4f2a48..f88754ab56 100644
--- a/arch/mips/cpu/u-boot-spl.lds
+++ b/arch/mips/cpu/u-boot-spl.lds
@@ -13,7 +13,9 @@ SECTIONS
. = ALIGN(4);
.text : {
+ __text_start = .;
*(.text*)
+ __text_end = .;
} > .spl_mem
. = ALIGN(4);
@@ -36,6 +38,7 @@ SECTIONS
. = ALIGN(4);
__image_copy_end = .;
+ __image_copy_len = __image_copy_end - __text_start;
_image_binary_end = .;
--
2.36.1

111
package/boot/uboot-mediatek/patches/001-mtk-0004-mips-add-support-for-noncached_alloc.patch Normal file
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@@ -0,0 +1,111 @@
From d7cfa1cb5602a1d936df36ee70869753835de28e Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:21:51 +0800
Subject: [PATCH 04/25] mips: add support for noncached_alloc()
This patch adds support for noncached_alloc() which was only supported by
ARM platform.
Unlike the ARM platform, MMU is not used in u-boot for MIPS. Instead, KSEG
is provided to access uncached memory. So most code of this patch is copied
from cache.c of ARM platform, with only two differences:
1. MMU is untouched in noncached_set_region()
2. Address returned by noncached_alloc() is converted using KSEG1ADDR()
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/mips/include/asm/system.h | 20 ++++++++++++++++
arch/mips/lib/cache.c | 43 ++++++++++++++++++++++++++++++++++
2 files changed, 63 insertions(+)
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index 79e638844b..89a2ac209f 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -282,4 +282,24 @@ static inline void instruction_hazard_barrier(void)
: "=&r"(tmp));
}
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+/* 1MB granularity */
+#define MMU_SECTION_SHIFT 20
+#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
+
+/**
+ * noncached_init() - Initialize non-cached memory region
+ *
+ * Initialize non-cached memory area. This memory region will be typically
+ * located right below the malloc() area and be accessed from KSEG1.
+ *
+ * It is called during the generic post-relocation init sequence.
+ *
+ * Return: 0 if OK
+ */
+int noncached_init(void);
+
+phys_addr_t noncached_alloc(size_t size, size_t align);
+#endif /* CONFIG_SYS_NONCACHED_MEMORY */
+
#endif /* _ASM_SYSTEM_H */
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index ec652f0fba..d23b38d6b9 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <cpu_func.h>
+#include <malloc.h>
#include <asm/cache.h>
#include <asm/cacheops.h>
#include <asm/cm.h>
@@ -197,3 +198,45 @@ void dcache_disable(void)
/* ensure the pipeline doesn't contain now-invalid instructions */
instruction_hazard_barrier();
}
+
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+static unsigned long noncached_start;
+static unsigned long noncached_end;
+static unsigned long noncached_next;
+
+void noncached_set_region(void)
+{
+}
+
+int noncached_init(void)
+{
+ phys_addr_t start, end;
+ size_t size;
+
+ /* If this calculation changes, update board_f.c:reserve_noncached() */
+ end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
+ size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
+ start = end - size;
+
+ debug("mapping memory %pa-%pa non-cached\n", &start, &end);
+
+ noncached_start = start;
+ noncached_end = end;
+ noncached_next = start;
+
+ return 0;
+}
+
+phys_addr_t noncached_alloc(size_t size, size_t align)
+{
+ phys_addr_t next = ALIGN(noncached_next, align);
+
+ if (next >= noncached_end || (noncached_end - next) < size)
+ return 0;
+
+ debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
+ noncached_next = next + size;
+
+ return CKSEG1ADDR(next);
+}
+#endif /* CONFIG_SYS_NONCACHED_MEMORY */
--
2.36.1

2979
package/boot/uboot-mediatek/patches/001-mtk-0005-mips-mtmips-add-support-for-MediaTek-MT7621-SoC.patch Normal file
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456
package/boot/uboot-mediatek/patches/001-mtk-0006-mips-mtmips-add-two-reference-boards-for-mt7621.patch Normal file
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@@ -0,0 +1,456 @@
From b1549087ecd1eb53f6173b17b473134fd6cca157 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:22:26 +0800
Subject: [PATCH 06/25] mips: mtmips: add two reference boards for mt7621
The mt7621_rfb board supports integrated giga PHYs plus one external
giga PHYs. It also has up to 512MiB DDR3, 16MB SPI-NOR, 3 mini PCI-e x1
slots, SDXC and USB.
The mt7621_nand_rfb board is almost the same as mt7621_rfb board, but it
uses NAND flash and SDXC is not available.
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/mips/dts/Makefile | 2 +
arch/mips/dts/mediatek,mt7621-nand-rfb.dts | 67 +++++++++++++++++
arch/mips/dts/mediatek,mt7621-rfb.dts | 82 +++++++++++++++++++++
arch/mips/mach-mtmips/mt7621/Kconfig | 20 +++++
board/mediatek/mt7621/MAINTAINERS | 8 ++
board/mediatek/mt7621/Makefile | 3 +
board/mediatek/mt7621/board.c | 6 ++
configs/mt7621_nand_rfb_defconfig | 85 ++++++++++++++++++++++
configs/mt7621_rfb_defconfig | 82 +++++++++++++++++++++
9 files changed, 355 insertions(+)
create mode 100644 arch/mips/dts/mediatek,mt7621-nand-rfb.dts
create mode 100644 arch/mips/dts/mediatek,mt7621-rfb.dts
create mode 100644 board/mediatek/mt7621/MAINTAINERS
create mode 100644 board/mediatek/mt7621/Makefile
create mode 100644 board/mediatek/mt7621/board.c
create mode 100644 configs/mt7621_nand_rfb_defconfig
create mode 100644 configs/mt7621_rfb_defconfig
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 95144b24dc..1b179116c9 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -16,6 +16,8 @@ dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb
dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb
+dtb-$(CONFIG_BOARD_MT7621_RFB) += mediatek,mt7621-rfb.dtb
+dtb-$(CONFIG_BOARD_MT7621_NAND_RFB) += mediatek,mt7621-nand-rfb.dtb
dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb
dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb
diff --git a/arch/mips/dts/mediatek,mt7621-nand-rfb.dts b/arch/mips/dts/mediatek,mt7621-nand-rfb.dts
new file mode 100644
index 0000000000..67ba298b0a
--- /dev/null
+++ b/arch/mips/dts/mediatek,mt7621-nand-rfb.dts
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+/dts-v1/;
+
+#include "mt7621.dtsi"
+
+/ {
+ compatible = "mediatek,mt7621-nand-rfb", "mediatek,mt7621-soc";
+ model = "MediaTek MT7621 RFB (NAND)";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&pinctrl {
+ state_default: pin_state {
+ nand {
+ groups = "spi", "sdxc";
+ function = "nand";
+ };
+
+ gpios {
+ groups = "i2c", "uart3", "pcie reset";
+ function = "gpio";
+ };
+
+ wdt {
+ groups = "wdt";
+ function = "wdt rst";
+ };
+
+ jtag {
+ groups = "jtag";
+ function = "jtag";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
+
+&eth {
+ status = "okay";
+};
+
+&ssusb {
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
diff --git a/arch/mips/dts/mediatek,mt7621-rfb.dts b/arch/mips/dts/mediatek,mt7621-rfb.dts
new file mode 100644
index 0000000000..ff7eaf0f20
--- /dev/null
+++ b/arch/mips/dts/mediatek,mt7621-rfb.dts
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+/dts-v1/;
+
+#include "mt7621.dtsi"
+
+/ {
+ compatible = "mediatek,mt7621-rfb", "mediatek,mt7621-soc";
+ model = "MediaTek MT7621 RFB (SPI-NOR)";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&pinctrl {
+ state_default: pin_state {
+ gpios {
+ groups = "i2c", "uart3", "pcie reset";
+ function = "gpio";
+ };
+
+ wdt {
+ groups = "wdt";
+ function = "wdt rst";
+ };
+
+ jtag {
+ groups = "jtag";
+ function = "jtag";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
+
+&spi {
+ status = "okay";
+ num-cs = <2>;
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+};
+
+&eth {
+ status = "okay";
+};
+
+&mmc {
+ cap-sd-highspeed;
+
+ status = "okay";
+};
+
+&ssusb {
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
diff --git a/arch/mips/mach-mtmips/mt7621/Kconfig b/arch/mips/mach-mtmips/mt7621/Kconfig
index 37d512c68f..008a28f991 100644
--- a/arch/mips/mach-mtmips/mt7621/Kconfig
+++ b/arch/mips/mach-mtmips/mt7621/Kconfig
@@ -79,6 +79,26 @@ config MT7621_BOOT_FROM_NAND
choice
prompt "Board select"
+config BOARD_MT7621_RFB
+ bool "MediaTek MT7621 RFB (SPI-NOR)"
+ help
+ The reference design of MT7621A (WS3010) booting from SPI-NOR flash.
+ The board can be configured with DDR2 (64MiB~256MiB) or DDR3
+ (128MiB~512MiB). The board has 16 MiB SPI-NOR flash, built-in MT7530
+ GbE switch, 1 UART, 1 USB 2.0 host, 1 USB 3.0 host, 1 SDXC, 3 PCIe
+ sockets, 1 RGMII to external GbE PHY, 2 audio jacks (in/out),
+ JTAG pins and expansion GPIO pins.
+
+config BOARD_MT7621_NAND_RFB
+ bool "MediaTek MT7621 RFB (NAND)"
+ help
+ The reference design of MT7621A (WS3010) booting from NAND flash.
+ The board can be configured with DDR2 (64MiB~256MiB) or DDR3
+ (128MiB~512MiB). The board has 128 MiB parallel NAND flash, built-in
+ MT7530 GbE switch, 1 UART, 1 USB 2.0 host, 1 USB 3.0 host, 3 PCIe
+ sockets, 1 RGMII to external GbE PHY, 2 audio jacks (in/out),
+ JTAG pins and expansion GPIO pins.
+
endchoice
config SYS_CONFIG_NAME
diff --git a/board/mediatek/mt7621/MAINTAINERS b/board/mediatek/mt7621/MAINTAINERS
new file mode 100644
index 0000000000..f83141cea1
--- /dev/null
+++ b/board/mediatek/mt7621/MAINTAINERS
@@ -0,0 +1,8 @@
+MT7621_RFB BOARD
+M: Weijie Gao <weijie.gao@mediatek.com>
+S: Maintained
+F: board/mediatek/mt7621
+F: configs/mt7621_rfb_defconfig
+F: configs/mt7621_nand_rfb_defconfig
+F: arch/mips/dts/mediatek,mt7621-rfb.dts
+F: arch/mips/dts/mediatek,mt7621-nand-rfb.dts
diff --git a/board/mediatek/mt7621/Makefile b/board/mediatek/mt7621/Makefile
new file mode 100644
index 0000000000..db129c5aba
--- /dev/null
+++ b/board/mediatek/mt7621/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += board.o
diff --git a/board/mediatek/mt7621/board.c b/board/mediatek/mt7621/board.c
new file mode 100644
index 0000000000..0496f3f806
--- /dev/null
+++ b/board/mediatek/mt7621/board.c
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
diff --git a/configs/mt7621_nand_rfb_defconfig b/configs/mt7621_nand_rfb_defconfig
new file mode 100644
index 0000000000..fe8543df49
--- /dev/null
+++ b/configs/mt7621_nand_rfb_defconfig
@@ -0,0 +1,85 @@
+CONFIG_MIPS=y
+CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7621-nand-rfb"
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xbe000c00
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_SYS_LOAD_ADDR=0x83000000
+CONFIG_ARCH_MTMIPS=y
+CONFIG_SOC_MT7621=y
+CONFIG_MT7621_BOOT_FROM_NAND=y
+CONFIG_BOARD_MT7621_NAND_RFB=y
+# CONFIG_MIPS_CACHE_SETUP is not set
+# CONFIG_MIPS_CACHE_DISABLE is not set
+CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_NAND_BASE=y
+CONFIG_SPL_NAND_IDENT=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+CONFIG_MMC=y
+# CONFIG_MMC_QUIRKS is not set
+# CONFIG_MMC_HW_PARTITIONING is not set
+CONFIG_MMC_MTK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_MT7621=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x0
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_RESETCTL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_STORAGE=y
+CONFIG_WDT=y
+CONFIG_WDT_MT7621=y
+CONFIG_FAT_WRITE=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_LZMA=y
+# CONFIG_GZIP is not set
+CONFIG_SPL_LZMA=y
diff --git a/configs/mt7621_rfb_defconfig b/configs/mt7621_rfb_defconfig
new file mode 100644
index 0000000000..ae62360e63
--- /dev/null
+++ b/configs/mt7621_rfb_defconfig
@@ -0,0 +1,82 @@
+CONFIG_MIPS=y
+CONFIG_SYS_MALLOC_LEN=0x100000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7621-rfb"
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xbe000c00
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_SYS_LOAD_ADDR=0x83000000
+CONFIG_ARCH_MTMIPS=y
+CONFIG_SOC_MT7621=y
+# CONFIG_MIPS_CACHE_SETUP is not set
+# CONFIG_MIPS_CACHE_DISABLE is not set
+CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_TPL=y
+# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_NFS is not set
+CONFIG_DOS_PARTITION=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+CONFIG_MMC=y
+# CONFIG_MMC_QUIRKS is not set
+# CONFIG_MMC_HW_PARTITIONING is not set
+CONFIG_MMC_MTK=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SPI=y
+CONFIG_MT7621_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_RESETCTL=y
+CONFIG_WDT=y
+CONFIG_WDT_MT7621=y
+# CONFIG_BINMAN_FDT is not set
+CONFIG_LZMA=y
+# CONFIG_GZIP is not set
+CONFIG_SPL_LZMA=y
--
2.36.1

104
package/boot/uboot-mediatek/patches/001-mtk-0007-doc-mediatek-add-documentation-for-mt7621-reference-.patch Normal file
View File

@@ -0,0 +1,104 @@
From 3fed02d930597c53f1c8500aff14581bb87a1e3d Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:22:31 +0800
Subject: [PATCH 07/25] doc: mediatek: add documentation for mt7621 reference
boards
The MT7621 requires external binary blob being executed during u-boot's
boot-up flow. It's necessary to provide a guide here for users to correctly
build the u-boot.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
doc/board/index.rst | 1 +
doc/board/mediatek/index.rst | 9 +++++++
doc/board/mediatek/mt7621.rst | 48 +++++++++++++++++++++++++++++++++++
3 files changed, 58 insertions(+)
create mode 100644 doc/board/mediatek/index.rst
create mode 100644 doc/board/mediatek/mt7621.rst
diff --git a/doc/board/index.rst b/doc/board/index.rst
index f90a9cad45..01b99f9cf5 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -23,6 +23,7 @@ Board-specific doc
highbank/index
intel/index
kontron/index
+ mediatek/index
microchip/index
nokia/index
nxp/index
diff --git a/doc/board/mediatek/index.rst b/doc/board/mediatek/index.rst
new file mode 100644
index 0000000000..38cd8cb5b2
--- /dev/null
+++ b/doc/board/mediatek/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Mediatek
+=========
+
+.. toctree::
+ :maxdepth: 2
+
+ mt7621
diff --git a/doc/board/mediatek/mt7621.rst b/doc/board/mediatek/mt7621.rst
new file mode 100644
index 0000000000..1662255546
--- /dev/null
+++ b/doc/board/mediatek/mt7621.rst
@@ -0,0 +1,48 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+mt7621_rfb/mt7621_nand_rfb
+==========================
+
+U-Boot for the MediaTek MT7621 boards
+
+Quick Start
+-----------
+
+- Get the DDR initialization binary blob
+- Configure CPU and DDR parameters
+- Build U-Boot
+
+Get the DDR initialization binary blob
+--------------------------------------
+
+Download one from:
+ - https://raw.githubusercontent.com/mtk-openwrt/mt7621-lowlevel-preloader/master/mt7621_stage_sram.bin
+ - https://raw.githubusercontent.com/mtk-openwrt/mt7621-lowlevel-preloader/master/mt7621_stage_sram_noprint.bin
+
+mt7621_stage_sram_noprint.bin has removed all output logs. To use this one,
+download and rename it to mt7621_stage_sram.bin
+
+Put the binary blob to the u-boot build directory.
+
+Configure CPU and DDR parameters
+--------------------------------
+
+menuconfig > MIPS architecture > MediaTek MIPS platforms > CPU & DDR configuration
+
+Select the correct DDR timing parameters for your board. The size shown here
+must match the DDR size of you board.
+
+The frequency of CPU and DDR can also be adjusted.
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=mipsel-linux-
+ $ make O=build mt7621_rfb_defconfig # or mt7621_nand_rfb_defconfig
+ $ cp mt7621_stage_sram.bin ./build/mt7621_stage_sram.bin
+ $ # or cp mt7621_stage_sram_noprint.bin ./build/mt7621_stage_sram.bin
+ $ make O=build
+
+Burn the u-boot-mt7621.bin to the SPI-NOR or NAND flash.
--
2.36.1

378
package/boot/uboot-mediatek/patches/001-mtk-0008-clk-mtmips-add-clock-driver-for-MediaTek-MT7621-SoC.patch Normal file
View File

@@ -0,0 +1,378 @@
From c2e579662748cb5d3bf3e31f58d99c4db4d102c1 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:22:36 +0800
Subject: [PATCH 08/25] clk: mtmips: add clock driver for MediaTek MT7621 SoC
This patch adds a clock driver for MediaTek MT7621 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/clk/mtmips/Makefile | 1 +
drivers/clk/mtmips/clk-mt7621.c | 288 +++++++++++++++++++++++++
include/dt-bindings/clock/mt7621-clk.h | 46 ++++
3 files changed, 335 insertions(+)
create mode 100644 drivers/clk/mtmips/clk-mt7621.c
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
diff --git a/drivers/clk/mtmips/Makefile b/drivers/clk/mtmips/Makefile
index 732e7f2545..ee8b5afe87 100644
--- a/drivers/clk/mtmips/Makefile
+++ b/drivers/clk/mtmips/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o
+obj-$(CONFIG_SOC_MT7621) += clk-mt7621.o
obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o
diff --git a/drivers/clk/mtmips/clk-mt7621.c b/drivers/clk/mtmips/clk-mt7621.c
new file mode 100644
index 0000000000..03363b70d7
--- /dev/null
+++ b/drivers/clk/mtmips/clk-mt7621.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <dt-bindings/clock/mt7621-clk.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+
+#define SYSC_MAP_SIZE 0x100
+#define MEMC_MAP_SIZE 0x1000
+
+/* SYSC */
+#define SYSCFG0_REG 0x10
+#define XTAL_MODE_SEL GENMASK(8, 6)
+
+#define CLKCFG0_REG 0x2c
+#define CPU_CLK_SEL GENMASK(31, 30)
+#define PERI_CLK_SEL BIT(4)
+
+#define CLKCFG1_REG 0x30
+
+#define CUR_CLK_STS_REG 0x44
+#define CUR_CPU_FDIV GENMASK(12, 8)
+#define CUR_CPU_FFRAC GENMASK(4, 0)
+
+/* MEMC */
+#define MEMPLL1_REG 0x0604
+#define RG_MEPL_DIV2_SEL GENMASK(2, 1)
+
+#define MEMPLL6_REG 0x0618
+#define MEMPLL18_REG 0x0648
+#define RG_MEPL_PREDIV GENMASK(13, 12)
+#define RG_MEPL_FBDIV GENMASK(10, 4)
+
+/* Fixed 500M clock */
+#define GMPLL_CLK 500000000
+
+struct mt7621_clk_priv {
+ void __iomem *sysc_base;
+ int cpu_clk;
+ int ddr_clk;
+ int sys_clk;
+ int xtal_clk;
+};
+
+enum mt7621_clk_src {
+ CLK_SRC_CPU,
+ CLK_SRC_DDR,
+ CLK_SRC_SYS,
+ CLK_SRC_XTAL,
+ CLK_SRC_PERI,
+ CLK_SRC_125M,
+ CLK_SRC_150M,
+ CLK_SRC_250M,
+ CLK_SRC_270M,
+
+ __CLK_SRC_MAX
+};
+
+struct mt7621_clk_map {
+ u32 cgbit;
+ enum mt7621_clk_src clksrc;
+};
+
+#define CLK_MAP(_id, _cg, _src) \
+ [_id] = { .cgbit = (_cg), .clksrc = (_src) }
+
+#define CLK_MAP_SRC(_id, _src) \
+ [_id] = { .cgbit = UINT32_MAX, .clksrc = (_src) }
+
+static const struct mt7621_clk_map mt7621_clk_mappings[] = {
+ CLK_MAP_SRC(MT7621_CLK_XTAL, CLK_SRC_XTAL),
+ CLK_MAP_SRC(MT7621_CLK_CPU, CLK_SRC_CPU),
+ CLK_MAP_SRC(MT7621_CLK_BUS, CLK_SRC_SYS),
+ CLK_MAP_SRC(MT7621_CLK_50M, CLK_SRC_PERI),
+ CLK_MAP_SRC(MT7621_CLK_125M, CLK_SRC_125M),
+ CLK_MAP_SRC(MT7621_CLK_150M, CLK_SRC_150M),
+ CLK_MAP_SRC(MT7621_CLK_250M, CLK_SRC_250M),
+ CLK_MAP_SRC(MT7621_CLK_270M, CLK_SRC_270M),
+
+ CLK_MAP(MT7621_CLK_HSDMA, 5, CLK_SRC_150M),
+ CLK_MAP(MT7621_CLK_FE, 6, CLK_SRC_250M),
+ CLK_MAP(MT7621_CLK_SP_DIVTX, 7, CLK_SRC_270M),
+ CLK_MAP(MT7621_CLK_TIMER, 8, CLK_SRC_PERI),
+ CLK_MAP(MT7621_CLK_PCM, 11, CLK_SRC_270M),
+ CLK_MAP(MT7621_CLK_PIO, 13, CLK_SRC_PERI),
+ CLK_MAP(MT7621_CLK_GDMA, 14, CLK_SRC_SYS),
+ CLK_MAP(MT7621_CLK_NAND, 15, CLK_SRC_125M),
+ CLK_MAP(MT7621_CLK_I2C, 16, CLK_SRC_PERI),
+ CLK_MAP(MT7621_CLK_I2S, 17, CLK_SRC_270M),
+ CLK_MAP(MT7621_CLK_SPI, 18, CLK_SRC_SYS),
+ CLK_MAP(MT7621_CLK_UART1, 19, CLK_SRC_PERI),
+ CLK_MAP(MT7621_CLK_UART2, 20, CLK_SRC_PERI),
+ CLK_MAP(MT7621_CLK_UART3, 21, CLK_SRC_PERI),
+ CLK_MAP(MT7621_CLK_ETH, 23, CLK_SRC_PERI),
+ CLK_MAP(MT7621_CLK_PCIE0, 24, CLK_SRC_125M),
+ CLK_MAP(MT7621_CLK_PCIE1, 25, CLK_SRC_125M),
+ CLK_MAP(MT7621_CLK_PCIE2, 26, CLK_SRC_125M),
+ CLK_MAP(MT7621_CLK_CRYPTO, 29, CLK_SRC_250M),
+ CLK_MAP(MT7621_CLK_SHXC, 30, CLK_SRC_PERI),
+
+ CLK_MAP_SRC(MT7621_CLK_MAX, __CLK_SRC_MAX),
+
+ CLK_MAP_SRC(MT7621_CLK_DDR, CLK_SRC_DDR),
+};
+
+static ulong mt7621_clk_get_rate(struct clk *clk)
+{
+ struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
+ u32 val;
+
+ switch (mt7621_clk_mappings[clk->id].clksrc) {
+ case CLK_SRC_CPU:
+ return priv->cpu_clk;
+ case CLK_SRC_DDR:
+ return priv->ddr_clk;
+ case CLK_SRC_SYS:
+ return priv->sys_clk;
+ case CLK_SRC_XTAL:
+ return priv->xtal_clk;
+ case CLK_SRC_PERI:
+ val = readl(priv->sysc_base + CLKCFG0_REG);
+ if (val & PERI_CLK_SEL)
+ return priv->xtal_clk;
+ else
+ return GMPLL_CLK / 10;
+ case CLK_SRC_125M:
+ return 125000000;
+ case CLK_SRC_150M:
+ return 150000000;
+ case CLK_SRC_250M:
+ return 250000000;
+ case CLK_SRC_270M:
+ return 270000000;
+ default:
+ return 0;
+ }
+}
+
+static int mt7621_clk_enable(struct clk *clk)
+{
+ struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
+ u32 cgbit;
+
+ cgbit = mt7621_clk_mappings[clk->id].cgbit;
+ if (cgbit == UINT32_MAX)
+ return -ENOSYS;
+
+ setbits_32(priv->sysc_base + CLKCFG1_REG, BIT(cgbit));
+
+ return 0;
+}
+
+static int mt7621_clk_disable(struct clk *clk)
+{
+ struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
+ u32 cgbit;
+
+ cgbit = mt7621_clk_mappings[clk->id].cgbit;
+ if (cgbit == UINT32_MAX)
+ return -ENOSYS;
+
+ clrbits_32(priv->sysc_base + CLKCFG1_REG, BIT(cgbit));
+
+ return 0;
+}
+
+static int mt7621_clk_request(struct clk *clk)
+{
+ if (clk->id >= ARRAY_SIZE(mt7621_clk_mappings))
+ return -EINVAL;
+ return 0;
+}
+
+const struct clk_ops mt7621_clk_ops = {
+ .request = mt7621_clk_request,
+ .enable = mt7621_clk_enable,
+ .disable = mt7621_clk_disable,
+ .get_rate = mt7621_clk_get_rate,
+};
+
+static void mt7621_get_clocks(struct mt7621_clk_priv *priv, struct regmap *memc)
+{
+ u32 bs, xtal_sel, clkcfg0, cur_clk, mempll, dividx, fb;
+ u32 xtal_clk, xtal_div, ffiv, ffrac, cpu_clk, ddr_clk;
+ static const u32 xtal_div_tbl[] = {0, 1, 2, 2};
+
+ bs = readl(priv->sysc_base + SYSCFG0_REG);
+ clkcfg0 = readl(priv->sysc_base + CLKCFG0_REG);
+ cur_clk = readl(priv->sysc_base + CUR_CLK_STS_REG);
+
+ xtal_sel = FIELD_GET(XTAL_MODE_SEL, bs);
+
+ if (xtal_sel <= 2)
+ xtal_clk = 20 * 1000 * 1000;
+ else if (xtal_sel <= 5)
+ xtal_clk = 40 * 1000 * 1000;
+ else
+ xtal_clk = 25 * 1000 * 1000;
+
+ switch (FIELD_GET(CPU_CLK_SEL, clkcfg0)) {
+ case 0:
+ cpu_clk = GMPLL_CLK;
+ break;
+ case 1:
+ regmap_read(memc, MEMPLL18_REG, &mempll);
+ dividx = FIELD_GET(RG_MEPL_PREDIV, mempll);
+ fb = FIELD_GET(RG_MEPL_FBDIV, mempll);
+ xtal_div = 1 << xtal_div_tbl[dividx];
+ cpu_clk = (fb + 1) * xtal_clk / xtal_div;
+ break;
+ default:
+ cpu_clk = xtal_clk;
+ }
+
+ ffiv = FIELD_GET(CUR_CPU_FDIV, cur_clk);
+ ffrac = FIELD_GET(CUR_CPU_FFRAC, cur_clk);
+ cpu_clk = cpu_clk / ffiv * ffrac;
+
+ regmap_read(memc, MEMPLL6_REG, &mempll);
+ dividx = FIELD_GET(RG_MEPL_PREDIV, mempll);
+ fb = FIELD_GET(RG_MEPL_FBDIV, mempll);
+ xtal_div = 1 << xtal_div_tbl[dividx];
+ ddr_clk = fb * xtal_clk / xtal_div;
+
+ regmap_read(memc, MEMPLL1_REG, &bs);
+ if (!FIELD_GET(RG_MEPL_DIV2_SEL, bs))
+ ddr_clk *= 2;
+
+ priv->cpu_clk = cpu_clk;
+ priv->sys_clk = cpu_clk / 4;
+ priv->ddr_clk = ddr_clk;
+ priv->xtal_clk = xtal_clk;
+}
+
+static int mt7621_clk_probe(struct udevice *dev)
+{
+ struct mt7621_clk_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args args;
+ struct udevice *pdev;
+ struct regmap *memc;
+ int ret;
+
+ pdev = dev_get_parent(dev);
+ if (!pdev)
+ return -ENODEV;
+
+ priv->sysc_base = dev_remap_addr(pdev);
+ if (!priv->sysc_base)
+ return -EINVAL;
+
+ /* get corresponding memc phandle */
+ ret = dev_read_phandle_with_args(dev, "mediatek,memc", NULL, 0, 0,
+ &args);
+ if (ret)
+ return ret;
+
+ memc = syscon_node_to_regmap(args.node);
+ if (IS_ERR(memc))
+ return PTR_ERR(memc);
+
+ mt7621_get_clocks(priv, memc);
+
+ return 0;
+}
+
+static const struct udevice_id mt7621_clk_ids[] = {
+ { .compatible = "mediatek,mt7621-clk" },
+ { }
+};
+
+U_BOOT_DRIVER(mt7621_clk) = {
+ .name = "mt7621-clk",
+ .id = UCLASS_CLK,
+ .of_match = mt7621_clk_ids,
+ .probe = mt7621_clk_probe,
+ .priv_auto = sizeof(struct mt7621_clk_priv),
+ .ops = &mt7621_clk_ops,
+};
diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index 0000000000..978c67951b
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_MT7621_CLK_H_
+#define _DT_BINDINGS_MT7621_CLK_H_
+
+#define MT7621_CLK_XTAL 0
+#define MT7621_CLK_CPU 1
+#define MT7621_CLK_BUS 2
+#define MT7621_CLK_50M 3
+#define MT7621_CLK_125M 4
+#define MT7621_CLK_150M 5
+#define MT7621_CLK_250M 6
+#define MT7621_CLK_270M 7
+
+#define MT7621_CLK_HSDMA 8
+#define MT7621_CLK_FE 9
+#define MT7621_CLK_SP_DIVTX 10
+#define MT7621_CLK_TIMER 11
+#define MT7621_CLK_PCM 12
+#define MT7621_CLK_PIO 13
+#define MT7621_CLK_GDMA 14
+#define MT7621_CLK_NAND 15
+#define MT7621_CLK_I2C 16
+#define MT7621_CLK_I2S 17
+#define MT7621_CLK_SPI 18
+#define MT7621_CLK_UART1 19
+#define MT7621_CLK_UART2 20
+#define MT7621_CLK_UART3 21
+#define MT7621_CLK_ETH 22
+#define MT7621_CLK_PCIE0 23
+#define MT7621_CLK_PCIE1 24
+#define MT7621_CLK_PCIE2 25
+#define MT7621_CLK_CRYPTO 26
+#define MT7621_CLK_SHXC 27
+
+#define MT7621_CLK_MAX 28
+
+/* for u-boot only */
+#define MT7621_CLK_DDR 29
+
+#endif /* _DT_BINDINGS_MT7621_CLK_H_ */
--
2.36.1

62
package/boot/uboot-mediatek/patches/001-mtk-0009-reset-mtmips-add-reset-controller-support-for-MediaT.patch Normal file
View File

@@ -0,0 +1,62 @@
From 03035a6566300808c8845799b2f9ceca471aa61a Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:22:41 +0800
Subject: [PATCH 09/25] reset: mtmips: add reset controller support for
MediaTek MT7621 SoC
This patch adds reset controller bits definition header file for MediaTek
MT7621 SoC
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
include/dt-bindings/reset/mt7621-reset.h | 38 ++++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 include/dt-bindings/reset/mt7621-reset.h
diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h
new file mode 100644
index 0000000000..8e4341f040
--- /dev/null
+++ b/include/dt-bindings/reset/mt7621-reset.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_MT7621_RESET_H_
+#define _DT_BINDINGS_MT7621_RESET_H_
+
+#define RST_PPE 31
+#define RST_SDXC 30
+#define RST_CRYPTO 29
+#define RST_AUX_STCK 28
+#define RST_PCIE2 26
+#define RST_PCIE1 25
+#define RST_PCIE0 24
+#define RST_GMAC 23
+#define RST_UART3 21
+#define RST_UART2 20
+#define RST_UART1 19
+#define RST_SPI 18
+#define RST_I2S 17
+#define RST_I2C 16
+#define RST_NFI 15
+#define RST_GDMA 14
+#define RST_PIO 13
+#define RST_PCM 11
+#define RST_MC 10
+#define RST_INTC 9
+#define RST_TIMER 8
+#define RST_SPDIFTX 7
+#define RST_FE 6
+#define RST_HSDMA 5
+#define RST_MCM 2
+#define RST_SYS 0
+
+#endif /* _DT_BINDINGS_MT7621_RESET_H_ */
--
2.36.1

409
package/boot/uboot-mediatek/patches/001-mtk-0010-pinctrl-mtmips-add-support-for-MediaTek-MT7621-SoC.patch Normal file
View File

@@ -0,0 +1,409 @@
From 3cf9e2daca330a0ba89d3793ceb09037c788db46 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:22:49 +0800
Subject: [PATCH 10/25] pinctrl: mtmips: add support for MediaTek MT7621 SoC
This patch adds pinctrl support for MediaTek MT7621 SoC.
The MT7621 SoC supports pinconf, but it is not the same as mt7628.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/pinctrl/mtmips/Kconfig | 9 +
drivers/pinctrl/mtmips/Makefile | 1 +
drivers/pinctrl/mtmips/pinctrl-mt7621.c | 306 ++++++++++++++++++
.../pinctrl/mtmips/pinctrl-mtmips-common.c | 4 +-
.../pinctrl/mtmips/pinctrl-mtmips-common.h | 12 +
5 files changed, 330 insertions(+), 2 deletions(-)
create mode 100644 drivers/pinctrl/mtmips/pinctrl-mt7621.c
diff --git a/drivers/pinctrl/mtmips/Kconfig b/drivers/pinctrl/mtmips/Kconfig
index 844d5b743f..456f3ea25d 100644
--- a/drivers/pinctrl/mtmips/Kconfig
+++ b/drivers/pinctrl/mtmips/Kconfig
@@ -12,6 +12,15 @@ config PINCTRL_MT7620
The driver is controlled by a device tree node which contains
the pin mux functions for each available pin groups.
+config PINCTRL_MT7621
+ bool "MediaTek MT7621 pin control driver"
+ select PINCTRL_MTMIPS
+ depends on SOC_MT7621 && PINCTRL_GENERIC
+ help
+ Support pin multiplexing control on MediaTek MT7621.
+ The driver is controlled by a device tree node which contains
+ the pin mux functions for each available pin groups.
+
config PINCTRL_MT7628
bool "MediaTek MT7628 pin control driver"
select PINCTRL_MTMIPS
diff --git a/drivers/pinctrl/mtmips/Makefile b/drivers/pinctrl/mtmips/Makefile
index ba945a89a7..8fece4f5fa 100644
--- a/drivers/pinctrl/mtmips/Makefile
+++ b/drivers/pinctrl/mtmips/Makefile
@@ -5,4 +5,5 @@ obj-$(CONFIG_PINCTRL_MTMIPS) += pinctrl-mtmips-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o
+obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o
obj-$(CONFIG_PINCTRL_MT7628) += pinctrl-mt7628.o
diff --git a/drivers/pinctrl/mtmips/pinctrl-mt7621.c b/drivers/pinctrl/mtmips/pinctrl-mt7621.c
new file mode 100644
index 0000000000..3e98a01bad
--- /dev/null
+++ b/drivers/pinctrl/mtmips/pinctrl-mt7621.c
@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#include "pinctrl-mtmips-common.h"
+
+#define SYSC_MAP_SIZE 0x100
+
+#define PAD_UART1_GPIO0_OFS 0x00
+#define PAD_UART3_I2C_OFS 0x04
+#define PAD_UART2_JTAG_OFS 0x08
+#define PAD_PERST_WDT_OFS 0x0c
+#define PAD_RGMII2_MDIO_OFS 0x10
+#define PAD_SDXC_SPI_OFS 0x14
+#define GPIOMODE_OFS 0x18
+#define PAD_BOPT_ESWINT_OFS 0x28
+
+#define ESWINT_SHIFT 20
+#define SDXC_SHIFT 18
+#define SPI_SHIFT 16
+#define RGMII2_SHIFT 15
+#define RGMII1_SHIFT 14
+#define MDIO_SHIFT 12
+#define PERST_SHIFT 10
+#define WDT_SHIFT 8
+#define JTAG_SHIFT 7
+#define UART2_SHIFT 5
+#define UART3_SHIFT 3
+#define I2C_SHIFT 2
+#define UART1_SHIFT 1
+#define GPIO0_SHIFT 0 /* Dummy */
+
+#define GM4_MASK 3
+
+#define E4_E2_M 0x03
+#define E4_E2_S 4
+#define PULL_UP BIT(3)
+#define PULL_DOWN BIT(2)
+#define SMT BIT(1)
+#define SR BIT(0)
+
+struct mt7621_pinctrl_priv {
+ struct mtmips_pinctrl_priv mp;
+};
+
+#if CONFIG_IS_ENABLED(PINMUX)
+static const struct mtmips_pmx_func esw_int_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("esw int", 0),
+};
+
+static const struct mtmips_pmx_func sdxc_grp[] = {
+ FUNC("nand", 2),
+ FUNC("gpio", 1),
+ FUNC("sdxc", 0),
+};
+
+static const struct mtmips_pmx_func spi_grp[] = {
+ FUNC("nand", 2),
+ FUNC("gpio", 1),
+ FUNC("spi", 0),
+};
+
+static const struct mtmips_pmx_func rgmii2_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("rgmii", 0),
+};
+
+static const struct mtmips_pmx_func rgmii1_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("rgmii", 0),
+};
+
+static const struct mtmips_pmx_func mdio_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("mdio", 0),
+};
+
+static const struct mtmips_pmx_func perst_grp[] = {
+ FUNC("refclk", 2),
+ FUNC("gpio", 1),
+ FUNC("pcie reset", 0),
+};
+
+static const struct mtmips_pmx_func wdt_grp[] = {
+ FUNC("refclk", 2),
+ FUNC("gpio", 1),
+ FUNC("wdt rst", 0),
+};
+
+static const struct mtmips_pmx_func jtag_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("jtag", 0),
+};
+
+static const struct mtmips_pmx_func uart2_grp[] = {
+ FUNC("spdif", 3),
+ FUNC("pcm", 2),
+ FUNC("gpio", 1),
+ FUNC("uart", 0),
+};
+
+static const struct mtmips_pmx_func uart3_grp[] = {
+ FUNC("spdif", 3),
+ FUNC("i2s", 2),
+ FUNC("gpio", 1),
+ FUNC("uart", 0),
+};
+
+static const struct mtmips_pmx_func i2c_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("i2c", 0),
+};
+
+static const struct mtmips_pmx_func uart1_grp[] = {
+ FUNC("gpio", 1),
+ FUNC("uart", 0),
+};
+
+static const struct mtmips_pmx_func gpio0_grp[] = {
+ FUNC("gpio", 0),
+};
+
+static const struct mtmips_pmx_group mt7621_pmx_data[] = {
+ GRP_PCONF("esw int", esw_int_grp, GPIOMODE_OFS, ESWINT_SHIFT, 1,
+ PAD_BOPT_ESWINT_OFS, 0),
+ GRP_PCONF("sdxc", sdxc_grp, GPIOMODE_OFS, SDXC_SHIFT, GM4_MASK,
+ PAD_SDXC_SPI_OFS, 16),
+ GRP_PCONF("spi", spi_grp, GPIOMODE_OFS, SPI_SHIFT, GM4_MASK,
+ PAD_SDXC_SPI_OFS, 0),
+ GRP_PCONF("rgmii2", rgmii2_grp, GPIOMODE_OFS, RGMII2_SHIFT, 1,
+ PAD_RGMII2_MDIO_OFS, 16),
+ GRP("rgmii1", rgmii1_grp, GPIOMODE_OFS, RGMII1_SHIFT, 1),
+ GRP_PCONF("mdio", mdio_grp, GPIOMODE_OFS, MDIO_SHIFT, GM4_MASK,
+ PAD_RGMII2_MDIO_OFS, 0),
+ GRP_PCONF("pcie reset", perst_grp, GPIOMODE_OFS, PERST_SHIFT, GM4_MASK,
+ PAD_PERST_WDT_OFS, 16),
+ GRP_PCONF("wdt", wdt_grp, GPIOMODE_OFS, WDT_SHIFT, GM4_MASK,
+ PAD_PERST_WDT_OFS, 0),
+ GRP_PCONF("jtag", jtag_grp, GPIOMODE_OFS, JTAG_SHIFT, 1,
+ PAD_UART2_JTAG_OFS, 16),
+ GRP_PCONF("uart2", uart2_grp, GPIOMODE_OFS, UART2_SHIFT, GM4_MASK,
+ PAD_UART2_JTAG_OFS, 0),
+ GRP_PCONF("uart3", uart3_grp, GPIOMODE_OFS, UART3_SHIFT, GM4_MASK,
+ PAD_UART3_I2C_OFS, 16),
+ GRP_PCONF("i2c", i2c_grp, GPIOMODE_OFS, I2C_SHIFT, 1,
+ PAD_UART3_I2C_OFS, 0),
+ GRP_PCONF("uart1", uart1_grp, GPIOMODE_OFS, UART1_SHIFT, 1,
+ PAD_UART1_GPIO0_OFS, 16),
+ GRP_PCONF("gpio0", gpio0_grp, GPIOMODE_OFS, GPIO0_SHIFT, 1,
+ PAD_UART1_GPIO0_OFS, 0),
+};
+
+static int mt7621_get_groups_count(struct udevice *dev)
+{
+ return ARRAY_SIZE(mt7621_pmx_data);
+}
+
+static const char *mt7621_get_group_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return mt7621_pmx_data[selector].name;
+}
+#endif /* CONFIG_IS_ENABLED(PINMUX) */
+
+#if CONFIG_IS_ENABLED(PINCONF)
+static const struct pinconf_param mt7621_conf_params[] = {
+ { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+ { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
+ { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
+ { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
+ { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
+ { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
+ { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
+};
+
+static const u32 mt7621_pconf_drv_strength_tbl[] = {2, 4, 6, 8};
+
+static int mt7621_pinconf_group_set(struct udevice *dev,
+ unsigned int group_selector,
+ unsigned int param, unsigned int arg)
+{
+ struct mt7621_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct mtmips_pmx_group *grp = &mt7621_pmx_data[group_selector];
+ u32 clr = 0, set = 0;
+ int i;
+
+ if (!grp->pconf_avail)
+ return 0;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ clr = PULL_UP | PULL_DOWN;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ clr = PULL_DOWN;
+ set = PULL_UP;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ clr = PULL_UP;
+ set = PULL_DOWN;
+ break;
+
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (arg)
+ set = SMT;
+ else
+ clr = SMT;
+ break;
+
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ for (i = 0; i < ARRAY_SIZE(mt7621_pconf_drv_strength_tbl); i++)
+ if (mt7621_pconf_drv_strength_tbl[i] == arg)
+ break;
+
+ if (i >= ARRAY_SIZE(mt7621_pconf_drv_strength_tbl))
+ return -EINVAL;
+
+ clr = E4_E2_M << E4_E2_S;
+ set = i << E4_E2_S;
+ break;
+
+ case PIN_CONFIG_SLEW_RATE:
+ if (arg)
+ set = SR;
+ else
+ clr = SR;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ mtmips_pinctrl_reg_set(&priv->mp, grp->pconf_reg, grp->pconf_shift,
+ clr, set);
+
+ return 0;
+}
+#endif
+
+static int mt7621_pinctrl_probe(struct udevice *dev)
+{
+ struct mt7621_pinctrl_priv *priv = dev_get_priv(dev);
+ int ret = 0;
+
+#if CONFIG_IS_ENABLED(PINMUX)
+ ret = mtmips_pinctrl_probe(&priv->mp, ARRAY_SIZE(mt7621_pmx_data),
+ mt7621_pmx_data);
+#endif /* CONFIG_IS_ENABLED(PINMUX) */
+
+ return ret;
+}
+
+static int mt7621_pinctrl_of_to_plat(struct udevice *dev)
+{
+ struct mt7621_pinctrl_priv *priv = dev_get_priv(dev);
+
+ priv->mp.base = (void __iomem *)dev_remap_addr_index(dev, 0);
+
+ if (!priv->mp.base)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct pinctrl_ops mt7621_pinctrl_ops = {
+#if CONFIG_IS_ENABLED(PINMUX)
+ .get_groups_count = mt7621_get_groups_count,
+ .get_group_name = mt7621_get_group_name,
+ .get_functions_count = mtmips_get_functions_count,
+ .get_function_name = mtmips_get_function_name,
+ .pinmux_group_set = mtmips_pinmux_group_set,
+#endif /* CONFIG_IS_ENABLED(PINMUX) */
+#if CONFIG_IS_ENABLED(PINCONF)
+ .pinconf_num_params = ARRAY_SIZE(mt7621_conf_params),
+ .pinconf_params = mt7621_conf_params,
+ .pinconf_group_set = mt7621_pinconf_group_set,
+#endif /* CONFIG_IS_ENABLED(PINCONF) */
+ .set_state = pinctrl_generic_set_state,
+};
+
+static const struct udevice_id mt7621_pinctrl_ids[] = {
+ { .compatible = "mediatek,mt7621-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(mt7621_pinctrl) = {
+ .name = "mt7621-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = mt7621_pinctrl_ids,
+ .of_to_plat = mt7621_pinctrl_of_to_plat,
+ .ops = &mt7621_pinctrl_ops,
+ .probe = mt7621_pinctrl_probe,
+ .priv_auto = sizeof(struct mt7621_pinctrl_priv),
+};
diff --git a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c
index e361916eb2..869b781068 100644
--- a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c
+++ b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c
@@ -13,8 +13,8 @@
#include "pinctrl-mtmips-common.h"
-static void mtmips_pinctrl_reg_set(struct mtmips_pinctrl_priv *priv,
- u32 reg, u32 shift, u32 mask, u32 value)
+void mtmips_pinctrl_reg_set(struct mtmips_pinctrl_priv *priv,
+ u32 reg, u32 shift, u32 mask, u32 value)
{
u32 val;
diff --git a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h
index b51d8f009c..1f1023ef42 100644
--- a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h
+++ b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h
@@ -22,6 +22,10 @@ struct mtmips_pmx_group {
u32 shift;
char mask;
+ int pconf_avail;
+ u32 pconf_reg;
+ u32 pconf_shift;
+
int nfuncs;
const struct mtmips_pmx_func *funcs;
};
@@ -42,6 +46,14 @@ struct mtmips_pinctrl_priv {
{ .name = (_name), .reg = (_reg), .shift = (_shift), .mask = (_mask), \
.funcs = (_funcs), .nfuncs = ARRAY_SIZE(_funcs) }
+#define GRP_PCONF(_name, _funcs, _reg, _shift, _mask, _pconf_reg, _pconf_shift) \
+ { .name = (_name), .reg = (_reg), .shift = (_shift), .mask = (_mask), \
+ .funcs = (_funcs), .nfuncs = ARRAY_SIZE(_funcs), .pconf_avail = 1, \
+ .pconf_reg = (_pconf_reg), .pconf_shift = (_pconf_shift) }
+
+void mtmips_pinctrl_reg_set(struct mtmips_pinctrl_priv *priv,
+ u32 reg, u32 shift, u32 mask, u32 value);
+
int mtmips_get_functions_count(struct udevice *dev);
const char *mtmips_get_function_name(struct udevice *dev,
unsigned int selector);
--
2.36.1

28
package/boot/uboot-mediatek/patches/001-mtk-0011-usb-xhci-mtk-add-support-for-MediaTek-MT7621-SoC.patch Normal file
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@@ -0,0 +1,28 @@
From ab59bb14a0efd40c12a967f73bd08ba2f27da3be Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:22:56 +0800
Subject: [PATCH 11/25] usb: xhci-mtk: add support for MediaTek MT7621 SoC
This patch makes xhci-mtk driver available for MediaTek MT7621 SoC
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/usb/host/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 8f77412cc7..8f7bfe1602 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -34,7 +34,7 @@ config USB_XHCI_DWC3_OF_SIMPLE
config USB_XHCI_MTK
bool "Support for MediaTek on-chip xHCI USB controller"
- depends on ARCH_MEDIATEK
+ depends on ARCH_MEDIATEK || SOC_MT7621
help
Enables support for the on-chip xHCI controller on MediaTek SoCs.
--
2.36.1

28
package/boot/uboot-mediatek/patches/001-mtk-0012-phy-mtk-tphy-add-support-for-MediaTek-MT7621-SoC.patch Normal file
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@@ -0,0 +1,28 @@
From 23c19fa476929b6e94cc7f1a55f5ed4d3ab03934 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:23:01 +0800
Subject: [PATCH 12/25] phy: mtk-tphy: add support for MediaTek MT7621 SoC
This patch makes mtk-tphy driver available for MediaTek MT7621 SoC
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/phy/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c01d9e09b9..1708d4f533 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -266,7 +266,7 @@ config MT76X8_USB_PHY
config PHY_MTK_TPHY
bool "MediaTek T-PHY Driver"
depends on PHY
- depends on ARCH_MEDIATEK
+ depends on ARCH_MEDIATEK || SOC_MT7621
help
MediaTek T-PHY driver supports usb2.0, usb3.0 ports, PCIe and
SATA, and meanwhile supports two version T-PHY which have
--
2.36.1

28
package/boot/uboot-mediatek/patches/001-mtk-0013-spi-add-support-for-MediaTek-MT7621-SoC.patch Normal file
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@@ -0,0 +1,28 @@
From 34b623ccfd135e846b8464729a8b0e8df4b77a66 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:23:08 +0800
Subject: [PATCH 13/25] spi: add support for MediaTek MT7621 SoC
This patch makes mt7621_spi driver available for MediaTek MT7621 SoC
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/spi/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a1e515cb2b..2923ed8db3 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -240,7 +240,7 @@ config MT7620_SPI
config MT7621_SPI
bool "MediaTek MT7621 SPI driver"
- depends on SOC_MT7628
+ depends on SOC_MT7621 || SOC_MT7628
help
Enable the MT7621 SPI driver. This driver can be used to access
the SPI NOR flash on platforms embedding this Ralink / MediaTek
--
2.36.1

29
package/boot/uboot-mediatek/patches/001-mtk-0014-gpio-add-support-for-MediaTek-MT7621-SoC.patch Normal file
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@@ -0,0 +1,29 @@
From f265423a441a3bcb51e25238544adb69f74becc7 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:23:14 +0800
Subject: [PATCH 14/25] gpio: add support for MediaTek MT7621 SoC
This patch makes mt7621_gpio driver available for MediaTek MT7621 SoC
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/gpio/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d7f37f0471..8f7e630098 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -553,7 +553,7 @@ config MT7620_GPIO
config MT7621_GPIO
bool "MediaTek MT7621 GPIO driver"
- depends on DM_GPIO && SOC_MT7628
+ depends on DM_GPIO && (SOC_MT7621 || SOC_MT7628)
default y
help
Say yes here to support MediaTek MT7621 compatible GPIOs.
--
2.36.1

29
package/boot/uboot-mediatek/patches/001-mtk-0015-watchdog-add-support-for-MediaTek-MT7621-SoC.patch Normal file
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@@ -0,0 +1,29 @@
From eb1806fbf65c60b2ce462a0ebe39d9f9e652235a Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:23:19 +0800
Subject: [PATCH 15/25] watchdog: add support for MediaTek MT7621 SoC
This patch makes mt7621_wdt driver available for MediaTek MT7621 SoC
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/watchdog/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index c3eb8a8aec..dfb02aa468 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -191,7 +191,7 @@ config WDT_MT7620
config WDT_MT7621
bool "MediaTek MT7621 watchdog timer support"
- depends on WDT && SOC_MT7628
+ depends on WDT && (SOC_MT7621 || SOC_MT7628)
help
Select this to enable Ralink / Mediatek watchdog timer,
which can be found on some MediaTek chips.
--
2.36.1

47
package/boot/uboot-mediatek/patches/001-mtk-0016-mmc-mediatek-add-support-for-MediaTek-MT7621-SoC.patch Normal file
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@@ -0,0 +1,47 @@
From 4339ec44313e85dd1f6d3d708dd2e594855ce25d Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:23:26 +0800
Subject: [PATCH 16/25] mmc: mediatek: add support for MediaTek MT7621 SoC
This patch adds SDXC support for MediaTek MT7621 SoC
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mmc/mtk-sd.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index 97182ffd7f..e61e8cf4b9 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -1761,6 +1761,18 @@ static const struct msdc_compatible mt7620_compat = {
.default_pad_dly = true,
};
+static const struct msdc_compatible mt7621_compat = {
+ .clk_div_bits = 8,
+ .pad_tune0 = false,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = false,
+ .stop_clk_fix = false,
+ .enhance_rx = false,
+ .builtin_pad_ctrl = true,
+ .default_pad_dly = true,
+};
+
static const struct msdc_compatible mt7622_compat = {
.clk_div_bits = 12,
.pad_tune0 = true,
@@ -1809,6 +1821,7 @@ static const struct msdc_compatible mt8183_compat = {
static const struct udevice_id msdc_ids[] = {
{ .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
+ { .compatible = "mediatek,mt7621-mmc", .data = (ulong)&mt7621_compat },
{ .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat },
{ .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
{ .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat },
--
2.36.1

38
package/boot/uboot-mediatek/patches/001-mtk-0017-net-mediatek-remap-iobase-address.patch Normal file
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@@ -0,0 +1,38 @@
From 391785398f61c85e6b55b1e9edbab94e3ba1b783 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:23:31 +0800
Subject: [PATCH 17/25] net: mediatek: remap iobase address
The iobase address from dts node is actually physical address. It's
identical to the virtual address in ARM platform. This is ok because this
driver was used only by ARM platforms (mt7622/mt7623 ...).
But now this driver will be used by mt7621 which is a MIPS SoC. For MIPS
platform the physical address space is mapped to KSEG0 and KSEG1 and this
makes the virtual address apparently not idential to its physical address.
To solve this issue, this patch replaces dev_read_addr with dev_remap_addr
to get the remapped iobase address.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
index 666ddeb10d..caa83b7cec 100644
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1419,7 +1419,7 @@ static int mtk_eth_of_to_plat(struct udevice *dev)
priv->soc = dev_get_driver_data(dev);
- pdata->iobase = dev_read_addr(dev);
+ pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
/* get corresponding ethsys phandle */
ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0,
--
2.36.1

72
package/boot/uboot-mediatek/patches/001-mtk-0018-net-mediatek-use-regmap-api-to-modify-ethsys-registe.patch Normal file
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@@ -0,0 +1,72 @@
From 955cc76d8074df943d59d559895007f91de8eed5 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:23:37 +0800
Subject: [PATCH 18/25] net: mediatek: use regmap api to modify ethsys
registers
The address returned by regmap_get_range() is not remapped. Directly r/w
to this address is ok for ARM platforms since it's idential to the virtual
address.
But for MIPS platform only virtual address should be used for access.
To solve this issue, the regmap api regmap_read/regmap_write should be used
since they will remap address before accessing.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
index caa83b7cec..ac1e8abd71 100644
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -159,9 +159,10 @@ struct mtk_eth_priv {
void __iomem *fe_base;
void __iomem *gmac_base;
- void __iomem *ethsys_base;
void __iomem *sgmii_base;
+ struct regmap *ethsys_regmap;
+
struct mii_dev *mdio_bus;
int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
@@ -233,7 +234,12 @@ static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
u32 set)
{
- clrsetbits_le32(priv->ethsys_base + reg, clr, set);
+ uint val;
+
+ regmap_read(priv->ethsys_regmap, reg, &val);
+ val &= ~clr;
+ val |= set;
+ regmap_write(priv->ethsys_regmap, reg, val);
}
/* Direct MDIO clause 22/45 access via SoC */
@@ -1427,15 +1433,9 @@ static int mtk_eth_of_to_plat(struct udevice *dev)
if (ret)
return ret;
- regmap = syscon_node_to_regmap(args.node);
- if (IS_ERR(regmap))
- return PTR_ERR(regmap);
-
- priv->ethsys_base = regmap_get_range(regmap, 0);
- if (!priv->ethsys_base) {
- dev_err(dev, "Unable to find ethsys\n");
- return -ENODEV;
- }
+ priv->ethsys_regmap = syscon_node_to_regmap(args.node);
+ if (IS_ERR(priv->ethsys_regmap))
+ return PTR_ERR(priv->ethsys_regmap);
/* Reset controllers */
ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
--
2.36.1

72
package/boot/uboot-mediatek/patches/001-mtk-0019-net-mediatek-add-support-for-MediaTek-MT7621-SoC.patch Normal file
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@@ -0,0 +1,72 @@
From 7237a6a0c020c05bb819774391154b40b2cfaabd Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:23:42 +0800
Subject: [PATCH 19/25] net: mediatek: add support for MediaTek MT7621 SoC
This patch adds GMAC support for MediaTek MT7621 SoC.
MT7621 has the same GMAC/Switch configuration as MT7623.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/net/mtk_eth.c | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
index ac1e8abd71..4fe7ee0d36 100644
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -145,7 +145,8 @@ enum mtk_switch {
enum mtk_soc {
SOC_MT7623,
SOC_MT7629,
- SOC_MT7622
+ SOC_MT7622,
+ SOC_MT7621
};
struct mtk_eth_priv {
@@ -675,12 +676,18 @@ static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode)
static int mt7530_setup(struct mtk_eth_priv *priv)
{
u16 phy_addr, phy_val;
- u32 val;
+ u32 val, txdrv;
int i;
- /* Select 250MHz clk for RGMII mode */
- mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
- ETHSYS_TRGMII_CLK_SEL362_5, 0);
+ if (priv->soc != SOC_MT7621) {
+ /* Select 250MHz clk for RGMII mode */
+ mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
+ ETHSYS_TRGMII_CLK_SEL362_5, 0);
+
+ txdrv = 8;
+ } else {
+ txdrv = 4;
+ }
/* Modify HWTRAP first to allow direct access to internal PHYs */
mt753x_reg_read(priv, HWTRAP_REG, &val);
@@ -738,7 +745,8 @@ static int mt7530_setup(struct mtk_eth_priv *priv)
/* Lower Tx Driving for TRGMII path */
for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i),
- (8 << TD_DM_DRVP_S) | (8 << TD_DM_DRVN_S));
+ (txdrv << TD_DM_DRVP_S) |
+ (txdrv << TD_DM_DRVN_S));
for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16);
@@ -1540,6 +1548,7 @@ static const struct udevice_id mtk_eth_ids[] = {
{ .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 },
{ .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 },
{ .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 },
+ { .compatible = "mediatek,mt7621-eth", .data = SOC_MT7621 },
{}
};
--
2.36.1

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package/boot/uboot-mediatek/patches/001-mtk-0020-nand-raw-add-support-for-MediaTek-MT7621-SoC.patch Normal file
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File diff suppressed because it is too large Load Diff

29
package/boot/uboot-mediatek/patches/001-mtk-0021-spl-allow-using-nand-base-without-standard-nand-driv.patch Normal file
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@@ -0,0 +1,29 @@
From 474082b03ae2b569f9daf43f78b91b57f7a1ae50 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:23:53 +0800
Subject: [PATCH 21/25] spl: allow using nand base without standard nand driver
This patch removes the dependency to SPL_NAND_DRIVERS for SPL_NAND_BASE to
allow minimal spl nand driver to use nand base for probing NAND chips.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
common/spl/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 50ff113cab..eee9315e43 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -764,7 +764,7 @@ config SPL_NAND_SIMPLE
expose the cmd_ctrl() interface.
config SPL_NAND_BASE
- depends on SPL_NAND_DRIVERS
+ depends on SPL_NAND_SUPPORT
bool "Use Base NAND Driver"
help
Include nand_base.c in the SPL.
--
2.36.1

69
package/boot/uboot-mediatek/patches/001-mtk-0022-spl-spl_legacy-fix-the-use-of-SPL_COPY_PAYLOAD_ONLY.patch Normal file
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@@ -0,0 +1,69 @@
From ba9c81e720f39b5dbc14592252bfc9402afee79d Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:23:58 +0800
Subject: [PATCH 22/25] spl: spl_legacy: fix the use of SPL_COPY_PAYLOAD_ONLY
If the payload is compressed, SPL_COPY_PAYLOAD_ONLY should always be set
since the payload will not be directly read to its load address. The
payload will first be read to a temporary buffer, and then be decompressed
to its load address, without image header.
If the payload is not compressed, and SPL_COPY_PAYLOAD_ONLY is set, image
header should be skipped on loading. Otherwise image header should also be
read to its load address.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
common/spl/spl_legacy.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c
index 2ec7154423..ae8731c782 100644
--- a/common/spl/spl_legacy.c
+++ b/common/spl/spl_legacy.c
@@ -88,15 +88,29 @@ int spl_load_legacy_img(struct spl_image_info *spl_image,
/* Read header into local struct */
load->read(load, header, sizeof(hdr), &hdr);
+ /*
+ * If the payload is compressed, the decompressed data should be
+ * directly write to its load address.
+ */
+ if (spl_image_get_comp(&hdr) != IH_COMP_NONE)
+ spl_image->flags |= SPL_COPY_PAYLOAD_ONLY;
+
ret = spl_parse_image_header(spl_image, bootdev, &hdr);
if (ret)
return ret;
- dataptr = header + sizeof(hdr);
-
/* Read image */
switch (spl_image_get_comp(&hdr)) {
case IH_COMP_NONE:
+ dataptr = header;
+
+ /*
+ * Image header will be skipped only if SPL_COPY_PAYLOAD_ONLY
+ * is set
+ */
+ if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY)
+ dataptr += sizeof(hdr);
+
load->read(load, dataptr, spl_image->size,
(void *)(unsigned long)spl_image->load_addr);
break;
@@ -104,6 +118,9 @@ int spl_load_legacy_img(struct spl_image_info *spl_image,
case IH_COMP_LZMA:
lzma_len = LZMA_LEN;
+ /* dataptr points to compressed payload */
+ dataptr = header + sizeof(hdr);
+
debug("LZMA: Decompressing %08lx to %08lx\n",
dataptr, spl_image->load_addr);
src = malloc(spl_image->size);
--
2.36.1

64
package/boot/uboot-mediatek/patches/001-mtk-0023-spl-nand-support-loading-legacy-image-with-payload-c.patch Normal file
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@@ -0,0 +1,64 @@
From b4e5137067d34a099efd921532ece177560789ca Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:24:04 +0800
Subject: [PATCH 23/25] spl: nand: support loading legacy image with payload
compressed
Add support to load legacy image with payload compressed. This redirects
the boot flow for all legacy images. If the payload is not compressed, the
actual behavior will remain unchanged.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
common/spl/spl_nand.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 82a10ffa63..7b7579a2df 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -56,6 +56,21 @@ static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs,
return size / load->bl_len;
}
+static ulong spl_nand_legacy_read(struct spl_load_info *load, ulong offs,
+ ulong size, void *dst)
+{
+ int err;
+
+ debug("%s: offs %lx, size %lx, dst %p\n",
+ __func__, offs, size, dst);
+
+ err = nand_spl_load_image(offs, size, dst);
+ if (err)
+ return 0;
+
+ return size;
+}
+
struct mtd_info * __weak nand_get_mtd(void)
{
return NULL;
@@ -93,6 +108,18 @@ static int spl_nand_load_element(struct spl_image_info *spl_image,
load.bl_len = bl_len;
load.read = spl_nand_fit_read;
return spl_load_imx_container(spl_image, &load, offset / bl_len);
+ } else if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT) &&
+ image_get_magic(header) == IH_MAGIC) {
+ struct spl_load_info load;
+
+ debug("Found legacy image\n");
+ load.dev = NULL;
+ load.priv = NULL;
+ load.filename = NULL;
+ load.bl_len = 1;
+ load.read = spl_nand_legacy_read;
+
+ return spl_load_legacy_img(spl_image, bootdev, &load, offset);
} else {
err = spl_parse_image_header(spl_image, bootdev, header);
if (err)
--
2.36.1

340
package/boot/uboot-mediatek/patches/001-mtk-0024-tools-mtk_image-add-support-for-MT7621-NAND-images.patch Normal file
View File

@@ -0,0 +1,340 @@
From 18dd1ef9417d0880f2f492b55bd4d9ede499f137 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:24:10 +0800
Subject: [PATCH 24/25] tools: mtk_image: add support for MT7621 NAND images
The BootROM of MT7621 requires a image header for SPL to record its size
and load address when booting from NAND.
To create such an image, one can use the following command line:
mkimage -T mtk_image -a 0x80200000 -e 0x80200000 -n "mt7621=1"
-d u-boot-spl-ddr.bin u-boot-spl-ddr.img
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
tools/mtk_image.c | 182 ++++++++++++++++++++++++++++++++++++++++++++++
tools/mtk_image.h | 24 ++++++
2 files changed, 206 insertions(+)
diff --git a/tools/mtk_image.c b/tools/mtk_image.c
index 418c5fd54b..de5ce4d964 100644
--- a/tools/mtk_image.c
+++ b/tools/mtk_image.c
@@ -6,7 +6,9 @@
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
+#include <time.h>
#include <image.h>
+#include <u-boot/crc.h>
#include <u-boot/sha256.h>
#include "imagetool.h"
#include "mtk_image.h"
@@ -251,17 +253,45 @@ static uint32_t img_size;
static enum brlyt_img_type hdr_media;
static uint32_t hdr_offset;
static int use_lk_hdr;
+static int use_mt7621_hdr;
static bool is_arm64_image;
/* LK image name */
static char lk_name[32] = "U-Boot";
+/* CRC32 normal table required by MT7621 image */
+static uint32_t crc32tbl[256];
+
/* NAND header selected by user */
static const union nand_boot_header *hdr_nand;
/* GFH header + 2 * 4KB pages of NAND */
static char hdr_tmp[sizeof(struct gfh_header) + 0x2000];
+static uint32_t crc32_normal_cal(uint32_t crc, const void *data, size_t length,
+ const uint32_t *crc32c_table)
+{
+ const uint8_t *p = data;
+
+ while (length--)
+ crc = crc32c_table[(uint8_t)((crc >> 24) ^ *p++)] ^ (crc << 8);
+
+ return crc;
+}
+
+static void crc32_normal_init(uint32_t *crc32c_table, uint32_t poly)
+{
+ uint32_t v, i, j;
+
+ for (i = 0; i < 256; i++) {
+ v = i << 24;
+ for (j = 0; j < 8; j++)
+ v = (v << 1) ^ ((v & (1 << 31)) ? poly : 0);
+
+ crc32c_table[i] = v;
+ }
+}
+
static int mtk_image_check_image_types(uint8_t type)
{
if (type == IH_TYPE_MTKIMAGE)
@@ -283,6 +313,7 @@ static int mtk_brom_parse_imagename(const char *imagename)
static const char *hdr_offs = "";
static const char *nandinfo = "";
static const char *lk = "";
+ static const char *mt7621 = "";
static const char *arm64_param = "";
key = buf;
@@ -332,6 +363,9 @@ static int mtk_brom_parse_imagename(const char *imagename)
if (!strcmp(key, "lk"))
lk = val;
+ if (!strcmp(key, "mt7621"))
+ mt7621 = val;
+
if (!strcmp(key, "lkname"))
snprintf(lk_name, sizeof(lk_name), "%s", val);
@@ -352,6 +386,13 @@ static int mtk_brom_parse_imagename(const char *imagename)
return 0;
}
+ /* if user specified MT7621 image header, skip following checks */
+ if (mt7621 && mt7621[0] == '1') {
+ use_mt7621_hdr = 1;
+ free(buf);
+ return 0;
+ }
+
/* parse media type */
for (i = 0; i < ARRAY_SIZE(brom_images); i++) {
if (!strcmp(brom_images[i].name, media)) {
@@ -419,6 +460,13 @@ static int mtk_image_vrec_header(struct image_tool_params *params,
return 0;
}
+ if (use_mt7621_hdr) {
+ tparams->header_size = image_get_header_size();
+ tparams->hdr = &hdr_tmp;
+ memset(&hdr_tmp, 0, tparams->header_size);
+ return 0;
+ }
+
if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND)
tparams->header_size = 2 * le16_to_cpu(hdr_nand->pagesize);
else
@@ -579,9 +627,90 @@ static int mtk_image_verify_nand_header(const uint8_t *ptr, int print)
return 0;
}
+static uint32_t crc32be_cal(const void *data, size_t length)
+{
+ uint32_t crc = 0;
+ uint8_t c;
+
+ if (crc32tbl[1] != MT7621_IH_CRC_POLYNOMIAL)
+ crc32_normal_init(crc32tbl, MT7621_IH_CRC_POLYNOMIAL);
+
+ crc = crc32_normal_cal(crc, data, length, crc32tbl);
+
+ for (; length; length >>= 8) {
+ c = length & 0xff;
+ crc = crc32_normal_cal(crc, &c, 1, crc32tbl);
+ }
+
+ return ~crc;
+}
+
+static int mtk_image_verify_mt7621_header(const uint8_t *ptr, int print)
+{
+ const image_header_t *hdr = (const image_header_t *)ptr;
+ struct mt7621_nand_header *nhdr;
+ uint32_t spl_size, crcval;
+ image_header_t header;
+ int ret;
+
+ spl_size = image_get_size(hdr);
+
+ if (spl_size > img_size) {
+ if (print)
+ printf("Incomplete SPL image\n");
+ return -1;
+ }
+
+ ret = image_check_hcrc(hdr);
+ if (!ret) {
+ if (print)
+ printf("Bad header CRC\n");
+ return -1;
+ }
+
+ ret = image_check_dcrc(hdr);
+ if (!ret) {
+ if (print)
+ printf("Bad data CRC\n");
+ return -1;
+ }
+
+ /* Copy header so we can blank CRC field for re-calculation */
+ memmove(&header, hdr, image_get_header_size());
+ image_set_hcrc(&header, 0);
+
+ nhdr = (struct mt7621_nand_header *)header.ih_name;
+ crcval = be32_to_cpu(nhdr->crc);
+ nhdr->crc = 0;
+
+ if (crcval != crc32be_cal(&header, image_get_header_size())) {
+ if (print)
+ printf("Bad NAND header CRC\n");
+ return -1;
+ }
+
+ if (print) {
+ printf("Load Address: %08x\n", image_get_load(hdr));
+
+ printf("Image Name: %.*s\n", MT7621_IH_NMLEN,
+ image_get_name(hdr));
+
+ if (IMAGE_ENABLE_TIMESTAMP) {
+ printf("Created: ");
+ genimg_print_time((time_t)image_get_time(hdr));
+ }
+
+ printf("Data Size: ");
+ genimg_print_size(image_get_data_size(hdr));
+ }
+
+ return 0;
+}
+
static int mtk_image_verify_header(unsigned char *ptr, int image_size,
struct image_tool_params *params)
{
+ image_header_t *hdr = (image_header_t *)ptr;
union lk_hdr *lk = (union lk_hdr *)ptr;
/* nothing to verify for LK image header */
@@ -590,6 +719,9 @@ static int mtk_image_verify_header(unsigned char *ptr, int image_size,
img_size = image_size;
+ if (image_get_magic(hdr) == IH_MAGIC)
+ return mtk_image_verify_mt7621_header(ptr, 0);
+
if (!strcmp((char *)ptr, NAND_BOOT_NAME))
return mtk_image_verify_nand_header(ptr, 0);
else
@@ -600,6 +732,7 @@ static int mtk_image_verify_header(unsigned char *ptr, int image_size,
static void mtk_image_print_header(const void *ptr)
{
+ image_header_t *hdr = (image_header_t *)ptr;
union lk_hdr *lk = (union lk_hdr *)ptr;
if (le32_to_cpu(lk->magic) == LK_PART_MAGIC) {
@@ -610,6 +743,11 @@ static void mtk_image_print_header(const void *ptr)
printf("Image Type: MediaTek BootROM Loadable Image\n");
+ if (image_get_magic(hdr) == IH_MAGIC) {
+ mtk_image_verify_mt7621_header(ptr, 1);
+ return;
+ }
+
if (!strcmp((char *)ptr, NAND_BOOT_NAME))
mtk_image_verify_nand_header(ptr, 1);
else
@@ -773,6 +911,45 @@ static void mtk_image_set_nand_header(void *ptr, off_t filesize,
filesize - 2 * le16_to_cpu(hdr_nand->pagesize) - SHA256_SUM_LEN);
}
+static void mtk_image_set_mt7621_header(void *ptr, off_t filesize,
+ uint32_t loadaddr)
+{
+ image_header_t *hdr = (image_header_t *)ptr;
+ struct mt7621_stage1_header *shdr;
+ struct mt7621_nand_header *nhdr;
+ uint32_t datasize, crcval;
+
+ datasize = filesize - image_get_header_size();
+ nhdr = (struct mt7621_nand_header *)hdr->ih_name;
+ shdr = (struct mt7621_stage1_header *)(ptr + image_get_header_size());
+
+ shdr->ep = cpu_to_be32(loadaddr);
+ shdr->stage_size = cpu_to_be32(datasize);
+
+ image_set_magic(hdr, IH_MAGIC);
+ image_set_time(hdr, time(NULL));
+ image_set_size(hdr, datasize);
+ image_set_load(hdr, loadaddr);
+ image_set_ep(hdr, loadaddr);
+ image_set_os(hdr, IH_OS_U_BOOT);
+ image_set_arch(hdr, IH_ARCH_MIPS);
+ image_set_type(hdr, IH_TYPE_STANDALONE);
+ image_set_comp(hdr, IH_COMP_NONE);
+
+ crcval = crc32(0, (uint8_t *)shdr, datasize);
+ image_set_dcrc(hdr, crcval);
+
+ strncpy(nhdr->ih_name, "MT7621 NAND", MT7621_IH_NMLEN);
+
+ nhdr->ih_stage_offset = cpu_to_be32(image_get_header_size());
+
+ crcval = crc32be_cal(hdr, image_get_header_size());
+ nhdr->crc = cpu_to_be32(crcval);
+
+ crcval = crc32(0, (uint8_t *)hdr, image_get_header_size());
+ image_set_hcrc(hdr, crcval);
+}
+
static void mtk_image_set_header(void *ptr, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
@@ -791,6 +968,11 @@ static void mtk_image_set_header(void *ptr, struct stat *sbuf, int ifd,
img_gen = true;
img_size = sbuf->st_size;
+ if (use_mt7621_hdr) {
+ mtk_image_set_mt7621_header(ptr, sbuf->st_size, params->addr);
+ return;
+ }
+
if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND)
mtk_image_set_nand_header(ptr, sbuf->st_size, params->addr);
else
diff --git a/tools/mtk_image.h b/tools/mtk_image.h
index 7dda71ce88..d868545a33 100644
--- a/tools/mtk_image.h
+++ b/tools/mtk_image.h
@@ -200,4 +200,28 @@ union lk_hdr {
#define LK_PART_MAGIC 0x58881688
+/* MT7621 NAND SPL image header */
+
+#define MT7621_IH_NMLEN 12
+#define MT7621_IH_CRC_POLYNOMIAL 0x04c11db7
+
+struct mt7621_nand_header {
+ char ih_name[MT7621_IH_NMLEN];
+ uint32_t nand_ac_timing;
+ uint32_t ih_stage_offset;
+ uint32_t ih_bootloader_offset;
+ uint32_t nand_info_1_data;
+ uint32_t crc;
+};
+
+struct mt7621_stage1_header {
+ uint32_t jump_insn[2];
+ uint32_t ep;
+ uint32_t stage_size;
+ uint32_t has_stage2;
+ uint32_t next_ep;
+ uint32_t next_size;
+ uint32_t next_offset;
+};
+
#endif /* _MTK_IMAGE_H */
--
2.36.1

44
package/boot/uboot-mediatek/patches/001-mtk-0025-MAINTAINERS-update-maintainer-for-MediaTek-MIPS-plat.patch Normal file
View File

@@ -0,0 +1,44 @@
From e5fc4022af3cfd59e3459276305671a595ac5ff0 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Fri, 20 May 2022 11:24:16 +0800
Subject: [PATCH 25/25] MAINTAINERS: update maintainer for MediaTek MIPS
platform
Update maintainer for MediaTek MIPS platform
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7f27ff4c20..d8d060bd92 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1007,15 +1007,23 @@ R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
S: Maintained
F: arch/mips/mach-mtmips/
F: arch/mips/dts/mt7620.dtsi
+F: arch/mips/dts/mt7621.dtsi
F: arch/mips/dts/mt7620-u-boot.dtsi
+F: arch/mips/dts/mt7621-u-boot.dtsi
F: include/configs/mt7620.h
+F: include/configs/mt7621.h
F: include/dt-bindings/clock/mt7620-clk.h
+F: include/dt-bindings/clock/mt7621-clk.h
F: include/dt-bindings/clock/mt7628-clk.h
F: include/dt-bindings/reset/mt7620-reset.h
+F: include/dt-bindings/reset/mt7621-reset.h
F: include/dt-bindings/reset/mt7628-reset.h
F: drivers/clk/mtmips/
F: drivers/pinctrl/mtmips/
F: drivers/gpio/mt7620_gpio.c
+F: drivers/mtd/nand/raw/mt7621_nand.c
+F: drivers/mtd/nand/raw/mt7621_nand.h
+F: drivers/mtd/nand/raw/mt7621_nand_spl.c
F: drivers/net/mt7620-eth.c
F: drivers/phy/mt7620-usb-phy.c
F: drivers/reset/reset-mtmips.c
--
2.36.1

5
package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch
View File

@@ -420,7 +420,7 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@@ -392,6 +393,21 @@ static int initr_onenand(void) @@ -392,6 +393,20 @@ static int initr_onenand(void)
} }
#endif #endif
@@ -432,9 +432,8 @@
+ +
+spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, +spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS,
+ CONFIG_SF_DEFAULT_CS, + CONFIG_SF_DEFAULT_CS,
+ CONFIG_SF_DEFAULT_SPEED,
+ CONFIG_SF_DEFAULT_MODE,
+ &new); + &new);
+
+ return 0; + return 0;
+} +}
+#endif +#endif

107
package/boot/uboot-ramips/patches/0001-add-support-for-RAVPower-RP-WD009.patch → package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch
View File

@@ -20,23 +20,16 @@ Subject: [PATCH] add support for RAVPower RP-WD009
create mode 100644 configs/ravpower-rp-wd009-ram_defconfig create mode 100644 configs/ravpower-rp-wd009-ram_defconfig
create mode 100644 include/configs/ravpower-rp-wd009.h create mode 100644 include/configs/ravpower-rp-wd009.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index c9d75596f2..23868ae1d2 100644
--- a/arch/mips/dts/Makefile --- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile
@@ -2,7 +2,8 @@ @@ -25,6 +25,7 @@ dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += m
dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb
dtb-$(CONFIG_ARCH_MTMIPS) += \ dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
gardena-smart-gateway-mt7688.dtb \ dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
- linkit-smart-7688.dtb +dtb-$(CONFIG_BOARD_RAVPOWER_RP_WD009) += ravpower-rp-wd009.dtb
+ linkit-smart-7688.dtb \ dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
+ ravpower-rp-wd009.dtb dtb-$(CONFIG_BOARD_SFR_NB4_SER) += sfr,nb4-ser.dtb
dtb-$(CONFIG_TARGET_AP121) += ap121.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
dtb-$(CONFIG_TARGET_AP152) += ap152.dtb
diff --git a/arch/mips/dts/ravpower-rp-wd009.dts b/arch/mips/dts/ravpower-rp-wd009.dts
new file mode 100644
index 0000000000..b271d5bfbc
--- /dev/null --- /dev/null
+++ b/arch/mips/dts/ravpower-rp-wd009.dts +++ b/arch/mips/dts/ravpower-rp-wd009.dts
@@ -0,0 +1,50 @@ @@ -0,0 +1,50 @@
@@ -90,36 +83,6 @@ index 0000000000..b271d5bfbc
+ pinctrl-names = "default"; + pinctrl-names = "default";
+ pinctrl-0 = <&ephy_router_mode>; + pinctrl-0 = <&ephy_router_mode>;
+}; +};
diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig
index c8dcf19c0d..85ac8878ab 100644
--- a/arch/mips/mach-mtmips/Kconfig
+++ b/arch/mips/mach-mtmips/Kconfig
@@ -32,6 +32,14 @@ config BOARD_GARDENA_SMART_GATEWAY_MT7688
GARDENA smart Gateway boards have a MT7688 SoC with 128 MiB of RAM
and 8 MiB of flash (SPI NOR) and additional SPI NAND storage.
+config BOARD_RAVPOWER_RP_WD009
+ bool "RAVPower RP-WD009"
+ depends on SOC_MT7628
+ select BOARD_LATE_INIT
+ select SUPPORTS_BOOT_RAM
+ help
+ RAVPower RP-WD009
+
config BOARD_LINKIT_SMART_7688
bool "LinkIt Smart 7688"
depends on SOC_MT7628
@@ -133,6 +141,7 @@ config SUPPORTS_BOOT_RAM
bool
source "board/gardena/smart-gateway-mt7688/Kconfig"
+source "board/ravpower/rp-wd009/Kconfig"
source "board/seeed/linkit-smart-7688/Kconfig"
endmenu
diff --git a/board/ravpower/rp-wd009/Kconfig b/board/ravpower/rp-wd009/Kconfig
new file mode 100644
index 0000000000..111f8e4478
--- /dev/null --- /dev/null
+++ b/board/ravpower/rp-wd009/Kconfig +++ b/board/ravpower/rp-wd009/Kconfig
@@ -0,0 +1,12 @@ @@ -0,0 +1,12 @@
@@ -135,18 +98,12 @@ index 0000000000..111f8e4478
+ default "ravpower-rp-wd009" + default "ravpower-rp-wd009"
+ +
+endif +endif
diff --git a/board/ravpower/rp-wd009/Makefile b/board/ravpower/rp-wd009/Makefile
new file mode 100644
index 0000000000..70cd7a8e56
--- /dev/null --- /dev/null
+++ b/board/ravpower/rp-wd009/Makefile +++ b/board/ravpower/rp-wd009/Makefile
@@ -0,0 +1,3 @@ @@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+ +# SPDX-License-Identifier: GPL-2.0+
+ +
+obj-y += board.o +obj-y += board.o
diff --git a/board/ravpower/rp-wd009/board.c b/board/ravpower/rp-wd009/board.c
new file mode 100644
index 0000000000..eabcf85735
--- /dev/null --- /dev/null
+++ b/board/ravpower/rp-wd009/board.c +++ b/board/ravpower/rp-wd009/board.c
@@ -0,0 +1,16 @@ @@ -0,0 +1,16 @@
@@ -166,16 +123,14 @@ index 0000000000..eabcf85735
+{ +{
+ return 0; + return 0;
+} +}
diff --git a/configs/ravpower-rp-wd009-ram_defconfig b/configs/ravpower-rp-wd009-ram_defconfig
new file mode 100644
index 0000000000..08cbf40638
--- /dev/null --- /dev/null
+++ b/configs/ravpower-rp-wd009-ram_defconfig +++ b/configs/ravpower-rp-wd009-ram_defconfig
@@ -0,0 +1,59 @@ @@ -0,0 +1,61 @@
+CONFIG_MIPS=y +CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_SYS_LOAD_ADDR=0x80010000
+CONFIG_NR_DRAM_BANKS=1 +CONFIG_NR_DRAM_BANKS=1
+CONFIG_ARCH_MTMIPS=y +CONFIG_ARCH_MTMIPS=y
+CONFIG_SOC_MT7628=y
+CONFIG_MIPS_BOOT_FDT=y +CONFIG_MIPS_BOOT_FDT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_OF_STDOUT_VIA_ALIAS=y
@@ -185,7 +140,6 @@ index 0000000000..08cbf40638
+CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y +CONFIG_VERSION_VARIABLE=y
+CONFIG_BOARD_RAVPOWER_RP_WD009=y +CONFIG_BOARD_RAVPOWER_RP_WD009=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y +CONFIG_HUSH_PARSER=y
+CONFIG_CMD_LICENSE=y +CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_ELF is not set +# CONFIG_CMD_ELF is not set
@@ -203,6 +157,8 @@ index 0000000000..08cbf40638
+CONFIG_CMD_TIME=y +CONFIG_CMD_TIME=y
+CONFIG_CMD_UUID=y +CONFIG_CMD_UUID=y
+CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_MTDPARTS=y
+CONFIG_FIT=y
+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" +CONFIG_MTDIDS_DEFAULT="nor0=spi0.0"
+CONFIG_MTDPARTS_DEFAULT="spi0.0:192k(factory-uboot),64k(config),64k(factory),1536k(loader),64k(params),64k(user_backup),64k(user),14272k(firmware),64k(mode)" +CONFIG_MTDPARTS_DEFAULT="spi0.0:192k(factory-uboot),64k(config),64k(factory),1536k(loader),64k(params),64k(user_backup),64k(user),14272k(firmware),64k(mode)"
+CONFIG_DEFAULT_DEVICE_TREE="ravpower-rp-wd009" +CONFIG_DEFAULT_DEVICE_TREE="ravpower-rp-wd009"
@@ -231,12 +187,9 @@ index 0000000000..08cbf40638
+CONFIG_WDT_MT7621=y +CONFIG_WDT_MT7621=y
+CONFIG_LZMA=y +CONFIG_LZMA=y
+CONFIG_BAUDRATE=57600 +CONFIG_BAUDRATE=57600
diff --git a/include/configs/ravpower-rp-wd009.h b/include/configs/ravpower-rp-wd009.h
new file mode 100644
index 0000000000..bb4145197c
--- /dev/null --- /dev/null
+++ b/include/configs/ravpower-rp-wd009.h +++ b/include/configs/ravpower-rp-wd009.h
@@ -0,0 +1,48 @@ @@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0+ */
+/* +/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de> + * Copyright (C) 2018 Stefan Roese <sr@denx.de>
@@ -251,8 +204,6 @@ index 0000000000..bb4145197c
+/* RAM */ +/* RAM */
+#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_BASE 0x80000000
+ +
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+ +
+#ifdef CONFIG_BOOT_RAM +#ifdef CONFIG_BOOT_RAM
@@ -269,13 +220,9 @@ index 0000000000..bb4145197c
+ +
+/* Memory usage */ +/* Memory usage */
+#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
+#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_CBSIZE 512
+ +
+/* U-Boot */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+/* Environment settings */ +/* Environment settings */
+ +
+/* +/*
@@ -285,6 +232,28 @@ index 0000000000..bb4145197c
+#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET +#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
+ +
+#endif /* __CONFIG_RAVPOWER_RP_WD009_H */ +#endif /* __CONFIG_RAVPOWER_RP_WD009_H */
-- --- a/arch/mips/mach-mtmips/mt7628/Kconfig
2.27.0 +++ b/arch/mips/mach-mtmips/mt7628/Kconfig
@@ -27,6 +27,14 @@ config BOARD_MT7628_RFB
SPI-NOR flash, 1 built-in switch with 5 ports, 1 UART, 1 USB host,
1 SDXC, 1 PCIe socket and JTAG pins.
+config BOARD_RAVPOWER_RP_WD009
+ bool "RAVPower RP-WD009"
+ depends on SOC_MT7628
+ select BOARD_LATE_INIT
+ select SUPPORTS_BOOT_RAM
+ help
+ RAVPower RP-WD009
+
config BOARD_VOCORE2
bool "VoCore2"
select SPL_SERIAL
@@ -53,6 +61,7 @@ config SYS_CONFIG_NAME
default "mt7628" if BOARD_MT7628_RFB
source "board/gardena/smart-gateway-mt7688/Kconfig"
+source "board/ravpower/rp-wd009/Kconfig"
source "board/seeed/linkit-smart-7688/Kconfig"
source "board/vocore/vocore2/Kconfig"

34
package/boot/uboot-ramips/Makefile
View File

@@ -1,34 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2020.04
PKG_RELEASE:=$(AUTORELEASE)
PKG_HASH:=fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
define U-Boot/Default
BUILD_TARGET:=ramips
UBOOT_IMAGE:=u-boot.bin
endef
define U-Boot/ravpower_rp-wd009
BUILD_DEVICES:=ravpower_rp-wd009
BUILD_SUBTARGET:=mt76x8
NAME:=RAVPower RP-WD009
UBOOT_CONFIG:=ravpower-rp-wd009-ram
endef
UBOOT_TARGETS := \
ravpower_rp-wd009
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(VARIANT)-$(UBOOT_IMAGE)
endef
$(eval $(call BuildPackage/U-Boot))