ipq40xx: fix hw-crypto detection of qce driver
This adds the CRYPTO_ALG_KERN_DRIVER_ONLY flag to Qualcomm crypto engine driver algorithms, so that openssl devcrypto can recognize them as hardware-accelerated. Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com> [refresh, move to ipq40xx as its the only target right now] Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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			| @@ -0,0 +1,31 @@ | ||||
| From: Eneas U de Queiroz <cotequeiroz@gmail.com> | ||||
| Subject: [PATCH] crypto: qce - add CRYPTO_ALG_KERN_DRIVER_ONLY flag | ||||
|  | ||||
| Set the CRYPTO_ALG_KERN_DRIVER_ONLY flag to all algorithms exposed by | ||||
| the qce driver, since they are all hardware accelerated, accessible | ||||
| through a kernel driver only, and not available directly to userspace. | ||||
|  | ||||
| Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com> | ||||
|  | ||||
| --- a/drivers/crypto/qce/ablkcipher.c | ||||
| +++ b/drivers/crypto/qce/ablkcipher.c | ||||
| @@ -373,7 +373,7 @@ static int qce_ablkcipher_register_one(c | ||||
|   | ||||
|  	alg->cra_priority = 300; | ||||
|  	alg->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC | | ||||
| -			 CRYPTO_ALG_NEED_FALLBACK; | ||||
| +			 CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY; | ||||
|  	alg->cra_ctxsize = sizeof(struct qce_cipher_ctx); | ||||
|  	alg->cra_alignmask = 0; | ||||
|  	alg->cra_type = &crypto_ablkcipher_type; | ||||
| --- a/drivers/crypto/qce/sha.c | ||||
| +++ b/drivers/crypto/qce/sha.c | ||||
| @@ -526,7 +526,7 @@ static int qce_ahash_register_one(const | ||||
|  	base = &alg->halg.base; | ||||
|  	base->cra_blocksize = def->blocksize; | ||||
|  	base->cra_priority = 300; | ||||
| -	base->cra_flags = CRYPTO_ALG_ASYNC; | ||||
| +	base->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY; | ||||
|  	base->cra_ctxsize = sizeof(struct qce_sha_ctx); | ||||
|  	base->cra_alignmask = 0; | ||||
|  	base->cra_module = THIS_MODULE; | ||||
| @@ -0,0 +1,31 @@ | ||||
| From: Eneas U de Queiroz <cotequeiroz@gmail.com> | ||||
| Subject: [PATCH] crypto: qce - add CRYPTO_ALG_KERN_DRIVER_ONLY flag | ||||
|  | ||||
| Set the CRYPTO_ALG_KERN_DRIVER_ONLY flag to all algorithms exposed by | ||||
| the qce driver, since they are all hardware accelerated, accessible | ||||
| through a kernel driver only, and not available directly to userspace. | ||||
|  | ||||
| Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com> | ||||
|  | ||||
| --- a/drivers/crypto/qce/ablkcipher.c | ||||
| +++ b/drivers/crypto/qce/ablkcipher.c | ||||
| @@ -370,7 +370,7 @@ static int qce_ablkcipher_register_one(c | ||||
|   | ||||
|  	alg->cra_priority = 300; | ||||
|  	alg->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC | | ||||
| -			 CRYPTO_ALG_NEED_FALLBACK; | ||||
| +			 CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_KERN_DRIVER_ONLY; | ||||
|  	alg->cra_ctxsize = sizeof(struct qce_cipher_ctx); | ||||
|  	alg->cra_alignmask = 0; | ||||
|  	alg->cra_type = &crypto_ablkcipher_type; | ||||
| --- a/drivers/crypto/qce/sha.c | ||||
| +++ b/drivers/crypto/qce/sha.c | ||||
| @@ -503,7 +503,7 @@ static int qce_ahash_register_one(const | ||||
|  	base = &alg->halg.base; | ||||
|  	base->cra_blocksize = def->blocksize; | ||||
|  	base->cra_priority = 300; | ||||
| -	base->cra_flags = CRYPTO_ALG_ASYNC; | ||||
| +	base->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY; | ||||
|  	base->cra_ctxsize = sizeof(struct qce_sha_ctx); | ||||
|  	base->cra_alignmask = 0; | ||||
|  	base->cra_module = THIS_MODULE; | ||||
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