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ath25: add kernel 4.14 support

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Copy and refresh patches and config from 4.9, no more work is need.

Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
This commit is contained in:
Sergey Ryazanov
2018-05-21 12:19:29 +03:00
committed by John Crispin
parent 9c0ddafd46
commit 3d69857ac1
12 changed files with 3865 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

171
target/linux/ath25/config-4.14 Normal file
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@@ -0,0 +1,171 @@
CONFIG_ADM6996_PHY=y
CONFIG_AR2315_WDT=y
CONFIG_AR8216_PHY=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
# CONFIG_ARCH_HAS_SG_CHAIN is not set
# CONFIG_ARCH_HAS_STRICT_KERNEL_RWX is not set
# CONFIG_ARCH_HAS_STRICT_MODULE_RWX is not set
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_ARCH_MMAP_RND_BITS_MAX=15
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_ATH25=y
CONFIG_BLK_MQ_PCI=y
CONFIG_CEVT_R4K=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPS32_R1=y
CONFIG_CPU_MIPSR1=y
CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
CONFIG_CPU_R4K_CACHE_TLB=y
CONFIG_CPU_R4K_FPU=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CSRC_R4K=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_EARLY_PRINTK=y
CONFIG_ETHERNET_PACKET_MANGLE=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_AR2315=y
CONFIG_GPIO_AR5312=y
CONFIG_GPIO_SYSFS=y
# CONFIG_GRO_CELLS is not set
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
# CONFIG_HAVE_ARCH_BITREVERSE is not set
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_HAVE_CBPF_JIT=y
CONFIG_HAVE_CC_STACKPROTECTOR=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_COPY_THREAD_TLS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_NET_DSA=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
CONFIG_HZ_PERIODIC=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IP17XX_PHY=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MIPS_CPU=y
CONFIG_IRQ_WORK=y
CONFIG_LEDS_GPIO=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MIPS=y
CONFIG_MIPS_ASID_BITS=8
CONFIG_MIPS_ASID_SHIFT=0
CONFIG_MIPS_CLOCK_VSYSCALL=y
# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_MIPS_MACHINE is not set
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_AR2315=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
# CONFIG_MTD_CFI_GEOMETRY is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_MYLOADER_PARTS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MVSWITCH_PHY=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
CONFIG_NET_AR231X=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
# CONFIG_NO_IOPORT_MAP is not set
# CONFIG_OF is not set
CONFIG_PCI=y
CONFIG_PCI_AR2315=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DRIVERS_LEGACY=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
# CONFIG_RCU_NEED_SEGCBLIST is not set
# CONFIG_RCU_STALL_COMMON is not set
# CONFIG_SCHED_INFO is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SERIAL_8250_FSL is not set
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SOC_AR2315=y
CONFIG_SOC_AR5312=y
CONFIG_SRCU=y
# CONFIG_SWAP is not set
CONFIG_SWCONFIG=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TINY_SRCU=y
CONFIG_USB_SUPPORT=y

212
target/linux/ath25/patches-4.14/107-ar5312_gpio.patch Normal file
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@@ -0,0 +1,212 @@
--- a/arch/mips/ath25/Kconfig
+++ b/arch/mips/ath25/Kconfig
@@ -2,6 +2,7 @@
config SOC_AR5312
bool "Atheros AR5312/AR2312+ SoC support"
depends on ATH25
+ select GPIO_AR5312
default y
config SOC_AR2315
--- a/arch/mips/ath25/ar5312.c
+++ b/arch/mips/ath25/ar5312.c
@@ -22,6 +22,7 @@
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/reboot.h>
+#include <linux/gpio.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/time.h>
@@ -180,6 +181,22 @@ static struct platform_device ar5312_phy
.num_resources = 1,
};
+static struct resource ar5312_gpio_res[] = {
+ {
+ .name = "ar5312-gpio",
+ .flags = IORESOURCE_MEM,
+ .start = AR5312_GPIO_BASE,
+ .end = AR5312_GPIO_BASE + AR5312_GPIO_SIZE - 1,
+ },
+};
+
+static struct platform_device ar5312_gpio = {
+ .name = "ar5312-gpio",
+ .id = -1,
+ .resource = ar5312_gpio_res,
+ .num_resources = ARRAY_SIZE(ar5312_gpio_res),
+};
+
static void __init ar5312_flash_init(void)
{
void __iomem *flashctl_base;
@@ -247,6 +264,8 @@ void __init ar5312_init_devices(void)
platform_device_register(&ar5312_physmap_flash);
+ platform_device_register(&ar5312_gpio);
+
switch (ath25_soc) {
case ATH25_SOC_AR5312:
if (!ath25_board.radio)
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -105,6 +105,13 @@ config GPIO_AMDPT
driver for GPIO functionality on Promontory IOHub
Require ACPI ASL code to enumerate as a platform device.
+config GPIO_AR5312
+ bool "AR5312 SoC GPIO support"
+ default y if SOC_AR5312
+ depends on SOC_AR5312
+ help
+ Say yes here to enable GPIO support for Atheros AR5312/AR2312+ SoCs.
+
config GPIO_ASPEED
tristate "Aspeed GPIO support"
depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-alte
obj-$(CONFIG_GPIO_ALTERA_A10SR) += gpio-altera-a10sr.o
obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o
+obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o
obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o
obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o
--- /dev/null
+++ b/drivers/gpio/gpio-ar5312.c
@@ -0,0 +1,121 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
+ * Copyright (C) 2006 FON Technology, SL.
+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>
+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+
+#define DRIVER_NAME "ar5312-gpio"
+
+#define AR5312_GPIO_DO 0x00 /* output register */
+#define AR5312_GPIO_DI 0x04 /* intput register */
+#define AR5312_GPIO_CR 0x08 /* control register */
+
+#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
+#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
+#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
+#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
+#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
+
+#define AR5312_GPIO_NUM 8
+
+static void __iomem *ar5312_mem;
+
+static inline u32 ar5312_gpio_reg_read(unsigned reg)
+{
+ return __raw_readl(ar5312_mem + reg);
+}
+
+static inline void ar5312_gpio_reg_write(unsigned reg, u32 val)
+{
+ __raw_writel(val, ar5312_mem + reg);
+}
+
+static inline void ar5312_gpio_reg_mask(unsigned reg, u32 mask, u32 val)
+{
+ ar5312_gpio_reg_write(reg, (ar5312_gpio_reg_read(reg) & ~mask) | val);
+}
+
+static int ar5312_gpio_get_val(struct gpio_chip *chip, unsigned gpio)
+{
+ return (ar5312_gpio_reg_read(AR5312_GPIO_DI) >> gpio) & 1;
+}
+
+static void ar5312_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val)
+{
+ u32 reg = ar5312_gpio_reg_read(AR5312_GPIO_DO);
+
+ reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio);
+ ar5312_gpio_reg_write(AR5312_GPIO_DO, reg);
+}
+
+static int ar5312_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
+{
+ ar5312_gpio_reg_mask(AR5312_GPIO_CR, 0, 1 << gpio);
+ return 0;
+}
+
+static int ar5312_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val)
+{
+ ar5312_gpio_reg_mask(AR5312_GPIO_CR, 1 << gpio, 0);
+ ar5312_gpio_set_val(chip, gpio, val);
+ return 0;
+}
+
+static struct gpio_chip ar5312_gpio_chip = {
+ .label = DRIVER_NAME,
+ .direction_input = ar5312_gpio_dir_in,
+ .direction_output = ar5312_gpio_dir_out,
+ .set = ar5312_gpio_set_val,
+ .get = ar5312_gpio_get_val,
+ .base = 0,
+ .ngpio = AR5312_GPIO_NUM,
+};
+
+static int ar5312_gpio_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ int ret;
+
+ if (ar5312_mem)
+ return -EBUSY;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ar5312_mem = devm_ioremap_resource(dev, res);
+ if (IS_ERR(ar5312_mem))
+ return PTR_ERR(ar5312_mem);
+
+ ar5312_gpio_chip.parent = dev;
+ ret = gpiochip_add(&ar5312_gpio_chip);
+ if (ret) {
+ dev_err(dev, "failed to add gpiochip\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct platform_driver ar5312_gpio_driver = {
+ .probe = ar5312_gpio_probe,
+ .driver = {
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
+ }
+};
+
+static int __init ar5312_gpio_init(void)
+{
+ return platform_driver_register(&ar5312_gpio_driver);
+}
+subsys_initcall(ar5312_gpio_init);
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -174,6 +174,7 @@ config ATH25
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
+ select GPIOLIB
select IRQ_MIPS_CPU
select IRQ_DOMAIN
select SYS_HAS_CPU_MIPS32_R1

363
target/linux/ath25/patches-4.14/108-ar2315_gpio.patch Normal file
View File

@@ -0,0 +1,363 @@
--- a/arch/mips/ath25/Kconfig
+++ b/arch/mips/ath25/Kconfig
@@ -8,6 +8,7 @@ config SOC_AR5312
config SOC_AR2315
bool "Atheros AR2315+ SoC support"
depends on ATH25
+ select GPIO_AR2315
default y
config PCI_AR2315
--- a/arch/mips/ath25/ar2315.c
+++ b/arch/mips/ath25/ar2315.c
@@ -21,6 +21,8 @@
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/time.h>
@@ -167,11 +169,42 @@ void __init ar2315_arch_init_irq(void)
ar2315_misc_irq_domain = domain;
}
+static struct resource ar2315_gpio_res[] = {
+ {
+ .name = "ar2315-gpio",
+ .flags = IORESOURCE_MEM,
+ .start = AR2315_RST_BASE + AR2315_GPIO,
+ .end = AR2315_RST_BASE + AR2315_GPIO + 0x10 - 1,
+ },
+ {
+ .name = "ar2315-gpio",
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "ar2315-gpio-irq-base",
+ .flags = IORESOURCE_IRQ,
+ .start = AR231X_GPIO_IRQ_BASE,
+ .end = AR231X_GPIO_IRQ_BASE,
+ }
+};
+
+static struct platform_device ar2315_gpio = {
+ .id = -1,
+ .name = "ar2315-gpio",
+ .resource = ar2315_gpio_res,
+ .num_resources = ARRAY_SIZE(ar2315_gpio_res)
+};
+
void __init ar2315_init_devices(void)
{
/* Find board configuration */
ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
+ ar2315_gpio_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
+ AR2315_MISC_IRQ_GPIO);
+ ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
+ platform_device_register(&ar2315_gpio);
+
ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
}
@@ -187,8 +220,8 @@ static void ar2315_restart(char *command
/* Cold reset does not work on the AR2315/6, use the GPIO reset bits
* a workaround. Give it some time to attempt a gpio based hardware
* reset (atheros reference design workaround) */
-
- /* TODO: implement the GPIO reset workaround */
+ gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
+ mdelay(100);
/* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
* workaround. Attempt to jump to the mips reset location -
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -105,6 +105,13 @@ config GPIO_AMDPT
driver for GPIO functionality on Promontory IOHub
Require ACPI ASL code to enumerate as a platform device.
+config GPIO_AR2315
+ bool "AR2315 SoC GPIO support"
+ default y if SOC_AR2315
+ depends on SOC_AR2315
+ help
+ Say yes here to enable GPIO support for Atheros AR2315+ SoCs.
+
config GPIO_AR5312
bool "AR5312 SoC GPIO support"
default y if SOC_AR5312
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-alte
obj-$(CONFIG_GPIO_ALTERA_A10SR) += gpio-altera-a10sr.o
obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o
+obj-$(CONFIG_GPIO_AR2315) += gpio-ar2315.o
obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o
obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o
--- /dev/null
+++ b/drivers/gpio/gpio-ar2315.c
@@ -0,0 +1,233 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
+ * Copyright (C) 2006 FON Technology, SL.
+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2006 Felix Fietkau <nbd@nbd.name>
+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+
+#define DRIVER_NAME "ar2315-gpio"
+
+#define AR2315_GPIO_DI 0x0000
+#define AR2315_GPIO_DO 0x0008
+#define AR2315_GPIO_DIR 0x0010
+#define AR2315_GPIO_INT 0x0018
+
+#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
+#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
+#define AR2315_GPIO_DIR_I(x) (0) /* input */
+
+#define AR2315_GPIO_INT_NUM_M 0x3F /* mask for GPIO num */
+#define AR2315_GPIO_INT_TRIG(x) ((x) << 6) /* interrupt trigger */
+#define AR2315_GPIO_INT_TRIG_M (0x3 << 6) /* mask for int trig */
+
+#define AR2315_GPIO_INT_TRIG_OFF 0 /* Triggerring off */
+#define AR2315_GPIO_INT_TRIG_LOW 1 /* Low Level Triggered */
+#define AR2315_GPIO_INT_TRIG_HIGH 2 /* High Level Triggered */
+#define AR2315_GPIO_INT_TRIG_EDGE 3 /* Edge Triggered */
+
+#define AR2315_GPIO_NUM 22
+
+static u32 ar2315_gpio_intmask;
+static u32 ar2315_gpio_intval;
+static unsigned ar2315_gpio_irq_base;
+static void __iomem *ar2315_mem;
+
+static inline u32 ar2315_gpio_reg_read(unsigned reg)
+{
+ return __raw_readl(ar2315_mem + reg);
+}
+
+static inline void ar2315_gpio_reg_write(unsigned reg, u32 val)
+{
+ __raw_writel(val, ar2315_mem + reg);
+}
+
+static inline void ar2315_gpio_reg_mask(unsigned reg, u32 mask, u32 val)
+{
+ ar2315_gpio_reg_write(reg, (ar2315_gpio_reg_read(reg) & ~mask) | val);
+}
+
+static void ar2315_gpio_irq_handler(struct irq_desc *desc)
+{
+ u32 pend;
+ int bit = -1;
+
+ /* only do one gpio interrupt at a time */
+ pend = ar2315_gpio_reg_read(AR2315_GPIO_DI);
+ pend ^= ar2315_gpio_intval;
+ pend &= ar2315_gpio_intmask;
+
+ if (pend) {
+ bit = fls(pend) - 1;
+ pend &= ~(1 << bit);
+ ar2315_gpio_intval ^= (1 << bit);
+ }
+
+ /* Enable interrupt with edge detection */
+ if ((ar2315_gpio_reg_read(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
+ AR2315_GPIO_DIR_I(bit))
+ return;
+
+ if (bit >= 0)
+ generic_handle_irq(ar2315_gpio_irq_base + bit);
+}
+
+static void ar2315_gpio_int_setup(unsigned gpio, int trig)
+{
+ u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_INT);
+
+ reg &= ~(AR2315_GPIO_INT_NUM_M | AR2315_GPIO_INT_TRIG_M);
+ reg |= gpio | AR2315_GPIO_INT_TRIG(trig);
+ ar2315_gpio_reg_write(AR2315_GPIO_INT, reg);
+}
+
+static void ar2315_gpio_irq_unmask(struct irq_data *d)
+{
+ unsigned gpio = d->irq - ar2315_gpio_irq_base;
+ u32 dir = ar2315_gpio_reg_read(AR2315_GPIO_DIR);
+
+ /* Enable interrupt with edge detection */
+ if ((dir & AR2315_GPIO_DIR_M(gpio)) != AR2315_GPIO_DIR_I(gpio))
+ return;
+
+ ar2315_gpio_intmask |= (1 << gpio);
+ ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_EDGE);
+}
+
+static void ar2315_gpio_irq_mask(struct irq_data *d)
+{
+ unsigned gpio = d->irq - ar2315_gpio_irq_base;
+
+ /* Disable interrupt */
+ ar2315_gpio_intmask &= ~(1 << gpio);
+ ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_OFF);
+}
+
+static struct irq_chip ar2315_gpio_irq_chip = {
+ .name = DRIVER_NAME,
+ .irq_unmask = ar2315_gpio_irq_unmask,
+ .irq_mask = ar2315_gpio_irq_mask,
+};
+
+static void ar2315_gpio_irq_init(unsigned irq)
+{
+ unsigned i;
+
+ ar2315_gpio_intval = ar2315_gpio_reg_read(AR2315_GPIO_DI);
+ for (i = 0; i < AR2315_GPIO_NUM; i++) {
+ unsigned _irq = ar2315_gpio_irq_base + i;
+
+ irq_set_chip_and_handler(_irq, &ar2315_gpio_irq_chip,
+ handle_level_irq);
+ }
+ irq_set_chained_handler(irq, ar2315_gpio_irq_handler);
+}
+
+static int ar2315_gpio_get_val(struct gpio_chip *chip, unsigned gpio)
+{
+ return (ar2315_gpio_reg_read(AR2315_GPIO_DI) >> gpio) & 1;
+}
+
+static void ar2315_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val)
+{
+ u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_DO);
+
+ reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio);
+ ar2315_gpio_reg_write(AR2315_GPIO_DO, reg);
+}
+
+static int ar2315_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
+{
+ ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 1 << gpio, 0);
+ return 0;
+}
+
+static int ar2315_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val)
+{
+ ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 0, 1 << gpio);
+ ar2315_gpio_set_val(chip, gpio, val);
+ return 0;
+}
+
+static int ar2315_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
+{
+ return ar2315_gpio_irq_base + gpio;
+}
+
+static struct gpio_chip ar2315_gpio_chip = {
+ .label = DRIVER_NAME,
+ .direction_input = ar2315_gpio_dir_in,
+ .direction_output = ar2315_gpio_dir_out,
+ .set = ar2315_gpio_set_val,
+ .get = ar2315_gpio_get_val,
+ .to_irq = ar2315_gpio_to_irq,
+ .base = 0,
+ .ngpio = AR2315_GPIO_NUM,
+};
+
+static int ar2315_gpio_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ unsigned irq;
+ int ret;
+
+ if (ar2315_mem)
+ return -EBUSY;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
+ "ar2315-gpio-irq-base");
+ if (!res) {
+ dev_err(dev, "not found GPIO IRQ base\n");
+ return -ENXIO;
+ }
+ ar2315_gpio_irq_base = res->start;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, DRIVER_NAME);
+ if (!res) {
+ dev_err(dev, "not found IRQ number\n");
+ return -ENXIO;
+ }
+ irq = res->start;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, DRIVER_NAME);
+ ar2315_mem = devm_ioremap_resource(dev, res);
+ if (IS_ERR(ar2315_mem))
+ return PTR_ERR(ar2315_mem);
+
+ ar2315_gpio_chip.parent = dev;
+ ret = gpiochip_add(&ar2315_gpio_chip);
+ if (ret) {
+ dev_err(dev, "failed to add gpiochip\n");
+ return ret;
+ }
+
+ ar2315_gpio_irq_init(irq);
+
+ return 0;
+}
+
+static struct platform_driver ar2315_gpio_driver = {
+ .probe = ar2315_gpio_probe,
+ .driver = {
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
+ }
+};
+
+static int __init ar2315_gpio_init(void)
+{
+ return platform_driver_register(&ar2315_gpio_driver);
+}
+subsys_initcall(ar2315_gpio_init);
--- a/arch/mips/ath25/devices.h
+++ b/arch/mips/ath25/devices.h
@@ -4,6 +4,11 @@
#include <linux/cpu.h>
+#define AR231X_GPIO_IRQ_BASE 0x30
+
+/* GPIO number for AR2315/16 reset issue workaround */
+#define AR2315_RESET_GPIO 5
+
#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
--- a/arch/mips/ath25/ar2315_regs.h
+++ b/arch/mips/ath25/ar2315_regs.h
@@ -315,6 +315,9 @@
#define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
#define AR2315_MEM_CFG_BANKADDR_BITS_S 3
+/* GPIO MMR base address */
+#define AR2315_GPIO 0x0088
+
/*
* Local Bus Interface Registers
*/

1734
target/linux/ath25/patches-4.14/110-ar2313_ethernet.patch Normal file
View File

File diff suppressed because it is too large Load Diff

634
target/linux/ath25/patches-4.14/120-spiflash.patch Normal file
View File

@@ -0,0 +1,634 @@
--- a/drivers/mtd/devices/Kconfig
+++ b/drivers/mtd/devices/Kconfig
@@ -130,6 +130,10 @@ config MTD_BCM47XXSFLASH
registered by bcma as platform devices. This enables driver for
serial flash memories.
+config MTD_AR2315
+ tristate "Atheros AR2315+ SPI Flash support"
+ depends on SOC_AR2315
+
config MTD_SLRAM
tristate "Uncached system RAM"
help
--- a/drivers/mtd/devices/Makefile
+++ b/drivers/mtd/devices/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_M25P80) += m25p80.o
obj-$(CONFIG_MTD_MCHP23K256) += mchp23k256.o
obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o
obj-$(CONFIG_MTD_SST25L) += sst25l.o
+obj-$(CONFIG_MTD_AR2315) += ar2315.o
obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o
obj-$(CONFIG_MTD_ST_SPI_FSM) += st_spi_fsm.o
obj-$(CONFIG_MTD_POWERNV_FLASH) += powernv_flash.o
--- /dev/null
+++ b/drivers/mtd/devices/ar2315.c
@@ -0,0 +1,459 @@
+
+/*
+ * MTD driver for the SPI Flash Memory support on Atheros AR2315
+ *
+ * Copyright (c) 2005-2006 Atheros Communications Inc.
+ * Copyright (C) 2006-2007 FON Technology, SL.
+ * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>
+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
+ *
+ * This code is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/mutex.h>
+
+#include "ar2315_spiflash.h"
+
+#define DRIVER_NAME "ar2315-spiflash"
+
+#define busy_wait(_priv, _condition, _wait) do { \
+ while (_condition) { \
+ if (_wait > 1) \
+ msleep(_wait); \
+ else if ((_wait == 1) && need_resched()) \
+ schedule(); \
+ else \
+ udelay(1); \
+ } \
+} while (0)
+
+enum {
+ FLASH_NONE,
+ FLASH_1MB,
+ FLASH_2MB,
+ FLASH_4MB,
+ FLASH_8MB,
+ FLASH_16MB,
+};
+
+/* Flash configuration table */
+struct flashconfig {
+ u32 byte_cnt;
+ u32 sector_cnt;
+ u32 sector_size;
+};
+
+static const struct flashconfig flashconfig_tbl[] = {
+ [FLASH_NONE] = { 0, 0, 0},
+ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT,
+ STM_1MB_SECTOR_SIZE},
+ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT,
+ STM_2MB_SECTOR_SIZE},
+ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT,
+ STM_4MB_SECTOR_SIZE},
+ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT,
+ STM_8MB_SECTOR_SIZE},
+ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT,
+ STM_16MB_SECTOR_SIZE}
+};
+
+/* Mapping of generic opcodes to STM serial flash opcodes */
+enum {
+ SPI_WRITE_ENABLE,
+ SPI_WRITE_DISABLE,
+ SPI_RD_STATUS,
+ SPI_WR_STATUS,
+ SPI_RD_DATA,
+ SPI_FAST_RD_DATA,
+ SPI_PAGE_PROGRAM,
+ SPI_SECTOR_ERASE,
+ SPI_BULK_ERASE,
+ SPI_DEEP_PWRDOWN,
+ SPI_RD_SIG,
+};
+
+struct opcodes {
+ __u16 code;
+ __s8 tx_cnt;
+ __s8 rx_cnt;
+};
+
+static const struct opcodes stm_opcodes[] = {
+ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
+ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
+ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
+ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
+ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
+ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
+ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
+ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
+ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
+ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
+ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
+};
+
+/* Driver private data structure */
+struct spiflash_priv {
+ struct mtd_info mtd;
+ void __iomem *readaddr; /* memory mapped data for read */
+ void __iomem *mmraddr; /* memory mapped register space */
+ struct mutex lock; /* serialize registers access */
+};
+
+#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
+
+enum {
+ FL_READY,
+ FL_READING,
+ FL_ERASING,
+ FL_WRITING
+};
+
+/*****************************************************************************/
+
+static u32
+spiflash_read_reg(struct spiflash_priv *priv, int reg)
+{
+ return ioread32(priv->mmraddr + reg);
+}
+
+static void
+spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
+{
+ iowrite32(data, priv->mmraddr + reg);
+}
+
+static u32
+spiflash_wait_busy(struct spiflash_priv *priv)
+{
+ u32 reg;
+
+ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
+ SPI_CTL_BUSY, 0);
+ return reg;
+}
+
+static u32
+spiflash_sendcmd(struct spiflash_priv *priv, int opcode, u32 addr)
+{
+ const struct opcodes *op;
+ u32 reg, mask;
+
+ op = &stm_opcodes[opcode];
+ reg = spiflash_wait_busy(priv);
+ spiflash_write_reg(priv, SPI_FLASH_OPCODE,
+ ((u32)op->code) | (addr << 8));
+
+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
+ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
+
+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
+ spiflash_wait_busy(priv);
+
+ if (!op->rx_cnt)
+ return 0;
+
+ reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
+
+ switch (op->rx_cnt) {
+ case 1:
+ mask = 0x000000ff;
+ break;
+ case 2:
+ mask = 0x0000ffff;
+ break;
+ case 3:
+ mask = 0x00ffffff;
+ break;
+ default:
+ mask = 0xffffffff;
+ break;
+ }
+ reg &= mask;
+
+ return reg;
+}
+
+/*
+ * Probe SPI flash device
+ * Function returns 0 for failure.
+ * and flashconfig_tbl array index for success.
+ */
+static int
+spiflash_probe_chip(struct platform_device *pdev, struct spiflash_priv *priv)
+{
+ u32 sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
+ int flash_size;
+
+ switch (sig) {
+ case STM_8MBIT_SIGNATURE:
+ flash_size = FLASH_1MB;
+ break;
+ case STM_16MBIT_SIGNATURE:
+ flash_size = FLASH_2MB;
+ break;
+ case STM_32MBIT_SIGNATURE:
+ flash_size = FLASH_4MB;
+ break;
+ case STM_64MBIT_SIGNATURE:
+ flash_size = FLASH_8MB;
+ break;
+ case STM_128MBIT_SIGNATURE:
+ flash_size = FLASH_16MB;
+ break;
+ default:
+ dev_warn(&pdev->dev, "read of flash device signature failed!\n");
+ return 0;
+ }
+
+ return flash_size;
+}
+
+static void
+spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
+{
+ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
+ SPI_STATUS_WIP, timeout);
+}
+
+static int
+spiflash_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ struct spiflash_priv *priv = to_spiflash(mtd);
+ const struct opcodes *op;
+ u32 temp, reg;
+
+ if (instr->addr + instr->len > mtd->size)
+ return -EINVAL;
+
+ mutex_lock(&priv->lock);
+
+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
+ reg = spiflash_wait_busy(priv);
+
+ op = &stm_opcodes[SPI_SECTOR_ERASE];
+ temp = ((u32)instr->addr << 8) | (u32)(op->code);
+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
+
+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
+ reg |= op->tx_cnt | SPI_CTL_START;
+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
+
+ spiflash_wait_complete(priv, 20);
+
+ mutex_unlock(&priv->lock);
+
+ instr->state = MTD_ERASE_DONE;
+ mtd_erase_callback(instr);
+
+ return 0;
+}
+
+static int
+spiflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+ u_char *buf)
+{
+ struct spiflash_priv *priv = to_spiflash(mtd);
+
+ if (!len)
+ return 0;
+
+ if (from + len > mtd->size)
+ return -EINVAL;
+
+ *retlen = len;
+
+ mutex_lock(&priv->lock);
+
+ memcpy_fromio(buf, priv->readaddr + from, len);
+
+ mutex_unlock(&priv->lock);
+
+ return 0;
+}
+
+static int
+spiflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+ const u8 *buf)
+{
+ struct spiflash_priv *priv = to_spiflash(mtd);
+ u32 opcode, bytes_left;
+
+ *retlen = 0;
+
+ if (!len)
+ return 0;
+
+ if (to + len > mtd->size)
+ return -EINVAL;
+
+ bytes_left = len;
+
+ do {
+ u32 read_len, reg, page_offset, spi_data = 0;
+
+ read_len = min(bytes_left, sizeof(u32));
+
+ /* 32-bit writes cannot span across a page boundary
+ * (256 bytes). This types of writes require two page
+ * program operations to handle it correctly. The STM part
+ * will write the overflow data to the beginning of the
+ * current page as opposed to the subsequent page.
+ */
+ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
+
+ if (page_offset > STM_PAGE_SIZE)
+ read_len -= (page_offset - STM_PAGE_SIZE);
+
+ mutex_lock(&priv->lock);
+
+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
+ spi_data = 0;
+ switch (read_len) {
+ case 4:
+ spi_data |= buf[3] << 24;
+ /* fall through */
+ case 3:
+ spi_data |= buf[2] << 16;
+ /* fall through */
+ case 2:
+ spi_data |= buf[1] << 8;
+ /* fall through */
+ case 1:
+ spi_data |= buf[0] & 0xff;
+ break;
+ default:
+ break;
+ }
+
+ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
+ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
+ (to & 0x00ffffff) << 8;
+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
+
+ reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
+ reg |= (read_len + 4) | SPI_CTL_START;
+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
+
+ spiflash_wait_complete(priv, 1);
+
+ mutex_unlock(&priv->lock);
+
+ bytes_left -= read_len;
+ to += read_len;
+ buf += read_len;
+
+ *retlen += read_len;
+ } while (bytes_left != 0);
+
+ return 0;
+}
+
+#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
+static const char * const part_probe_types[] = {
+ "cmdlinepart", "RedBoot", "MyLoader", NULL
+};
+#endif
+
+static int
+spiflash_probe(struct platform_device *pdev)
+{
+ struct spiflash_priv *priv;
+ struct mtd_info *mtd;
+ struct resource *res;
+ int index;
+ int result = 0;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ mutex_init(&priv->lock);
+ mtd = &priv->mtd;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ priv->mmraddr = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(priv->mmraddr)) {
+ dev_warn(&pdev->dev, "failed to map flash MMR\n");
+ return PTR_ERR(priv->mmraddr);
+ }
+
+ index = spiflash_probe_chip(pdev, priv);
+ if (!index) {
+ dev_warn(&pdev->dev, "found no flash device\n");
+ return -ENODEV;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->readaddr = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(priv->readaddr)) {
+ dev_warn(&pdev->dev, "failed to map flash read mem\n");
+ return PTR_ERR(priv->readaddr);
+ }
+
+ platform_set_drvdata(pdev, priv);
+ mtd->name = "spiflash";
+ mtd->type = MTD_NORFLASH;
+ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
+ mtd->size = flashconfig_tbl[index].byte_cnt;
+ mtd->erasesize = flashconfig_tbl[index].sector_size;
+ mtd->writesize = 1;
+ mtd->numeraseregions = 0;
+ mtd->eraseregions = NULL;
+ mtd->_erase = spiflash_erase;
+ mtd->_read = spiflash_read;
+ mtd->_write = spiflash_write;
+ mtd->owner = THIS_MODULE;
+
+ dev_info(&pdev->dev, "%lld Kbytes flash detected\n", mtd->size >> 10);
+
+#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
+ /* parse redboot partitions */
+
+ result = mtd_device_parse_register(mtd, part_probe_types,
+ NULL, NULL, 0);
+#endif
+
+ return result;
+}
+
+static int
+spiflash_remove(struct platform_device *pdev)
+{
+ struct spiflash_priv *priv = platform_get_drvdata(pdev);
+
+ mtd_device_unregister(&priv->mtd);
+
+ return 0;
+}
+
+static struct platform_driver spiflash_driver = {
+ .driver.name = DRIVER_NAME,
+ .probe = spiflash_probe,
+ .remove = spiflash_remove,
+};
+
+module_platform_driver(spiflash_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("OpenWrt.org");
+MODULE_AUTHOR("Atheros Communications Inc");
+MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros AR2315+ SOC");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+
--- /dev/null
+++ b/drivers/mtd/devices/ar2315_spiflash.h
@@ -0,0 +1,106 @@
+/*
+ * Atheros AR2315 SPI Flash Memory support header file.
+ *
+ * Copyright (c) 2005, Atheros Communications Inc.
+ * Copyright (C) 2006 FON Technology, SL.
+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>
+ *
+ * This code is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __AR2315_SPIFLASH_H
+#define __AR2315_SPIFLASH_H
+
+#define STM_PAGE_SIZE 256
+
+#define SFI_WRITE_BUFFER_SIZE 4
+#define SFI_FLASH_ADDR_MASK 0x00ffffff
+
+#define STM_8MBIT_SIGNATURE 0x13
+#define STM_M25P80_BYTE_COUNT 1048576
+#define STM_M25P80_SECTOR_COUNT 16
+#define STM_M25P80_SECTOR_SIZE 0x10000
+
+#define STM_16MBIT_SIGNATURE 0x14
+#define STM_M25P16_BYTE_COUNT 2097152
+#define STM_M25P16_SECTOR_COUNT 32
+#define STM_M25P16_SECTOR_SIZE 0x10000
+
+#define STM_32MBIT_SIGNATURE 0x15
+#define STM_M25P32_BYTE_COUNT 4194304
+#define STM_M25P32_SECTOR_COUNT 64
+#define STM_M25P32_SECTOR_SIZE 0x10000
+
+#define STM_64MBIT_SIGNATURE 0x16
+#define STM_M25P64_BYTE_COUNT 8388608
+#define STM_M25P64_SECTOR_COUNT 128
+#define STM_M25P64_SECTOR_SIZE 0x10000
+
+#define STM_128MBIT_SIGNATURE 0x17
+#define STM_M25P128_BYTE_COUNT 16777216
+#define STM_M25P128_SECTOR_COUNT 256
+#define STM_M25P128_SECTOR_SIZE 0x10000
+
+#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT
+#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
+#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE
+#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT
+#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
+#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE
+#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT
+#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
+#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE
+#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT
+#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
+#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE
+#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT
+#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
+#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE
+
+/*
+ * ST Microelectronics Opcodes for Serial Flash
+ */
+
+#define STM_OP_WR_ENABLE 0x06 /* Write Enable */
+#define STM_OP_WR_DISABLE 0x04 /* Write Disable */
+#define STM_OP_RD_STATUS 0x05 /* Read Status */
+#define STM_OP_WR_STATUS 0x01 /* Write Status */
+#define STM_OP_RD_DATA 0x03 /* Read Data */
+#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */
+#define STM_OP_PAGE_PGRM 0x02 /* Page Program */
+#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */
+#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */
+#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */
+#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */
+
+#define STM_STATUS_WIP 0x01 /* Write-In-Progress */
+#define STM_STATUS_WEL 0x02 /* Write Enable Latch */
+#define STM_STATUS_BP0 0x04 /* Block Protect 0 */
+#define STM_STATUS_BP1 0x08 /* Block Protect 1 */
+#define STM_STATUS_BP2 0x10 /* Block Protect 2 */
+#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */
+
+/*
+ * SPI Flash Interface Registers
+ */
+
+#define SPI_FLASH_CTL 0x00
+#define SPI_FLASH_OPCODE 0x04
+#define SPI_FLASH_DATA 0x08
+
+#define SPI_CTL_START 0x00000100
+#define SPI_CTL_BUSY 0x00010000
+#define SPI_CTL_TXCNT_MASK 0x0000000f
+#define SPI_CTL_RXCNT_MASK 0x000000f0
+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
+#define SPI_CTL_SIZE_MASK 0x00060000
+
+#define SPI_CTL_CLK_SEL_MASK 0x03000000
+#define SPI_OPCODE_MASK 0x000000ff
+
+#define SPI_STATUS_WIP STM_STATUS_WIP
+
+#endif
--- a/arch/mips/ath25/ar2315.c
+++ b/arch/mips/ath25/ar2315.c
@@ -220,6 +220,28 @@ static struct platform_device ar2315_gpi
.num_resources = ARRAY_SIZE(ar2315_gpio_res)
};
+static struct resource ar2315_spiflash_res[] = {
+ {
+ .name = "spiflash_read",
+ .flags = IORESOURCE_MEM,
+ .start = AR2315_SPI_READ_BASE,
+ .end = AR2315_SPI_READ_BASE + AR2315_SPI_READ_SIZE - 1,
+ },
+ {
+ .name = "spiflash_mmr",
+ .flags = IORESOURCE_MEM,
+ .start = AR2315_SPI_MMR_BASE,
+ .end = AR2315_SPI_MMR_BASE + AR2315_SPI_MMR_SIZE - 1,
+ },
+};
+
+static struct platform_device ar2315_spiflash = {
+ .id = 0,
+ .name = "ar2315-spiflash",
+ .resource = ar2315_spiflash_res,
+ .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
+};
+
void __init ar2315_init_devices(void)
{
/* Find board configuration */
@@ -230,6 +252,8 @@ void __init ar2315_init_devices(void)
ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
platform_device_register(&ar2315_gpio);
+ platform_device_register(&ar2315_spiflash);
+
ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii",
AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,

277
target/linux/ath25/patches-4.14/130-watchdog.patch Normal file
View File

@@ -0,0 +1,277 @@
--- /dev/null
+++ b/drivers/watchdog/ar2315-wtd.c
@@ -0,0 +1,209 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
+ * Based on EP93xx and ifxmips wdt driver
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/types.h>
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+#include <linux/fs.h>
+#include <linux/ioport.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/uaccess.h>
+
+#define DRIVER_NAME "ar2315-wdt"
+
+#define CLOCK_RATE 40000000
+#define HEARTBEAT(x) (x < 1 || x > 90 ? 20 : x)
+
+#define WDT_REG_TIMER 0x00
+#define WDT_REG_CTRL 0x04
+
+#define WDT_CTRL_ACT_NONE 0x00000000 /* No action */
+#define WDT_CTRL_ACT_NMI 0x00000001 /* NMI on watchdog */
+#define WDT_CTRL_ACT_RESET 0x00000002 /* reset on watchdog */
+
+static int wdt_timeout = 20;
+static int started;
+static int in_use;
+static void __iomem *wdt_base;
+
+static inline void ar2315_wdt_wr(unsigned reg, u32 val)
+{
+ iowrite32(val, wdt_base + reg);
+}
+
+static void
+ar2315_wdt_enable(void)
+{
+ ar2315_wdt_wr(WDT_REG_TIMER, wdt_timeout * CLOCK_RATE);
+}
+
+static ssize_t
+ar2315_wdt_write(struct file *file, const char __user *data, size_t len,
+ loff_t *ppos)
+{
+ if (len)
+ ar2315_wdt_enable();
+ return len;
+}
+
+static int
+ar2315_wdt_open(struct inode *inode, struct file *file)
+{
+ if (in_use)
+ return -EBUSY;
+ ar2315_wdt_enable();
+ in_use = 1;
+ started = 1;
+ return nonseekable_open(inode, file);
+}
+
+static int
+ar2315_wdt_release(struct inode *inode, struct file *file)
+{
+ in_use = 0;
+ return 0;
+}
+
+static irqreturn_t
+ar2315_wdt_interrupt(int irq, void *dev)
+{
+ struct platform_device *pdev = (struct platform_device *)dev;
+
+ if (started) {
+ dev_crit(&pdev->dev, "watchdog expired, rebooting system\n");
+ emergency_restart();
+ } else {
+ ar2315_wdt_wr(WDT_REG_CTRL, 0);
+ ar2315_wdt_wr(WDT_REG_TIMER, 0);
+ }
+ return IRQ_HANDLED;
+}
+
+static struct watchdog_info ident = {
+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
+ .identity = "ar2315 Watchdog",
+};
+
+static long
+ar2315_wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+ int new_wdt_timeout;
+ int ret = -ENOIOCTLCMD;
+
+ switch (cmd) {
+ case WDIOC_GETSUPPORT:
+ ret = copy_to_user((void __user *)arg, &ident, sizeof(ident)) ?
+ -EFAULT : 0;
+ break;
+ case WDIOC_KEEPALIVE:
+ ar2315_wdt_enable();
+ ret = 0;
+ break;
+ case WDIOC_SETTIMEOUT:
+ ret = get_user(new_wdt_timeout, (int __user *)arg);
+ if (ret)
+ break;
+ wdt_timeout = HEARTBEAT(new_wdt_timeout);
+ ar2315_wdt_enable();
+ break;
+ case WDIOC_GETTIMEOUT:
+ ret = put_user(wdt_timeout, (int __user *)arg);
+ break;
+ }
+ return ret;
+}
+
+static const struct file_operations ar2315_wdt_fops = {
+ .owner = THIS_MODULE,
+ .llseek = no_llseek,
+ .write = ar2315_wdt_write,
+ .unlocked_ioctl = ar2315_wdt_ioctl,
+ .open = ar2315_wdt_open,
+ .release = ar2315_wdt_release,
+};
+
+static struct miscdevice ar2315_wdt_miscdev = {
+ .minor = WATCHDOG_MINOR,
+ .name = "watchdog",
+ .fops = &ar2315_wdt_fops,
+};
+
+static int
+ar2315_wdt_probe(struct platform_device *dev)
+{
+ struct resource *mem_res, *irq_res;
+ int ret = 0;
+
+ if (wdt_base)
+ return -EBUSY;
+
+ irq_res = platform_get_resource(dev, IORESOURCE_IRQ, 0);
+ if (!irq_res) {
+ dev_err(&dev->dev, "no IRQ resource\n");
+ return -ENOENT;
+ }
+
+ mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
+ wdt_base = devm_ioremap_resource(&dev->dev, mem_res);
+ if (IS_ERR(wdt_base))
+ return PTR_ERR(wdt_base);
+
+ ret = devm_request_irq(&dev->dev, irq_res->start, ar2315_wdt_interrupt,
+ 0, DRIVER_NAME, dev);
+ if (ret) {
+ dev_err(&dev->dev, "failed to register inetrrupt\n");
+ goto out;
+ }
+
+ ret = misc_register(&ar2315_wdt_miscdev);
+ if (ret)
+ dev_err(&dev->dev, "failed to register miscdev\n");
+
+out:
+ return ret;
+}
+
+static int
+ar2315_wdt_remove(struct platform_device *dev)
+{
+ misc_deregister(&ar2315_wdt_miscdev);
+ return 0;
+}
+
+static struct platform_driver ar2315_wdt_driver = {
+ .probe = ar2315_wdt_probe,
+ .remove = ar2315_wdt_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+module_platform_driver(ar2315_wdt_driver);
+
+MODULE_DESCRIPTION("Atheros AR2315 hardware watchdog driver");
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -1646,6 +1646,13 @@ config PIC32_DMT
To compile this driver as a loadable module, choose M here.
The module will be called pic32-dmt.
+config AR2315_WDT
+ tristate "Atheros AR2315+ WiSoCs Watchdog Timer"
+ depends on ATH25
+ help
+ Hardware driver for the built-in watchdog timer on the Atheros
+ AR2315/AR2316 WiSoCs.
+
# PARISC Architecture
# POWERPC Architecture
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -166,6 +166,7 @@ obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o
obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
+obj-$(CONFIG_AR2315_WDT) += ar2315-wtd.o
obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
--- a/arch/mips/ath25/ar2315.c
+++ b/arch/mips/ath25/ar2315.c
@@ -220,6 +220,24 @@ static struct platform_device ar2315_gpi
.num_resources = ARRAY_SIZE(ar2315_gpio_res)
};
+static struct resource ar2315_wdt_res[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = AR2315_RST_BASE + AR2315_WDT_TIMER,
+ .end = AR2315_RST_BASE + AR2315_WDT_TIMER + 8 - 1,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct platform_device ar2315_wdt = {
+ .id = 0,
+ .name = "ar2315-wdt",
+ .resource = ar2315_wdt_res,
+ .num_resources = ARRAY_SIZE(ar2315_wdt_res)
+};
+
static struct resource ar2315_spiflash_res[] = {
{
.name = "spiflash_read",
@@ -252,6 +270,11 @@ void __init ar2315_init_devices(void)
ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
platform_device_register(&ar2315_gpio);
+ ar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
+ AR2315_MISC_IRQ_WATCHDOG);
+ ar2315_wdt_res[1].end = ar2315_wdt_res[1].start;
+ platform_device_register(&ar2315_wdt);
+
platform_device_register(&ar2315_spiflash);
ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;

60
target/linux/ath25/patches-4.14/140-redboot_boardconfig.patch Normal file
View File

@@ -0,0 +1,60 @@
--- a/drivers/mtd/redboot.c
+++ b/drivers/mtd/redboot.c
@@ -30,6 +30,8 @@
#include <linux/mtd/partitions.h>
#include <linux/module.h>
+#define BOARD_CONFIG_PART "boardconfig"
+
struct fis_image_desc {
unsigned char name[16]; // Null terminated name
uint32_t flash_base; // Address within FLASH of image
@@ -60,6 +62,7 @@ static int parse_redboot_partitions(stru
const struct mtd_partition **pparts,
struct mtd_part_parser_data *data)
{
+ unsigned long max_offset = 0;
int nrparts = 0;
struct fis_image_desc *buf;
struct mtd_partition *parts;
@@ -225,14 +228,15 @@ static int parse_redboot_partitions(stru
}
}
#endif
- parts = kzalloc(sizeof(*parts)*nrparts + nulllen + namelen, GFP_KERNEL);
+ parts = kzalloc(sizeof(*parts) * (nrparts + 1) + nulllen + namelen +
+ sizeof(BOARD_CONFIG_PART), GFP_KERNEL);
if (!parts) {
ret = -ENOMEM;
goto out;
}
- nullname = (char *)&parts[nrparts];
+ nullname = (char *)&parts[nrparts + 1];
#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
if (nulllen > 0) {
strcpy(nullname, nullstring);
@@ -251,6 +255,8 @@ static int parse_redboot_partitions(stru
}
#endif
for ( ; i<nrparts; i++) {
+ if (max_offset < buf[i].flash_base + buf[i].size)
+ max_offset = buf[i].flash_base + buf[i].size;
parts[i].size = fl->img->size;
parts[i].offset = fl->img->flash_base;
parts[i].name = names;
@@ -284,6 +290,13 @@ static int parse_redboot_partitions(stru
fl = fl->next;
kfree(tmp_fl);
}
+ if (master->size - max_offset >= master->erasesize) {
+ parts[nrparts].size = master->size - max_offset;
+ parts[nrparts].offset = max_offset;
+ parts[nrparts].name = names;
+ strcpy(names, BOARD_CONFIG_PART);
+ nrparts++;
+ }
ret = nrparts;
*pparts = parts;
out:

44
target/linux/ath25/patches-4.14/141-redboot_partition_scan.patch Normal file
View File

@@ -0,0 +1,44 @@
--- a/drivers/mtd/redboot.c
+++ b/drivers/mtd/redboot.c
@@ -79,12 +79,18 @@ static int parse_redboot_partitions(stru
static char nullstring[] = "unallocated";
#endif
+ buf = vmalloc(master->erasesize);
+ if (!buf)
+ return -ENOMEM;
+
+ restart:
if ( directory < 0 ) {
offset = master->size + directory * master->erasesize;
while (mtd_block_isbad(master, offset)) {
if (!offset) {
nogood:
printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
+ vfree(buf);
return -EIO;
}
offset -= master->erasesize;
@@ -97,10 +103,6 @@ static int parse_redboot_partitions(stru
goto nogood;
}
}
- buf = vmalloc(master->erasesize);
-
- if (!buf)
- return -ENOMEM;
printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
master->name, offset);
@@ -173,6 +175,11 @@ static int parse_redboot_partitions(stru
}
if (i == numslots) {
/* Didn't find it */
+ if (offset + master->erasesize < master->size) {
+ /* not at the end of the flash yet, maybe next block */
+ directory++;
+ goto restart;
+ }
printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
master->name);
ret = 0;

72
target/linux/ath25/patches-4.14/142-redboot_various_erase_size_fix.patch Normal file
View File

@@ -0,0 +1,72 @@
--- a/drivers/mtd/redboot.c
+++ b/drivers/mtd/redboot.c
@@ -58,6 +58,22 @@ static inline int redboot_checksum(struc
return 1;
}
+static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset)
+{
+ struct mtd_erase_region_info *regions = mtd->eraseregions;
+ int i;
+
+ for (i = 0; i < mtd->numeraseregions; i++) {
+ if (regions[i].offset +
+ regions[i].numblocks * regions[i].erasesize <= offset)
+ continue;
+
+ return regions[i].erasesize;
+ }
+
+ return mtd->erasesize;
+}
+
static int parse_redboot_partitions(struct mtd_info *master,
const struct mtd_partition **pparts,
struct mtd_part_parser_data *data)
@@ -74,6 +90,7 @@ static int parse_redboot_partitions(stru
int namelen = 0;
int nulllen = 0;
int numslots;
+ int first_slot;
unsigned long offset;
#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
static char nullstring[] = "unallocated";
@@ -186,7 +203,10 @@ static int parse_redboot_partitions(stru
goto out;
}
- for (i = 0; i < numslots; i++) {
+ first_slot = (buf[i].flash_base & (master->erasesize - 1)) /
+ sizeof(struct fis_image_desc);
+
+ for (i = first_slot; i < first_slot + numslots; i++) {
struct fis_list *new_fl, **prev;
if (buf[i].name[0] == 0xff) {
@@ -262,12 +282,13 @@ static int parse_redboot_partitions(stru
}
#endif
for ( ; i<nrparts; i++) {
- if (max_offset < buf[i].flash_base + buf[i].size)
- max_offset = buf[i].flash_base + buf[i].size;
parts[i].size = fl->img->size;
parts[i].offset = fl->img->flash_base;
parts[i].name = names;
+ if (max_offset < parts[i].offset + parts[i].size)
+ max_offset = parts[i].offset + parts[i].size;
+
strcpy(names, fl->img->name);
#ifdef CONFIG_MTD_REDBOOT_PARTS_READONLY
if (!memcmp(names, "RedBoot", 8) ||
@@ -297,7 +318,9 @@ static int parse_redboot_partitions(stru
fl = fl->next;
kfree(tmp_fl);
}
- if (master->size - max_offset >= master->erasesize) {
+
+ if (master->size - max_offset >=
+ mtd_get_offset_erasesize(master, max_offset)) {
parts[nrparts].size = master->size - max_offset;
parts[nrparts].offset = max_offset;
parts[nrparts].name = names;

71
target/linux/ath25/patches-4.14/210-reset_button.patch Normal file
View File

@@ -0,0 +1,71 @@
--- a/arch/mips/ath25/Makefile
+++ b/arch/mips/ath25/Makefile
@@ -8,7 +8,7 @@
# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
#
-obj-y += board.o prom.o devices.o
+obj-y += board.o prom.o devices.o reset.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
--- /dev/null
+++ b/arch/mips/ath25/reset.c
@@ -0,0 +1,57 @@
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <ath25_platform.h>
+#include "devices.h"
+
+static int __init
+ar231x_init_reset(void)
+{
+ struct platform_device *pdev;
+ struct gpio_keys_platform_data pdata;
+ struct gpio_keys_button *p;
+ int err;
+
+ if (ath25_board.config->reset_config_gpio == 0xffff)
+ return -ENODEV;
+
+ p = kzalloc(sizeof(*p), GFP_KERNEL);
+ if (!p)
+ goto err;
+
+ p->desc = "reset";
+ p->type = EV_KEY;
+ p->code = KEY_RESTART;
+ p->debounce_interval = 60;
+ p->gpio = ath25_board.config->reset_config_gpio;
+
+ memset(&pdata, 0, sizeof(pdata));
+ pdata.poll_interval = 20;
+ pdata.buttons = p;
+ pdata.nbuttons = 1;
+
+ pdev = platform_device_alloc("gpio-keys-polled", 0);
+ if (!pdev)
+ goto err_free;
+
+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+ if (err)
+ goto err_put_pdev;
+
+ err = platform_device_add(pdev);
+ if (err)
+ goto err_put_pdev;
+
+ return 0;
+
+err_put_pdev:
+ platform_device_put(pdev);
+err_free:
+ kfree(p);
+err:
+ return -ENOMEM;
+}
+
+device_initcall(ar231x_init_reset);

111
target/linux/ath25/patches-4.14/220-enet_micrel_workaround.patch Normal file
View File

@@ -0,0 +1,111 @@
--- a/drivers/net/ethernet/atheros/ar231x/ar231x.c
+++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c
@@ -135,6 +135,7 @@ static int ar231x_mdiobus_write(struct m
static int ar231x_mdiobus_reset(struct mii_bus *bus);
static int ar231x_mdiobus_probe(struct net_device *dev);
static void ar231x_adjust_link(struct net_device *dev);
+static bool no_phy;
#ifndef ERR
#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
@@ -167,6 +168,32 @@ static const struct net_device_ops ar231
#endif
};
+static int get_phy_id(struct mii_bus *bus, int addr, u32 *phy_id)
+{
+ int phy_reg;
+
+ /**
+ * Grab the bits from PHYIR1, and put them
+ * in the upper half.
+ */
+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID1);
+
+ if (phy_reg < 0)
+ return -EIO;
+
+ *phy_id = (phy_reg & 0xffff) << 16;
+
+ /* Grab the bits from PHYIR2, and put them in the lower half */
+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID2);
+
+ if (phy_reg < 0)
+ return -EIO;
+
+ *phy_id |= (phy_reg & 0xffff);
+
+ return 0;
+}
+
static int ar231x_probe(struct platform_device *pdev)
{
struct net_device *dev;
@@ -273,6 +300,24 @@ static int ar231x_probe(struct platform_
mdiobus_register(sp->mii_bus);
+ /**
+ * Workaround for Micrel switch, which is only available on
+ * one PHY and cannot be configured through MDIO.
+ */
+ if (!no_phy) {
+ u32 phy_id = 0;
+
+ get_phy_id(sp->mii_bus, 1, &phy_id);
+ if (phy_id == 0x00221450)
+ no_phy = true;
+ }
+ if (no_phy) {
+ sp->link = 1;
+ netif_carrier_on(dev);
+ return 0;
+ }
+ no_phy = true;
+
if (ar231x_mdiobus_probe(dev) != 0) {
printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
rx_tasklet_cleanup(dev);
@@ -326,8 +371,10 @@ static int ar231x_remove(struct platform
rx_tasklet_cleanup(dev);
ar231x_init_cleanup(dev);
unregister_netdev(dev);
- mdiobus_unregister(sp->mii_bus);
- mdiobus_free(sp->mii_bus);
+ if (sp->mii_bus) {
+ mdiobus_unregister(sp->mii_bus);
+ mdiobus_free(sp->mii_bus);
+ }
kfree(dev);
return 0;
}
@@ -870,7 +917,8 @@ static int ar231x_open(struct net_device
sp->eth_regs->mac_control |= MAC_CONTROL_RE;
- phy_start(sp->phy_dev);
+ if (sp->phy_dev)
+ phy_start(sp->phy_dev);
return 0;
}
@@ -951,7 +999,8 @@ static int ar231x_close(struct net_devic
#endif
- phy_stop(sp->phy_dev);
+ if (sp->phy_dev)
+ phy_stop(sp->phy_dev);
return 0;
}
@@ -995,6 +1044,9 @@ static int ar231x_ioctl(struct net_devic
{
struct ar231x_private *sp = netdev_priv(dev);
+ if (!sp->phy_dev)
+ return -ENODEV;
+
switch (cmd) {
case SIOCGMIIPHY:
case SIOCGMIIREG:

116
target/linux/ath25/patches-4.14/330-board_leds.patch Normal file
View File

@@ -0,0 +1,116 @@
--- a/arch/mips/ath25/ar2315.c
+++ b/arch/mips/ath25/ar2315.c
@@ -23,6 +23,7 @@
#include <linux/reboot.h>
#include <linux/delay.h>
#include <linux/gpio.h>
+#include <linux/leds.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/time.h>
@@ -260,6 +261,50 @@ static struct platform_device ar2315_spi
.num_resources = ARRAY_SIZE(ar2315_spiflash_res)
};
+#ifdef CONFIG_LEDS_GPIO
+static struct gpio_led ar2315_leds[6];
+static struct gpio_led_platform_data ar2315_led_data = {
+ .leds = (void *)ar2315_leds,
+};
+
+static struct platform_device ar2315_gpio_leds = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = (void *)&ar2315_led_data,
+ }
+};
+
+static void __init ar2315_init_gpio_leds(void)
+{
+ static char led_names[6][6];
+ int i, led = 0;
+
+ ar2315_led_data.num_leds = 0;
+ for (i = 1; i < 8; i++) {
+ if ((i == AR2315_RESET_GPIO) ||
+ (i == ath25_board.config->reset_config_gpio))
+ continue;
+
+ if (i == ath25_board.config->sys_led_gpio)
+ strcpy(led_names[led], "wlan");
+ else
+ sprintf(led_names[led], "gpio%d", i);
+
+ ar2315_leds[led].name = led_names[led];
+ ar2315_leds[led].gpio = i;
+ ar2315_leds[led].active_low = 0;
+ led++;
+ }
+ ar2315_led_data.num_leds = led;
+ platform_device_register(&ar2315_gpio_leds);
+}
+#else
+static inline void ar2315_init_gpio_leds(void)
+{
+}
+#endif
+
void __init ar2315_init_devices(void)
{
/* Find board configuration */
@@ -270,6 +315,8 @@ void __init ar2315_init_devices(void)
ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
platform_device_register(&ar2315_gpio);
+ ar2315_init_gpio_leds();
+
ar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
AR2315_MISC_IRQ_WATCHDOG);
ar2315_wdt_res[1].end = ar2315_wdt_res[1].start;
--- a/arch/mips/ath25/ar5312.c
+++ b/arch/mips/ath25/ar5312.c
@@ -23,6 +23,7 @@
#include <linux/mtd/physmap.h>
#include <linux/reboot.h>
#include <linux/gpio.h>
+#include <linux/leds.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/time.h>
@@ -231,6 +232,23 @@ static struct platform_device ar5312_gpi
.num_resources = ARRAY_SIZE(ar5312_gpio_res),
};
+#ifdef CONFIG_LEDS_GPIO
+static struct gpio_led ar5312_leds[] = {
+ { .name = "wlan", .gpio = 0, .active_low = 1, },
+};
+
+static const struct gpio_led_platform_data ar5312_led_data = {
+ .num_leds = ARRAY_SIZE(ar5312_leds),
+ .leds = (void *)ar5312_leds,
+};
+
+static struct platform_device ar5312_gpio_leds = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev.platform_data = (void *)&ar5312_led_data,
+};
+#endif
+
static void __init ar5312_flash_init(void)
{
void __iomem *flashctl_base;
@@ -301,6 +319,11 @@ void __init ar5312_init_devices(void)
platform_device_register(&ar5312_gpio);
+#ifdef CONFIG_LEDS_GPIO
+ ar5312_leds[0].gpio = config->sys_led_gpio;
+ platform_device_register(&ar5312_gpio_leds);
+#endif
+
/* Fix up MAC addresses if necessary */
if (is_broadcast_ether_addr(config->enet0_mac))
ether_addr_copy(config->enet0_mac, config->enet1_mac);