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lots of ifxmips fixes and features

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SVN-Revision: 11673
This commit is contained in:
John Crispin
2008-07-05 23:06:07 +00:00
parent 7866f69cbe
commit 3e2c38b0fb
18 changed files with 165 additions and 2592 deletions
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42
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
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@@ -15,7 +15,6 @@
*
* Copyright (C) 2005 infineon
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _IFXMIPS_H__
#define _IFXMIPS_H__
@@ -71,8 +70,41 @@
#define ASCOPT_STOPB 0x8
#define ASCOPT_PARODD 0x0
#define ASCOPT_CREAD 0x20
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
#define TXFIFO_FL 1
#define RXFIFO_FL 1
#define TXFIFO_FULL 16
#define ASCCLC_RMCMASK 0x0000FF00
#define ASCCLC_RMCOFFSET 8
#define ASCCON_M_8ASYNC 0x0
#define ASCCON_M_7ASYNC 0x2
#define ASCCON_ODD 0x00000020
#define ASCCON_STP 0x00000080
#define ASCCON_BRS 0x00000100
#define ASCCON_FDE 0x00000200
#define ASCCON_R 0x00008000
#define ASCCON_FEN 0x00020000
#define ASCCON_ROEN 0x00080000
#define ASCCON_TOEN 0x00100000
#define ASCSTATE_PE 0x00010000
#define ASCSTATE_FE 0x00020000
#define ASCSTATE_ROE 0x00080000
#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
#define ASCWHBSTATE_CLRREN 0x00000001
#define ASCWHBSTATE_SETREN 0x00000002
#define ASCWHBSTATE_CLRPE 0x00000004
#define ASCWHBSTATE_CLRFE 0x00000008
#define ASCWHBSTATE_CLRROE 0x00000020
#define ASCTXFCON_TXFEN 0x0001
#define ASCTXFCON_TXFFLU 0x0002
#define ASCTXFCON_TXFITLMASK 0x3F00
#define ASCTXFCON_TXFITLOFF 8
#define ASCRXFCON_RXFEN 0x0001
#define ASCRXFCON_RXFFLU 0x0002
#define ASCRXFCON_RXFITLMASK 0x3F00
#define ASCRXFCON_RXFITLOFF 8
#define ASCFSTAT_RXFFLMASK 0x003F
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
@@ -334,7 +366,7 @@
#define IFXMIPS_SSC_IRN ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
#define IFXMIPS_SSC_SFCON ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
#define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
#define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
#define IFXMIPS_SSC_STATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
#define IFXMIPS_SSC_WHBSTATE ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
#define IFXMIPS_SSC_FSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
#define IFXMIPS_SSC_ID ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
@@ -472,7 +504,7 @@
#define IFXMIPS_MPS_AD0ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
#define IFXMIPS_MPS_AD1ENR ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12)

36
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_cgu.h
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@@ -1,15 +1,29 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/
#ifndef _IFXMIPS_CGU_H__
#define _IFXMIPS_CGU_H__
u32 cgu_get_mips_clock(int cpu);
u32 cgu_get_cpu_clock(void);
u32 cgu_get_io_region_clock(void);
u32 cgu_get_fpi_bus_clock(int fpi);
u32 cgu_get_pp32_clock(void);
u32 cgu_get_ethernet_clock(int mii);
u32 cgu_get_usb_clock(void);
u32 cgu_get_clockout(int clkout);
unsigned int cgu_get_mips_clock(int cpu);
unsigned int cgu_get_io_region_clock(void);
unsigned int cgu_get_fpi_bus_clock(int fpi);
void cgu_setup_pci_clk(int internal_clock);
u32 ifxmips_get_ddr_hz(void);
u32 ifxmips_get_cpu_hz(void);
u32 ifxmips_get_fpi_hz(void);
unsigned int ifxmips_get_ddr_hz(void);
unsigned int ifxmips_get_fpi_hz(void);
unsigned int ifxmips_get_cpu_hz(void);
#endif

2
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_gpio.h
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@@ -12,9 +12,7 @@
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _IFXMIPS_GPIO_H__
#define _IFXMIPS_GPIO_H__

42
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_ioctl.h
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@@ -1,42 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _IFXMIPS_IOCTL_H__
#define _IFXMIPS_IOCTL_H__
/*------------ LED */
struct ifxmips_port_ioctl_parm
{
int port;
int pin;
int value;
};
#define IFXMIPS_PORT_IOC_MAGIC 0xbf
#define IFXMIPS_PORT_IOCOD _IOW(IFXMIPS_PORT_IOC_MAGIC,0,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCPUDSEL _IOW(IFXMIPS_PORT_IOC_MAGIC,1,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCPUDEN _IOW(IFXMIPS_PORT_IOC_MAGIC,2,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCSTOFF _IOW(IFXMIPS_PORT_IOC_MAGIC,3,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCDIR _IOW(IFXMIPS_PORT_IOC_MAGIC,4,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCOUTPUT _IOW(IFXMIPS_PORT_IOC_MAGIC,5,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCINPUT _IOWR(IFXMIPS_PORT_IOC_MAGIC,6,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCALTSEL0 _IOW(IFXMIPS_PORT_IOC_MAGIC,7,struct ifxmips_port_ioctl_parm)
#define IFXMIPS_PORT_IOCALTSEL1 _IOW(IFXMIPS_PORT_IOC_MAGIC,8,struct ifxmips_port_ioctl_parm)
#endif

1
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_irq.h
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@@ -15,7 +15,6 @@
*
* Copyright (C) 2005 infineon
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _IFXMIPS_IRQ__
#define _IFXMIPS_IRQ__

4
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_led.h
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@@ -15,8 +15,12 @@
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/
#ifndef _IFXMIPS_LED_H__
#define _IFXMIPS_LED_H__
extern void ifxmips_led_set(unsigned int led);
extern void ifxmips_led_clear(unsigned int led);
extern void ifxmips_led_blink_set(unsigned int led);
extern void ifxmips_led_blink_clear(unsigned int led);
#endif

34
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_mii0.h
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@@ -1,34 +0,0 @@
#ifndef IFXMIPS_MII0_H
#define IFXMIPS_MII0_H
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*/
#include <linux/netdevice.h>
struct ifxmips_mii_priv {
struct net_device_stats stats;
struct dma_device_info *dma_device;
struct sk_buff *skb;
};
struct ifxmips_mac {
unsigned char mac[6];
};
#endif

2021
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_orig.h
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File diff suppressed because it is too large Load Diff

1
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_pmu.h
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@@ -14,7 +14,6 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _IFXMIPS_PMU_H__
#define _IFXMIPS_PMU_H__

3
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_prom.h
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@@ -14,14 +14,13 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2008 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _IFXPROM_H__
#define _IFXPROM_H__
extern void prom_printf(const char * fmt, ...);
extern u32 *prom_get_cp1_base(void);
extern u32 prom_get_cp1_size(void);
extern int ifxmips_has_brn_block(void);
#endif

194
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips_serial.h
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@@ -1,194 +0,0 @@
/* incaAscSio.h - (IFXMIPS) ASC UART tty driver header */
#ifndef __IFXMIPS_ASC_H
#define __IFXMIPS_ASC_H
/******************************************************************************
**
** FILE NAME : serial.c
** PROJECT : IFXMips
** MODULES : ASC/UART
**
** DATE : 27 MAR 2006
** AUTHOR : Liu Peng
** DESCRIPTION : Asynchronous Serial Channel (ASC/UART) Driver Header File
** COPYRIGHT : Copyright (c) 2006
** Infineon Technologies AG
** Am Campeon 1-12, 85579 Neubiberg, Germany
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** HISTORY
** $Date $Author $Comment
** 27 MAR 2006 Liu Peng Initiate Version (rev 1.7)
** 23 OCT 2006 Xu Liang Add GPL header.
*******************************************************************************/
/* channel operating modes */
/*#define ASCOPT_CSIZE 0x00000003
#define ASCOPT_CS7 0x00000001
#define ASCOPT_CS8 0x00000002
#define ASCOPT_PARENB 0x00000004
#define ASCOPT_STOPB 0x00000008
#define ASCOPT_PARODD 0x00000010
#define ASCOPT_CREAD 0x00000020
*/
#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
/* ASC input select (0 or 1) */
#define CONSOLE_TTY 0
#define IFXMIPSASC_TXFIFO_FL 1
#define IFXMIPSASC_RXFIFO_FL 1
#define IFXMIPSASC_TXFIFO_FULL 16
/* interrupt lines masks for the ASC device interrupts*/
/* change these macroses if it's necessary */
#define IFXMIPSASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
#define IFXMIPSASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
#define IFXMIPSASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
#define IFXMIPSASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
#define IFXMIPSASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
#define IFXMIPSASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
#define IFXMIPSASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
#define IFXMIPSASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
/* interrupt controller access macros */
#define ASC_INTERRUPTS_ENABLE(X) \
*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) |= X;
#define ASC_INTERRUPTS_DISABLE(X) \
*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) &= ~X;
#define ASC_INTERRUPTS_CLEAR(X) \
*((volatile unsigned int*) IFXMIPS_ICU_IM0_ISR) = X;
/* CLC register's bits and bitfields */
#define ASCCLC_DISR 0x00000001
#define ASCCLC_DISS 0x00000002
#define ASCCLC_RMCMASK 0x0000FF00
#define ASCCLC_RMCOFFSET 8
/* CON register's bits and bitfields */
#define ASCCON_MODEMASK 0x0000000f
#define ASCCON_M_8ASYNC 0x0
#define ASCCON_M_8IRDA 0x1
#define ASCCON_M_7ASYNC 0x2
#define ASCCON_M_7IRDA 0x3
#define ASCCON_WLSMASK 0x0000000c
#define ASCCON_WLSOFFSET 2
#define ASCCON_WLS_8BIT 0x0
#define ASCCON_WLS_7BIT 0x1
#define ASCCON_PEN 0x00000010
#define ASCCON_ODD 0x00000020
#define ASCCON_SP 0x00000040
#define ASCCON_STP 0x00000080
#define ASCCON_BRS 0x00000100
#define ASCCON_FDE 0x00000200
#define ASCCON_ERRCLK 0x00000400
#define ASCCON_EMMASK 0x00001800
#define ASCCON_EMOFFSET 11
#define ASCCON_EM_ECHO_OFF 0x0
#define ASCCON_EM_ECHO_AB 0x1
#define ASCCON_EM_ECHO_ON 0x2
#define ASCCON_LB 0x00002000
#define ASCCON_ACO 0x00004000
#define ASCCON_R 0x00008000
#define ASCCON_PAL 0x00010000
#define ASCCON_FEN 0x00020000
#define ASCCON_RUEN 0x00040000
#define ASCCON_ROEN 0x00080000
#define ASCCON_TOEN 0x00100000
#define ASCCON_BEN 0x00200000
#define ASCCON_TXINV 0x01000000
#define ASCCON_RXINV 0x02000000
#define ASCCON_TXMSB 0x04000000
#define ASCCON_RXMSB 0x08000000
/* STATE register's bits and bitfields */
#define ASCSTATE_REN 0x00000001
#define ASCSTATE_PE 0x00010000
#define ASCSTATE_FE 0x00020000
#define ASCSTATE_RUE 0x00040000
#define ASCSTATE_ROE 0x00080000
#define ASCSTATE_TOE 0x00100000
#define ASCSTATE_BE 0x00200000
#define ASCSTATE_TXBVMASK 0x07000000
#define ASCSTATE_TXBVOFFSET 24
#define ASCSTATE_TXEOM 0x08000000
#define ASCSTATE_RXBVMASK 0x70000000
#define ASCSTATE_RXBVOFFSET 28
#define ASCSTATE_RXEOM 0x80000000
#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
/* WHBSTATE register's bits and bitfields */
#define ASCWHBSTATE_CLRREN 0x00000001
#define ASCWHBSTATE_SETREN 0x00000002
#define ASCWHBSTATE_CLRPE 0x00000004
#define ASCWHBSTATE_CLRFE 0x00000008
#define ASCWHBSTATE_CLRRUE 0x00000010
#define ASCWHBSTATE_CLRROE 0x00000020
#define ASCWHBSTATE_CLRTOE 0x00000040
#define ASCWHBSTATE_CLRBE 0x00000080
#define ASCWHBSTATE_SETPE 0x00000100
#define ASCWHBSTATE_SETFE 0x00000200
#define ASCWHBSTATE_SETRUE 0x00000400
#define ASCWHBSTATE_SETROE 0x00000800
#define ASCWHBSTATE_SETTOE 0x00001000
#define ASCWHBSTATE_SETBE 0x00002000
/* ABCON register's bits and bitfields */
#define ASCABCON_ABEN 0x0001
#define ASCABCON_AUREN 0x0002
#define ASCABCON_ABSTEN 0x0004
#define ASCABCON_ABDETEN 0x0008
#define ASCABCON_FCDETEN 0x0010
/* FDV register mask, offset and bitfields*/
#define ASCFDV_VALUE_MASK 0x000001FF
/* WHBABCON register's bits and bitfields */
#define ASCWHBABCON_CLRABEN 0x0001
#define ASCWHBABCON_SETABEN 0x0002
/* ABSTAT register's bits and bitfields */
#define ASCABSTAT_FCSDET 0x0001
#define ASCABSTAT_FCCDET 0x0002
#define ASCABSTAT_SCSDET 0x0004
#define ASCABSTAT_SCCDET 0x0008
#define ASCABSTAT_DETWAIT 0x0010
/* WHBABSTAT register's bits and bitfields */
#define ASCWHBABSTAT_CLRFCSDET 0x0001
#define ASCWHBABSTAT_SETFCSDET 0x0002
#define ASCWHBABSTAT_CLRFCCDET 0x0004
#define ASCWHBABSTAT_SETFCCDET 0x0008
#define ASCWHBABSTAT_CLRSCSDET 0x0010
#define ASCWHBABSTAT_SETSCSDET 0x0020
#define ASCWHBABSTAT_CLRSCCDET 0x0040
#define ASCWHBABSTAT_SETSCCDET 0x0080
#define ASCWHBABSTAT_CLRDETWAIT 0x0100
#define ASCWHBABSTAT_SETDETWAIT 0x0200
/* TXFCON register's bits and bitfields */
#define ASCTXFCON_TXFIFO1 0x00000400
#define ASCTXFCON_TXFEN 0x0001
#define ASCTXFCON_TXFFLU 0x0002
#define ASCTXFCON_TXFITLMASK 0x3F00
#define ASCTXFCON_TXFITLOFF 8
/* RXFCON register's bits and bitfields */
#define ASCRXFCON_RXFIFO1 0x00000400
#define ASCRXFCON_RXFEN 0x0001
#define ASCRXFCON_RXFFLU 0x0002
#define ASCRXFCON_RXFITLMASK 0x3F00
#define ASCRXFCON_RXFITLOFF 8
/* FSTAT register's bits and bitfields */
#define ASCFSTAT_RXFFLMASK 0x003F
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
#endif /* __IFXMIPS_ASC_H */