From 569d441b90681067e3872f1910c2672531dc23b2 Mon Sep 17 00:00:00 2001 From: ACwifidude Date: Fri, 25 Mar 2022 09:17:20 -0500 Subject: [PATCH] ipq806x: NSS Hardware Offloading .dts patch --- ...entries-in-dts-files-for-NSS-support.patch | 440 ++++++++++++++++++ 1 file changed, 440 insertions(+) create mode 100644 target/linux/ipq806x/patches-5.4/990-00-Add-required-entries-in-dts-files-for-NSS-support.patch diff --git a/target/linux/ipq806x/patches-5.4/990-00-Add-required-entries-in-dts-files-for-NSS-support.patch b/target/linux/ipq806x/patches-5.4/990-00-Add-required-entries-in-dts-files-for-NSS-support.patch new file mode 100644 index 0000000000..6e7ed649be --- /dev/null +++ b/target/linux/ipq806x/patches-5.4/990-00-Add-required-entries-in-dts-files-for-NSS-support.patch @@ -0,0 +1,440 @@ +--- b/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ a/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -1392,6 +1392,12 @@ + status = "disabled"; + }; + ++ nss-gmac-common { ++ compatible = "qcom,nss-gmac-common"; ++ reg = <0x03000000 0x0000FFFF 0x1bb00000 0x0000FFFF 0x00900000 0x00004000>; ++ reg-names = "nss_reg_base", "qsgmii_reg_base", "clk_ctl_base"; ++ }; ++ + gmac0: ethernet@37000000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac"; +@@ -1492,7 +1498,132 @@ + regulator-always-on; + }; + +- sdcc1bam:dma@12402000 { ++ nss0: nss@40000000 { ++ compatible = "qcom,nss"; ++ qcom,low-frequency = <733000000>; /* orig value 110000000 */ ++ qcom,mid-frequency = <733000000>; /* orig value 550000000 */ ++ qcom,max-frequency = <733000000>; ++ ++ interrupts = , ++ ; ++ reg = <0x36000000 0x1000 0x39000000 0x10000>; ++ reg-names = "nphys", "vphys"; ++ clocks = <&gcc NSS_CORE_CLK>, <&gcc NSSTCM_CLK_SRC>, ++ <&gcc NSSTCM_CLK>, <&rpmcc RPM_NSS_FABRIC_0_CLK>, ++ <&rpmcc RPM_NSS_FABRIC_1_CLK>; ++ clock-names = "nss-core-clk", "nss-tcm-src", ++ "nss-tcm-clk", "nss-fab0-clk", ++ "nss-fab1-clk"; ++ resets = <&gcc UBI32_CORE1_CLKRST_CLAMP_RESET>, ++ <&gcc UBI32_CORE1_CLAMP_RESET>, ++ <&gcc UBI32_CORE1_AHB_RESET>, ++ <&gcc UBI32_CORE1_AXI_RESET>; ++ reset-names = "clkrst-clamp", "clamp", "ahb", "axi"; ++ ++ qcom,id = <0>; ++ qcom,num-irq = <2>; ++ qcom,num-queue = <2>; ++ qcom,load-addr = <0x40000000>; ++ qcom,turbo-frequency; ++ ++ qcom,bridge-enabled; ++ qcom,gre-enabled; ++ qcom,gre-redir-enabled; ++ qcom,gre_tunnel_enabled; ++ qcom,ipv4-enabled; ++ qcom,ipv4-reasm-enabled; ++ qcom,ipv6-enabled; ++ qcom,ipv6-reasm-enabled; ++ qcom,l2tpv2-enabled; ++ qcom,map-t-enabled; ++ qcom,pppoe-enabled; ++ qcom,pptp-enabled; ++ qcom,portid-enabled; ++ qcom,shaping-enabled; ++ qcom,tun6rd-enabled; ++ qcom,tunipip6-enabled; ++ qcom,vlan-enabled; ++ qcom,wlan-dataplane-offload-enabled; ++ qcom,wlanredirect-enabled; ++ qcom,pxvlan-enabled; ++ qcom,vxlan-enabled; ++ qcom,match-enabled; ++ qcom,mirror-enabled; ++ qcom,rmnet-enabled; ++ qcom,clmap-enabled; ++ }; ++ ++ nss1: nss@40800000 { ++ compatible = "qcom,nss"; ++ qcom,low-frequency = <733000000>; /* orig value 110000000 */ ++ qcom,mid-frequency = <733000000>; /* orig value 550000000 */ ++ qcom,max-frequency = <733000000>; ++ ++ interrupts = , ++ ; ++ reg = <0x36400000 0x1000 0x39010000 0x10000>; ++ reg-names = "nphys", "vphys"; ++ resets = <&gcc UBI32_CORE2_CLKRST_CLAMP_RESET>, ++ <&gcc UBI32_CORE2_CLAMP_RESET>, ++ <&gcc UBI32_CORE2_AHB_RESET>, ++ <&gcc UBI32_CORE2_AXI_RESET>; ++ reset-names = "clkrst-clamp", "clamp", "ahb", "axi"; ++ ++ qcom,id = <1>; ++ qcom,num-irq = <2>; ++ qcom,load-addr = <0x40800000>; ++ qcom,num-queue = <2>; ++ qcom,turbo-frequency; ++ ++ qcom,capwap-enabled; ++ qcom,crypto-enabled; ++ qcom,dtls-enabled; ++ qcom,ipsec-enabled; ++ }; ++ ++ crypto1: crypto@38000000 { ++ compatible = "qcom,nss-crypto"; ++ reg = <0x38000000 0x20000>, <0x38004000 0x22000>; ++ reg-names = "crypto_pbase", "bam_base"; ++ clocks = <&gcc CE5_CORE_CLK>, <&gcc CE5_A_CLK>, <&gcc CE5_H_CLK>; ++ clock-names = "ce5_core", "ce5_aclk", "ce5_hclk"; ++ resets = <&gcc CRYPTO_ENG1_RESET>, <&gcc CRYPTO_AHB_RESET>; ++ reset-names = "rst_eng", "rst_ahb"; ++ qcom,id = <0>; ++ qcom,ee = <0>; ++ }; ++ ++ crypto2: crypto@38400000 { ++ compatible = "qcom,nss-crypto"; ++ reg = <0x38400000 0x20000>, <0x38404000 0x22000>; ++ reg-names = "crypto_pbase", "bam_base"; ++ resets = <&gcc CRYPTO_ENG2_RESET>; ++ reset-names = "rst_eng"; ++ qcom,id = <1>; ++ qcom,ee = <0>; ++ }; ++ ++ crypto3: crypto@38800000 { ++ compatible = "qcom,nss-crypto"; ++ reg = <0x38800000 0x20000>, <0x38804000 0x22000>; ++ reg-names = "crypto_pbase", "bam_base"; ++ resets = <&gcc CRYPTO_ENG3_RESET>; ++ reset-names = "rst_eng"; ++ qcom,id = <2>; ++ qcom,ee = <0>; ++ }; ++ ++ crypto4: crypto@38c00000 { ++ compatible = "qcom,nss-crypto"; ++ reg = <0x38c00000 0x20000>, <0x38c04000 0x22000>; ++ reg-names = "crypto_pbase", "bam_base"; ++ resets = <&gcc CRYPTO_ENG4_RESET>; ++ reset-names = "rst_eng"; ++ qcom,id = <3>; ++ qcom,ee = <0>; ++ }; ++ ++ sdcc1bam: dma@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x8000>; + interrupts = ; +@@ -1558,6 +1689,20 @@ + dma-names = "tx", "rx"; + }; + }; ++ ++ nss-common { ++ compatible = "qcom,nss-common"; ++ reg = <0x03000000 0x00001000>; ++ reg-names = "nss_fpb_base"; ++ clocks = <&gcc NSS_CORE_CLK>, <&gcc NSSTCM_CLK>, ++ <&rpmcc RPM_NSS_FABRIC_0_CLK>, <&rpmcc RPM_NSS_FABRIC_1_CLK>; ++ clock-names = "nss_core_clk", "nss_tcm_clk", ++ "nss-fab0-clk", "nss-fab1-clk"; ++ nss_core-supply = <&smb208_s1b>; ++ nss_core_vdd_nominal = <1100000>; ++ nss_core_vdd_high = <1150000>; ++ nss_core_threshold_freq = <733000000>; ++ }; + }; + + sfpb_mutex: sfpb-mutex { +@@ -1573,3 +1703,31 @@ + hwlocks = <&sfpb_mutex 3>; + }; + }; ++ ++ &gmac1 { ++ compatible = "qcom,nss-gmac"; ++ reg = <0x37200000 0x200000>; ++ interrupts = ; ++ qcom,pcs-chanid = <0>; ++ qcom,phy_mii_type = <0>; ++ qcom,emulation = <0>; ++ qcom,forced-speed = <1000>; ++ qcom,forced-duplex = <1>; ++ qcom,socver = <0>; ++ qcom,irq = <255>; ++ mdiobus = <&mdio0>; ++ }; ++ ++ &gmac2 { ++ compatible = "qcom,nss-gmac"; ++ reg = <0x37400000 0x200000>; ++ interrupts = ; ++ qcom,pcs-chanid = <1>; ++ qcom,phy_mii_type = <1>; ++ qcom,emulation = <0>; ++ qcom,forced-speed = <1000>; ++ qcom,forced-duplex = <1>; ++ qcom,socver = <0>; ++ qcom,irq = <258>; ++ mdiobus = <&mdio0>; ++ }; +--- b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi ++++ a/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi +@@ -18,6 +18,15 @@ + reg = <0x41200000 0x300000>; + no-map; + }; ++ ++ ramoops@42100000 { ++ compatible = "ramoops"; ++ reg = <0x42100000 0x40000>; ++ record-size = <0x4000>; ++ console-size = <0x4000>; ++ ftrace-size = <0x4000>; ++ pmsg-size = <0x4000>; ++ }; + }; + }; + +--- b/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi ++++ a/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi +@@ -170,10 +170,17 @@ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; ++ ++ phy4: ethernet-phy@4 { ++ reg = <4>; ++ }; + }; + + &gmac1 { + status = "okay"; ++ qcom,phy-mdio-addr = <0>; ++ qcom,poll-required = <0>; ++ qcom,rgmii-delay = <1>; + + phy-mode = "rgmii"; + qcom,id = <1>; +@@ -189,6 +196,9 @@ + + &gmac2 { + status = "okay"; ++ qcom,phy-mdio-addr = <4>; ++ qcom,poll-required = <0>; ++ qcom,rgmii-delay = <0>; + + phy-mode = "sgmii"; + qcom,id = <2>; +--- b/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts ++++ a/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts +@@ -103,20 +103,5 @@ + &mdio0 { + phy4: ethernet-phy@4 { + reg = <4>; + }; + }; +- +-&gmac1 { +- qcom,phy_mdio_addr = <4>; +- qcom,poll_required = <1>; +- qcom,rgmii_delay = <0>; +- qcom,emulation = <0>; +-}; +- +-/* LAN */ +-&gmac2 { +- qcom,phy_mdio_addr = <0>; /* none */ +- qcom,poll_required = <0>; /* no polling */ +- qcom,rgmii_delay = <0>; +- qcom,emulation = <0>; +-}; +--- b/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi ++++ a/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi +@@ -282,6 +282,9 @@ + + &gmac1 { + status = "okay"; ++ qcom,phy-mdio-addr = <4>; ++ qcom,poll-required = <0>; ++ qcom,rgmii-delay = <1>; + phy-mode = "rgmii"; + qcom,id = <1>; + +@@ -299,6 +302,9 @@ + + &gmac2 { + status = "okay"; ++ qcom,phy-mdio-addr = <0>; ++ qcom,poll-required = <0>; ++ qcom,rgmii-delay = <0>; + phy-mode = "sgmii"; + qcom,id = <2>; + +--- b/arch/arm/boot/dts/qcom-ipq8064-r7500.dts ++++ a/arch/arm/boot/dts/qcom-ipq8064-r7500.dts +@@ -254,6 +254,9 @@ + + &gmac1 { + status = "okay"; ++ qcom,phy-mdio-addr = <4>; ++ qcom,poll-required = <0>; ++ qcom,rgmii-delay = <1>; + phy-mode = "rgmii"; + qcom,id = <1>; + +@@ -270,6 +273,9 @@ + + &gmac2 { + status = "okay"; ++ qcom,phy-mdio-addr = <0>; ++ qcom,poll-required = <0>; ++ qcom,rgmii-delay = <0>; + phy-mode = "sgmii"; + qcom,id = <2>; + +--- b/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts ++++ a/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts +@@ -284,6 +284,9 @@ + + &gmac1 { + status = "okay"; ++ qcom,phy-mdio-addr = <4>; ++ qcom,poll-required = <0>; ++ qcom,rgmii-delay = <1>; + phy-mode = "rgmii"; + qcom,id = <1>; + +@@ -300,6 +303,9 @@ + + &gmac2 { + status = "okay"; ++ qcom,phy-mdio-addr = <0>; ++ qcom,poll-required = <0>; ++ qcom,rgmii-delay = <0>; + phy-mode = "sgmii"; + qcom,id = <2>; + +--- b/arch/arm/boot/dts/qcom-ipq8064-d7800.dts ++++ a/arch/arm/boot/dts/qcom-ipq8064-d7800.dts +@@ -282,6 +284,9 @@ + + &gmac1 { + status = "okay"; ++ qcom,phy-mdio-addr = <4>; ++ qcom,poll-required = <0>; ++ qcom,rgmii-delay = <1>; + phy-mode = "rgmii"; + qcom,id = <1>; + +@@ -298,6 +301,9 @@ + + &gmac2 { + status = "okay"; ++ qcom,phy-mdio-addr = <0>; ++ qcom,poll-required = <0>; ++ qcom,rgmii-delay = <0>; + phy-mode = "sgmii"; + qcom,id = <2>; + +--- b/arch/arm/boot/dts/qcom-ipq8064-g10.dts ++++ a/arch/arm/boot/dts/qcom-ipq8064-g10.dts +@@ -114,6 +114,9 @@ + + &gmac1 { + status = "okay"; ++ qcom,phy-mdio-addr = <4>; ++ qcom,poll-required = <0>; ++ qcom,rgmii-delay = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; +@@ -129,6 +132,9 @@ + + &gmac2 { + status = "okay"; ++ qcom,phy-mdio-addr = <0>; ++ qcom,poll-required = <0>; ++ qcom,rgmii-delay = <0>; + + phy-mode = "sgmii"; + qcom,id = <2>; +@@ -162,6 +168,10 @@ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; ++ ++ phy4: ethernet-phy@4 { ++ reg = <4>; ++ }; + }; + + &nand_controller { +--- b/arch/arm/boot/dts/qcom-ipq8065.dtsi ++++ a/arch/arm/boot/dts/qcom-ipq8065.dtsi +@@ -27,6 +27,15 @@ + reg = <0x41200000 0x300000>; + no-map; + }; ++ ++ ramoops@42100000 { ++ compatible = "ramoops"; ++ reg = <0x42100000 0x40000>; ++ record-size = <0x4000>; ++ console-size = <0x4000>; ++ ftrace-size = <0x4000>; ++ pmsg-size = <0x4000>; ++ }; + }; + }; + +@@ -155,3 +164,27 @@ + clock-latency-ns = <100000>; + }; + }; ++ ++ &nss0 { ++ qcom,low-frequency = <800000000>; ++ qcom,mid-frequency = <800000000>; ++ qcom,max-frequency = <800000000>; ++ }; ++ ++ &nss1 { ++ qcom,low-frequency = <800000000>; ++ qcom,mid-frequency = <800000000>; ++ qcom,max-frequency = <800000000>; ++ }; ++ ++ &gmac1 { ++ qcom,phy-mdio-addr = <4>; ++ qcom,poll-required = <0>; ++ qcom,rgmii-delay = <1>; ++ }; ++ ++ &gmac2 { ++ qcom,phy-mdio-addr = <0>; ++ qcom,poll-required = <0>; ++ qcom,rgmii-delay = <0>; ++ };