From 5eec0bc9c270b69878ec83067655aefe67433620 Mon Sep 17 00:00:00 2001 From: ACwifidude Date: Fri, 26 Feb 2021 18:07:50 -0600 Subject: [PATCH] ipq806x: NSS Hardware Offloading Required DTS and Voltage Entries --- ...s-in-dts-files-for-NSS-support.patch.patch | 170 ++++++++++++++ .../999-00-Regulator-Add-NSS-VOLT.patch | 212 ++++++++++++++++++ 2 files changed, 382 insertions(+) create mode 100644 target/linux/ipq806x/patches-5.4/990-00-Add-required-entries-in-dts-files-for-NSS-support.patch.patch create mode 100644 target/linux/ipq806x/patches-5.4/999-00-Regulator-Add-NSS-VOLT.patch diff --git a/target/linux/ipq806x/patches-5.4/990-00-Add-required-entries-in-dts-files-for-NSS-support.patch.patch b/target/linux/ipq806x/patches-5.4/990-00-Add-required-entries-in-dts-files-for-NSS-support.patch.patch new file mode 100644 index 0000000000..83d4ecf44d --- /dev/null +++ b/target/linux/ipq806x/patches-5.4/990-00-Add-required-entries-in-dts-files-for-NSS-support.patch.patch @@ -0,0 +1,170 @@ +--- b/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ a/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -1392,6 +1392,12 @@ + status = "disabled"; + }; + ++ nss-gmac-common { ++ compatible = "qcom,nss-gmac-common"; ++ reg = <0x03000000 0x0000FFFF 0x1bb00000 0x0000FFFF 0x00900000 0x00004000>; ++ reg-names = "nss_reg_base", "qsgmii_reg_base", "clk_ctl_base"; ++ }; ++ + gmac0: ethernet@37000000 { + device_type = "network"; + compatible = "qcom,ipq806x-gmac"; +@@ -1492,7 +1498,132 @@ + regulator-always-on; + }; + +- sdcc1bam:dma@12402000 { ++ nss0: nss@40000000 { ++ compatible = "qcom,nss"; ++ qcom,low-frequency = <733000000>; /* orig value 110000000 */ ++ qcom,mid-frequency = <733000000>; /* orig value 550000000 */ ++ qcom,max-frequency = <733000000>; ++ ++ interrupts = , ++ ; ++ reg = <0x36000000 0x1000 0x39000000 0x10000>; ++ reg-names = "nphys", "vphys"; ++ clocks = <&gcc NSS_CORE_CLK>, <&gcc NSSTCM_CLK_SRC>, ++ <&gcc NSSTCM_CLK>, <&rpmcc RPM_NSS_FABRIC_0_CLK>, ++ <&rpmcc RPM_NSS_FABRIC_1_CLK>; ++ clock-names = "nss-core-clk", "nss-tcm-src", ++ "nss-tcm-clk", "nss-fab0-clk", ++ "nss-fab1-clk"; ++ resets = <&gcc UBI32_CORE1_CLKRST_CLAMP_RESET>, ++ <&gcc UBI32_CORE1_CLAMP_RESET>, ++ <&gcc UBI32_CORE1_AHB_RESET>, ++ <&gcc UBI32_CORE1_AXI_RESET>; ++ reset-names = "clkrst-clamp", "clamp", "ahb", "axi"; ++ ++ qcom,id = <0>; ++ qcom,num-irq = <2>; ++ qcom,num-queue = <2>; ++ qcom,load-addr = <0x40000000>; ++ qcom,turbo-frequency; ++ ++ qcom,bridge-enabled; ++ qcom,gre-enabled; ++ qcom,gre-redir-enabled; ++ qcom,gre_tunnel_enabled; ++ qcom,ipv4-enabled; ++ qcom,ipv4-reasm-enabled; ++ qcom,ipv6-enabled; ++ qcom,ipv6-reasm-enabled; ++ qcom,l2tpv2-enabled; ++ qcom,map-t-enabled; ++ qcom,pppoe-enabled; ++ qcom,pptp-enabled; ++ qcom,portid-enabled; ++ qcom,shaping-enabled; ++ qcom,tun6rd-enabled; ++ qcom,tunipip6-enabled; ++ qcom,vlan-enabled; ++ qcom,wlan-dataplane-offload-enabled; ++ qcom,wlanredirect-enabled; ++ qcom,pxvlan-enabled; ++ qcom,vxlan-enabled; ++ qcom,match-enabled; ++ qcom,mirror-enabled; ++ qcom,rmnet-enabled; ++ qcom,clmap-enabled; ++ }; ++ ++ nss1: nss@40800000 { ++ compatible = "qcom,nss"; ++ qcom,low-frequency = <733000000>; /* orig value 110000000 */ ++ qcom,mid-frequency = <733000000>; /* orig value 550000000 */ ++ qcom,max-frequency = <733000000>; ++ ++ interrupts = , ++ ; ++ reg = <0x36400000 0x1000 0x39010000 0x10000>; ++ reg-names = "nphys", "vphys"; ++ resets = <&gcc UBI32_CORE2_CLKRST_CLAMP_RESET>, ++ <&gcc UBI32_CORE2_CLAMP_RESET>, ++ <&gcc UBI32_CORE2_AHB_RESET>, ++ <&gcc UBI32_CORE2_AXI_RESET>; ++ reset-names = "clkrst-clamp", "clamp", "ahb", "axi"; ++ ++ qcom,id = <1>; ++ qcom,num-irq = <2>; ++ qcom,load-addr = <0x40800000>; ++ qcom,num-queue = <2>; ++ qcom,turbo-frequency; ++ ++ qcom,capwap-enabled; ++ qcom,crypto-enabled; ++ qcom,dtls-enabled; ++ qcom,ipsec-enabled; ++ }; ++ ++ crypto1: crypto@38000000 { ++ compatible = "qcom,nss-crypto"; ++ reg = <0x38000000 0x20000>, <0x38004000 0x22000>; ++ reg-names = "crypto_pbase", "bam_base"; ++ clocks = <&gcc CE5_CORE_CLK>, <&gcc CE5_A_CLK>, <&gcc CE5_H_CLK>; ++ clock-names = "ce5_core", "ce5_aclk", "ce5_hclk"; ++ resets = <&gcc CRYPTO_ENG1_RESET>, <&gcc CRYPTO_AHB_RESET>; ++ reset-names = "rst_eng", "rst_ahb"; ++ qcom,id = <0>; ++ qcom,ee = <0>; ++ }; ++ ++ crypto2: crypto@38400000 { ++ compatible = "qcom,nss-crypto"; ++ reg = <0x38400000 0x20000>, <0x38404000 0x22000>; ++ reg-names = "crypto_pbase", "bam_base"; ++ resets = <&gcc CRYPTO_ENG2_RESET>; ++ reset-names = "rst_eng"; ++ qcom,id = <1>; ++ qcom,ee = <0>; ++ }; ++ ++ crypto3: crypto@38800000 { ++ compatible = "qcom,nss-crypto"; ++ reg = <0x38800000 0x20000>, <0x38804000 0x22000>; ++ reg-names = "crypto_pbase", "bam_base"; ++ resets = <&gcc CRYPTO_ENG3_RESET>; ++ reset-names = "rst_eng"; ++ qcom,id = <2>; ++ qcom,ee = <0>; ++ }; ++ ++ crypto4: crypto@38c00000 { ++ compatible = "qcom,nss-crypto"; ++ reg = <0x38c00000 0x20000>, <0x38c04000 0x22000>; ++ reg-names = "crypto_pbase", "bam_base"; ++ resets = <&gcc CRYPTO_ENG4_RESET>; ++ reset-names = "rst_eng"; ++ qcom,id = <3>; ++ qcom,ee = <0>; ++ }; ++ ++ sdcc1bam: dma@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x8000>; + interrupts = ; +@@ -1558,6 +1689,20 @@ + dma-names = "tx", "rx"; + }; + }; ++ ++ nss-common { ++ compatible = "qcom,nss-common"; ++ reg = <0x03000000 0x00001000>; ++ reg-names = "nss_fpb_base"; ++ clocks = <&gcc NSS_CORE_CLK>, <&gcc NSSTCM_CLK>, ++ <&rpmcc RPM_NSS_FABRIC_0_CLK>, <&rpmcc RPM_NSS_FABRIC_1_CLK>; ++ clock-names = "nss_core_clk", "nss_tcm_clk", ++ "nss-fab0-clk", "nss-fab1-clk"; ++ nss_core-supply = <&smb208_s1b>; ++ nss_core_vdd_nominal = <1100000>; ++ nss_core_vdd_high = <1150000>; ++ nss_core_threshold_freq = <733000000>; ++ }; + }; + + sfpb_mutex: sfpb-mutex { diff --git a/target/linux/ipq806x/patches-5.4/999-00-Regulator-Add-NSS-VOLT.patch b/target/linux/ipq806x/patches-5.4/999-00-Regulator-Add-NSS-VOLT.patch new file mode 100644 index 0000000000..ebe3e83409 --- /dev/null +++ b/target/linux/ipq806x/patches-5.4/999-00-Regulator-Add-NSS-VOLT.patch @@ -0,0 +1,212 @@ +From c70758d96b22e4421a6afd824cb59e350c6a8040 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 2 Jun 2020 22:09:15 +0200 +Subject: [PATCH] Regulator: Add NSS VOLT + +Signed-off-by: Robert Marko +--- + drivers/regulator/Kconfig | 7 +++++++ + drivers/regulator/Makefile | 1 + + 2 files changed, 8 insertions(+) + +--- a/drivers/regulator/Kconfig ++++ b/drivers/regulator/Kconfig +@@ -1105,5 +1105,12 @@ config REGULATOR_WM8994 + This driver provides support for the voltage regulators on the + WM8994 CODEC. + ++config REGULATOR_NSS_VOLT ++ bool "Qualcomm IPQ806X NSS Voltage regulator" ++ depends on ARCH_QCOM || COMPILE_TEST ++ help ++ This driver provides support for the Qualcomm IPQ806X NSS Voltage ++ regulator. ++ + endif + +--- a/drivers/regulator/Makefile ++++ b/drivers/regulator/Makefile +@@ -138,5 +138,6 @@ obj-$(CONFIG_REGULATOR_WM831X) += wm831x + obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o + obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o + obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o ++obj-$(CONFIG_REGULATOR_NSS_VOLT) += nss-volt-ipq806x.o + + ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG +--- a/dev/null +--- b/drivers/regulator/nss-volt-ipq806x.c +@@ -0,0 +1,146 @@ ++/* ++ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct nss_data { ++ struct regulator *nss_reg; ++ u32 nss_core_vdd_nominal; ++ u32 nss_core_vdd_high; ++ u32 nss_core_threshold_freq; ++}; ++ ++static struct nss_data *data; ++ ++int nss_ramp_voltage(unsigned long rate, bool ramp_up) ++{ ++ int ret; ++ int curr_uV, uV; ++ struct regulator *reg; ++ ++ if (!data) { ++ pr_err("NSS core regulator not init.\n"); ++ return -ENODEV; ++ } ++ ++ reg = data->nss_reg; ++ ++ if (!reg) { ++ pr_err("NSS core regulator not found.\n"); ++ return -EINVAL; ++ } ++ ++ uV = data->nss_core_vdd_nominal; ++ if (rate >= data->nss_core_threshold_freq) ++ return data->nss_core_vdd_high; ++ ++ curr_uV = regulator_get_voltage(reg); ++ ++ if (ramp_up) { ++ if (uV <= curr_uV) ++ return 0; ++ } else { ++ if (uV >= curr_uV) ++ return 0; ++ } ++ ++ ret = regulator_set_voltage(reg, uV, data->nss_core_vdd_high); ++ if (ret) ++ pr_err("NSS volt scaling failed (%d)\n", uV); ++ ++ return ret; ++} ++ ++static const struct of_device_id nss_ipq806x_match_table[] = { ++ { .compatible = "qcom,nss-common" }, ++ {} ++}; ++ ++static int nss_volt_ipq806x_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ int ret; ++ ++ if (!np) ++ return -ENODEV; ++ ++ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ data->nss_reg = devm_regulator_get(&pdev->dev, "nss_core"); ++ ret = PTR_ERR_OR_ZERO(data->nss_reg); ++ if (ret) { ++ if (ret == -EPROBE_DEFER) ++ dev_dbg(&pdev->dev, ++ "nss_core regulator not ready, retry\n"); ++ else ++ dev_err(&pdev->dev, "no regulator for nss_core: %d\n", ++ ret); ++ ++ return ret; ++ } ++ ++ if (of_property_read_u32(np, "nss_core_vdd_nominal", ++ &data->nss_core_vdd_nominal)) { ++ pr_warn("NSS core vdd nominal not found. Using defaults...\n"); ++ data->nss_core_vdd_nominal = 1100000; ++ } ++ ++ if (of_property_read_u32(np, "nss_core_vdd_high", ++ &data->nss_core_vdd_high)) { ++ pr_warn("NSS core vdd high not found. Using defaults...\n"); ++ data->nss_core_vdd_high = 1150000; ++ } ++ ++ if (of_property_read_u32(np, "nss_core_threshold_freq", ++ &data->nss_core_threshold_freq)) { ++ pr_warn("NSS core thres freq not found. Using defaults...\n"); ++ data->nss_core_threshold_freq = 733000000; ++ } ++ ++ platform_set_drvdata(pdev, data); ++ ++ return 0; ++} ++ ++static struct platform_driver nss_ipq806x_driver = { ++ .probe = nss_volt_ipq806x_probe, ++ .driver = { ++ .name = "nss-volt-ipq806x", ++ .owner = THIS_MODULE, ++ .of_match_table = nss_ipq806x_match_table, ++ }, ++}; ++ ++static int __init nss_ipq806x_init(void) ++{ ++ return platform_driver_register(&nss_ipq806x_driver); ++} ++late_initcall(nss_ipq806x_init); ++ ++static void __exit nss_ipq806x_exit(void) ++{ ++ platform_driver_unregister(&nss_ipq806x_driver); ++} ++module_exit(nss_ipq806x_exit); ++ +--- a/dev/null +--- b/include/linux/regulator/nss-volt-ipq806x.h +@@ -0,0 +1,25 @@ ++/* ++ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ */ ++ ++#ifndef __QCOM_NSS_VOL_SCALING_H ++#define __QCOM_NSS_VOL_SCALING_H ++ ++#include ++ ++int nss_ramp_voltage(unsigned long rate, bool ramp_up); ++ ++#endif ++