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imx6: add v4.1 support

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Build and boot tested on the following hardware:
 * GW54xx
 * GW53xx
 * GW52xx
 * GW51xx

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com>

SVN-Revision: 47331
This commit is contained in:
Felix Fietkau
2015-11-01 12:19:32 +00:00
parent 6a18146206
commit 6bc9a6d0a8
9 changed files with 2246 additions and 0 deletions
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11
target/linux/imx6/patches-4.1/100-bootargs.patch Normal file
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@@ -0,0 +1,11 @@
--- a/arch/arm/boot/dts/imx6dl-wandboard.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
@@ -19,4 +19,8 @@
memory {
reg = <0x10000000 0x40000000>;
};
+
+ chosen {
+ bootargs = "console=ttymxc0,115200";
+ };
};

129
target/linux/imx6/patches-4.1/202-net-igb-add-i210-i211-support-for-phy-read-write.patch Normal file
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@@ -0,0 +1,129 @@
Author: Tim Harvey <tharvey@gateworks.com>
Date: Thu May 15 00:12:26 2014 -0700
net: igb: add i210/i211 support for phy read/write
The i210/i211 uses the MDICNFG register for the phy address instead of the
MDIC register.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
--- a/drivers/net/ethernet/intel/igb/e1000_phy.c
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
@@ -135,7 +135,7 @@ out:
s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
{
struct e1000_phy_info *phy = &hw->phy;
- u32 i, mdic = 0;
+ u32 i, mdicnfg, mdic = 0;
s32 ret_val = 0;
if (offset > MAX_PHY_REG_ADDRESS) {
@@ -148,11 +148,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
- mdic = ((offset << E1000_MDIC_REG_SHIFT) |
- (phy->addr << E1000_MDIC_PHY_SHIFT) |
- (E1000_MDIC_OP_READ));
+ switch (hw->mac.type) {
+ case e1000_i210:
+ case e1000_i211:
+ mdicnfg = rd32(E1000_MDICNFG);
+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
+ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
+ wr32(E1000_MDICNFG, mdicnfg);
+ mdic = ((offset << E1000_MDIC_REG_SHIFT) |
+ (E1000_MDIC_OP_READ));
+ break;
+ default:
+ mdic = ((offset << E1000_MDIC_REG_SHIFT) |
+ (phy->addr << E1000_MDIC_PHY_SHIFT) |
+ (E1000_MDIC_OP_READ));
+ break;
+ }
wr32(E1000_MDIC, mdic);
+ wrfl();
/* Poll the ready bit to see if the MDI read completed
* Increasing the time out as testing showed failures with
@@ -177,6 +191,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
*data = (u16) mdic;
out:
+ switch (hw->mac.type) {
+ /* restore MDICNFG to have phy's addr */
+ case e1000_i210:
+ case e1000_i211:
+ mdicnfg = rd32(E1000_MDICNFG);
+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
+ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
+ wr32(E1000_MDICNFG, mdicnfg);
+ break;
+ default:
+ break;
+ }
return ret_val;
}
@@ -191,7 +217,7 @@ out:
s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
{
struct e1000_phy_info *phy = &hw->phy;
- u32 i, mdic = 0;
+ u32 i, mdicnfg, mdic = 0;
s32 ret_val = 0;
if (offset > MAX_PHY_REG_ADDRESS) {
@@ -204,12 +230,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
- mdic = (((u32)data) |
- (offset << E1000_MDIC_REG_SHIFT) |
- (phy->addr << E1000_MDIC_PHY_SHIFT) |
- (E1000_MDIC_OP_WRITE));
+ switch (hw->mac.type) {
+ case e1000_i210:
+ case e1000_i211:
+ mdicnfg = rd32(E1000_MDICNFG);
+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
+ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
+ wr32(E1000_MDICNFG, mdicnfg);
+ mdic = (((u32)data) |
+ (offset << E1000_MDIC_REG_SHIFT) |
+ (E1000_MDIC_OP_WRITE));
+ break;
+ default:
+ mdic = (((u32)data) |
+ (offset << E1000_MDIC_REG_SHIFT) |
+ (phy->addr << E1000_MDIC_PHY_SHIFT) |
+ (E1000_MDIC_OP_WRITE));
+ break;
+ }
wr32(E1000_MDIC, mdic);
+ wrfl();
/* Poll the ready bit to see if the MDI read completed
* Increasing the time out as testing showed failures with
@@ -233,6 +274,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_
}
out:
+ switch (hw->mac.type) {
+ /* restore MDICNFG to have phy's addr */
+ case e1000_i210:
+ case e1000_i211:
+ mdicnfg = rd32(E1000_MDICNFG);
+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
+ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
+ wr32(E1000_MDICNFG, mdicnfg);
+ break;
+ default:
+ break;
+ }
return ret_val;
}

260
target/linux/imx6/patches-4.1/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch Normal file
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@@ -0,0 +1,260 @@
From 16df7dc5901c1cb2a40f6adbd0d9423768ed8210 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Thu, 15 May 2014 00:29:18 -0700
Subject: [PATCH] net: igb: add phy read/write functions that accept phy addr
Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address.
The existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers
to this function.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
drivers/net/ethernet/intel/igb/e1000_82575.c | 4 +-
drivers/net/ethernet/intel/igb/e1000_phy.c | 74 +++++++++++++++++++---------
drivers/net/ethernet/intel/igb/e1000_phy.h | 6 ++-
3 files changed, 58 insertions(+), 26 deletions(-)
--- a/drivers/net/ethernet/intel/igb/e1000_82575.c
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
@@ -2129,7 +2129,7 @@ static s32 igb_read_phy_reg_82580(struct
if (ret_val)
goto out;
- ret_val = igb_read_phy_reg_mdic(hw, offset, data);
+ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data);
hw->phy.ops.release(hw);
@@ -2154,7 +2154,7 @@ static s32 igb_write_phy_reg_82580(struc
if (ret_val)
goto out;
- ret_val = igb_write_phy_reg_mdic(hw, offset, data);
+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data);
hw->phy.ops.release(hw);
--- a/drivers/net/ethernet/intel/igb/e1000_phy.c
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
@@ -132,9 +132,8 @@ out:
* Reads the MDI control regsiter in the PHY at offset and stores the
* information read to data.
**/
-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
{
- struct e1000_phy_info *phy = &hw->phy;
u32 i, mdicnfg, mdic = 0;
s32 ret_val = 0;
@@ -153,14 +152,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
case e1000_i211:
mdicnfg = rd32(E1000_MDICNFG);
mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
+ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
wr32(E1000_MDICNFG, mdicnfg);
mdic = ((offset << E1000_MDIC_REG_SHIFT) |
(E1000_MDIC_OP_READ));
break;
default:
mdic = ((offset << E1000_MDIC_REG_SHIFT) |
- (phy->addr << E1000_MDIC_PHY_SHIFT) |
+ (addr << E1000_MDIC_PHY_SHIFT) |
(E1000_MDIC_OP_READ));
break;
}
@@ -214,9 +213,8 @@ out:
*
* Writes data to MDI control register in the PHY at offset.
**/
-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
{
- struct e1000_phy_info *phy = &hw->phy;
u32 i, mdicnfg, mdic = 0;
s32 ret_val = 0;
@@ -235,7 +233,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
case e1000_i211:
mdicnfg = rd32(E1000_MDICNFG);
mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
+ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
wr32(E1000_MDICNFG, mdicnfg);
mdic = (((u32)data) |
(offset << E1000_MDIC_REG_SHIFT) |
@@ -244,7 +242,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
default:
mdic = (((u32)data) |
(offset << E1000_MDIC_REG_SHIFT) |
- (phy->addr << E1000_MDIC_PHY_SHIFT) |
+ (addr << E1000_MDIC_PHY_SHIFT) |
(E1000_MDIC_OP_WRITE));
break;
}
@@ -464,7 +462,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
goto out;
if (offset > MAX_PHY_MULTI_PAGE_REG) {
- ret_val = igb_write_phy_reg_mdic(hw,
+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
IGP01E1000_PHY_PAGE_SELECT,
(u16)offset);
if (ret_val) {
@@ -473,8 +471,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
}
}
- ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
- data);
+ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr,
+ MAX_PHY_REG_ADDRESS & offset, data);
hw->phy.ops.release(hw);
@@ -503,7 +501,7 @@ s32 igb_write_phy_reg_igp(struct e1000_h
goto out;
if (offset > MAX_PHY_MULTI_PAGE_REG) {
- ret_val = igb_write_phy_reg_mdic(hw,
+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
IGP01E1000_PHY_PAGE_SELECT,
(u16)offset);
if (ret_val) {
@@ -512,8 +510,8 @@ s32 igb_write_phy_reg_igp(struct e1000_h
}
}
- ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
- data);
+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
+ MAX_PHY_REG_ADDRESS & offset, data);
hw->phy.ops.release(hw);
@@ -2464,8 +2462,9 @@ out:
}
/**
- * igb_write_phy_reg_gs40g - Write GS40G PHY register
+ * igb_write_reg_gs40g - Write GS40G PHY register
* @hw: pointer to the HW structure
+ * @addr: phy address to write to
* @offset: lower half is register offset to write to
* upper half is page to use.
* @data: data to write at register offset
@@ -2473,7 +2472,7 @@ out:
* Acquires semaphore, if necessary, then writes the data to PHY register
* at the offset. Release any acquired semaphores before exiting.
**/
-s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
{
s32 ret_val;
u16 page = offset >> GS40G_PAGE_SHIFT;
@@ -2483,10 +2482,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000
if (ret_val)
return ret_val;
- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
+ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
if (ret_val)
goto release;
- ret_val = igb_write_phy_reg_mdic(hw, offset, data);
+ ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data);
release:
hw->phy.ops.release(hw);
@@ -2494,8 +2493,24 @@ release:
}
/**
- * igb_read_phy_reg_gs40g - Read GS40G PHY register
+ * igb_write_phy_reg_gs40g - Write GS40G PHY register
+ * @hw: pointer to the HW structure
+ * @offset: lower half is register offset to write to
+ * upper half is page to use.
+ * @data: data to write at register offset
+ *
+ * Acquires semaphore, if necessary, then writes the data to PHY register
+ * at the offset. Release any acquired semaphores before exiting.
+ **/
+s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
+{
+ return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data);
+}
+
+/**
+ * igb_read_reg_gs40g - Read GS40G PHY register
* @hw: pointer to the HW structure
+ * @addr: phy address to read from
* @offset: lower half is register offset to read to
* upper half is page to use.
* @data: data to read at register offset
@@ -2503,7 +2518,7 @@ release:
* Acquires semaphore, if necessary, then reads the data in the PHY register
* at the offset. Release any acquired semaphores before exiting.
**/
-s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
{
s32 ret_val;
u16 page = offset >> GS40G_PAGE_SHIFT;
@@ -2513,10 +2528,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_
if (ret_val)
return ret_val;
- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
+ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
if (ret_val)
goto release;
- ret_val = igb_read_phy_reg_mdic(hw, offset, data);
+ ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data);
release:
hw->phy.ops.release(hw);
@@ -2524,6 +2539,21 @@ release:
}
/**
+ * igb_read_phy_reg_gs40g - Read GS40G PHY register
+ * @hw: pointer to the HW structure
+ * @offset: lower half is register offset to read to
+ * upper half is page to use.
+ * @data: data to read at register offset
+ *
+ * Acquires semaphore, if necessary, then reads the data in the PHY register
+ * at the offset. Release any acquired semaphores before exiting.
+ **/
+s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
+{
+ return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data);
+}
+
+/**
* igb_set_master_slave_mode - Setup PHY for Master/slave mode
* @hw: pointer to the HW structure
*
--- a/drivers/net/ethernet/intel/igb/e1000_phy.h
+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h
@@ -61,8 +61,8 @@ s32 igb_phy_has_link(struct e1000_hw *h
void igb_power_up_phy_copper(struct e1000_hw *hw);
void igb_power_down_phy_copper(struct e1000_hw *hw);
s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
@@ -72,6 +72,8 @@ s32 igb_phy_force_speed_duplex_82580(st
s32 igb_get_cable_length_82580(struct e1000_hw *hw);
s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
s32 igb_check_polarity_m88(struct e1000_hw *hw);
/* IGP01E1000 Specific Registers */

308
target/linux/imx6/patches-4.1/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch Normal file
View File

@@ -0,0 +1,308 @@
From 03855caf93f7332a3f320228ba1a0e7baae8a749 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Thu, 15 May 2014 12:36:23 -0700
Subject: [PATCH] net: igb: register mii_bus for SerDes w/ external phy
If an i210 is configured for 1000BASE-BX link_mode and has an external phy
specified, then register an mii bus using the external phy address as
a mask.
An i210 hooked to an external standard phy will be configured with a link_mo
of SGMII in which case phy ops will be configured and used internall in the
igb driver for link status. However, in certain cases one might be using a
backplane SerDes connection to something that talks on the mdio bus but is
not a standard phy, such as a switch. In this case by registering an mdio
bus a phy driver can manage the device.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
drivers/net/ethernet/intel/igb/e1000_82575.c | 15 +++
drivers/net/ethernet/intel/igb/e1000_hw.h | 7 ++
drivers/net/ethernet/intel/igb/igb_main.c | 168 ++++++++++++++++++++++++++-
3 files changed, 185 insertions(+), 5 deletions(-)
--- a/drivers/net/ethernet/intel/igb/e1000_82575.c
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
@@ -598,13 +598,25 @@ static s32 igb_get_invariants_82575(stru
switch (link_mode) {
case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
hw->phy.media_type = e1000_media_type_internal_serdes;
+ if (igb_sgmii_uses_mdio_82575(hw)) {
+ u32 mdicnfg = rd32(E1000_MDICNFG);
+ mdicnfg &= E1000_MDICNFG_PHY_MASK;
+ hw->phy.addr = mdicnfg >> E1000_MDICNFG_PHY_SHIFT;
+ hw_dbg("1000BASE_KX w/ external MDIO device at 0x%x\n",
+ hw->phy.addr);
+ } else {
+ hw_dbg("1000BASE_KX");
+ }
break;
case E1000_CTRL_EXT_LINK_MODE_SGMII:
/* Get phy control interface type set (MDIO vs. I2C)*/
if (igb_sgmii_uses_mdio_82575(hw)) {
hw->phy.media_type = e1000_media_type_copper;
dev_spec->sgmii_active = true;
+ hw_dbg("SGMII with external MDIO PHY");
break;
+ } else {
+ hw_dbg("SGMII with external I2C PHY");
}
/* fall through for I2C based SGMII */
case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
@@ -621,8 +633,11 @@ static s32 igb_get_invariants_82575(stru
hw->phy.media_type = e1000_media_type_copper;
dev_spec->sgmii_active = true;
}
+ hw_dbg("SERDES with external SFP");
break;
+ } else {
+ hw_dbg("SERDES");
}
/* do not change link mode for 100BaseFX */
--- a/drivers/net/ethernet/intel/igb/e1000_hw.h
+++ b/drivers/net/ethernet/intel/igb/e1000_hw.h
@@ -27,6 +27,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/netdevice.h>
+#include <linux/phy.h>
#include "e1000_regs.h"
#include "e1000_defines.h"
@@ -543,6 +544,12 @@ struct e1000_hw {
struct e1000_mbx_info mbx;
struct e1000_host_mng_dhcp_cookie mng_cookie;
+#ifdef CONFIG_PHYLIB
+ /* Phylib and MDIO interface */
+ struct mii_bus *mii_bus;
+ struct phy_device *phy_dev;
+ phy_interface_t phy_interface;
+#endif
union {
struct e1000_dev_spec_82575 _82575;
} dev_spec;
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -41,6 +41,7 @@
#include <linux/if_vlan.h>
#include <linux/pci.h>
#include <linux/pci-aspm.h>
+#include <linux/phy.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/ip.h>
@@ -2231,6 +2232,126 @@ static s32 igb_init_i2c(struct igb_adapt
return status;
}
+
+#ifdef CONFIG_PHYLIB
+/*
+ * MMIO/PHYdev support
+ */
+
+static int igb_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+ struct e1000_hw *hw = bus->priv;
+ u16 out;
+ int err;
+
+ err = igb_read_reg_gs40g(hw, mii_id, regnum, &out);
+ if (err)
+ return err;
+ return out;
+}
+
+static int igb_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
+ u16 val)
+{
+ struct e1000_hw *hw = bus->priv;
+
+ return igb_write_reg_gs40g(hw, mii_id, regnum, val);
+}
+
+static int igb_enet_mdio_reset(struct mii_bus *bus)
+{
+ udelay(300);
+ return 0;
+}
+
+static void igb_enet_mii_link(struct net_device *netdev)
+{
+}
+
+/* Probe the mdio bus for phys and connect them */
+static int igb_enet_mii_probe(struct net_device *netdev)
+{
+ struct igb_adapter *adapter = netdev_priv(netdev);
+ struct e1000_hw *hw = &adapter->hw;
+ struct phy_device *phy_dev = NULL;
+ int phy_id;
+
+ /* check for attached phy */
+ for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
+ if (hw->mii_bus->phy_map[phy_id]) {
+ phy_dev = hw->mii_bus->phy_map[phy_id];
+ break;
+ }
+ }
+ if (!phy_dev) {
+ netdev_err(netdev, "no PHY found\n");
+ return -ENODEV;
+ }
+
+ hw->phy_interface = PHY_INTERFACE_MODE_RGMII;
+ phy_dev = phy_connect(netdev, dev_name(&phy_dev->dev),
+ igb_enet_mii_link, hw->phy_interface);
+ if (IS_ERR(phy_dev)) {
+ netdev_err(netdev, "could not attach to PHY\n");
+ return PTR_ERR(phy_dev);
+ }
+
+ hw->phy_dev = phy_dev;
+ netdev_info(netdev, "igb PHY driver [%s] (mii_bus:phy_addr=%s)\n",
+ hw->phy_dev->drv->name, dev_name(&hw->phy_dev->dev));
+
+ return 0;
+}
+
+/* Create and register mdio bus */
+static int igb_enet_mii_init(struct pci_dev *pdev)
+{
+ struct mii_bus *mii_bus;
+ struct net_device *netdev = pci_get_drvdata(pdev);
+ struct igb_adapter *adapter = netdev_priv(netdev);
+ struct e1000_hw *hw = &adapter->hw;
+ int err;
+
+ mii_bus = mdiobus_alloc();
+ if (mii_bus == NULL) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+
+ mii_bus->name = "igb_enet_mii_bus";
+ mii_bus->read = igb_enet_mdio_read;
+ mii_bus->write = igb_enet_mdio_write;
+ mii_bus->reset = igb_enet_mdio_reset;
+ snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+ pci_name(pdev), hw->device_id + 1);
+ mii_bus->priv = hw;
+ mii_bus->parent = &pdev->dev;
+ mii_bus->phy_mask = ~(1 << hw->phy.addr);
+
+ err = mdiobus_register(mii_bus);
+ if (err) {
+ printk(KERN_ERR "failed to register mii_bus: %d\n", err);
+ goto err_out_free_mdiobus;
+ }
+ hw->mii_bus = mii_bus;
+
+ return 0;
+
+err_out_free_mdiobus:
+ mdiobus_free(mii_bus);
+err_out:
+ return err;
+}
+
+static void igb_enet_mii_remove(struct e1000_hw *hw)
+{
+ if (hw->mii_bus) {
+ mdiobus_unregister(hw->mii_bus);
+ mdiobus_free(hw->mii_bus);
+ }
+}
+#endif /* CONFIG_PHYLIB */
+
/**
* igb_probe - Device Initialization Routine
* @pdev: PCI device information struct
@@ -2653,6 +2774,13 @@ static int igb_probe(struct pci_dev *pde
}
}
pm_runtime_put_noidle(&pdev->dev);
+
+#ifdef CONFIG_PHYLIB
+ /* create and register the mdio bus if using ext phy */
+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
+ igb_enet_mii_init(pdev);
+#endif
+
return 0;
err_register:
@@ -2796,6 +2924,10 @@ static void igb_remove(struct pci_dev *p
struct e1000_hw *hw = &adapter->hw;
pm_runtime_get_noresume(&pdev->dev);
+#ifdef CONFIG_PHYLIB
+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
+ igb_enet_mii_remove(hw);
+#endif
#ifdef CONFIG_IGB_HWMON
igb_sysfs_exit(adapter);
#endif
@@ -3101,6 +3233,12 @@ static int __igb_open(struct net_device
if (!resuming)
pm_runtime_put(&pdev->dev);
+#ifdef CONFIG_PHYLIB
+ /* Probe and connect to PHY if using ext phy */
+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
+ igb_enet_mii_probe(netdev);
+#endif
+
/* start the watchdog. */
hw->mac.get_link_status = 1;
schedule_work(&adapter->watchdog_task);
@@ -7097,21 +7235,41 @@ void igb_alloc_rx_buffers(struct igb_rin
static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
{
struct igb_adapter *adapter = netdev_priv(netdev);
+ struct e1000_hw *hw = &adapter->hw;
struct mii_ioctl_data *data = if_mii(ifr);
- if (adapter->hw.phy.media_type != e1000_media_type_copper)
+ if (adapter->hw.phy.media_type != e1000_media_type_copper &&
+ !(rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO))
return -EOPNOTSUPP;
switch (cmd) {
case SIOCGMIIPHY:
- data->phy_id = adapter->hw.phy.addr;
+ data->phy_id = hw->phy.addr;
break;
case SIOCGMIIREG:
- if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
- &data->val_out))
- return -EIO;
+ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
+ if (igb_read_reg_gs40g(&adapter->hw, data->phy_id,
+ data->reg_num & 0x1F,
+ &data->val_out))
+ return -EIO;
+ } else {
+ if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
+ &data->val_out))
+ return -EIO;
+ }
break;
case SIOCSMIIREG:
+ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
+ if (igb_write_reg_gs40g(hw, data->phy_id,
+ data->reg_num & 0x1F,
+ data->val_in))
+ return -EIO;
+ } else {
+ if (igb_write_phy_reg(hw, data->reg_num & 0x1F,
+ data->val_in))
+ return -EIO;
+ }
+ break;
default:
return -EOPNOTSUPP;
}

27
target/linux/imx6/patches-4.1/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch Normal file
View File

@@ -0,0 +1,27 @@
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -292,6 +292,14 @@ endif # RTL8366_SMI
source "drivers/net/phy/b53/Kconfig"
+config GATEWORKS_GW16083
+ tristate "Gateworks GW16083 Ethernet Expansion Mezzanine"
+ ---help---
+ The Gateworks GW16083 Ethernet Expansion Mezzanine connects to a
+ Gateworks Ventana baseboard and provides a 7-port GbE managed
+ Ethernet switch with 4 dedicated GbE RJ45 ports, and 2 Gbe/SFP
+ ports"
+
endif # PHYLIB
config MICREL_KS8995MA
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_DP83640_PHY) += dp83640.o
obj-$(CONFIG_STE10XP) += ste10Xp.o
obj-$(CONFIG_MICREL_PHY) += micrel.o
+obj-$(CONFIG_GATEWORKS_GW16083) += gw16083.o
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
obj-$(CONFIG_AT803X_PHY) += at803x.o

56
target/linux/imx6/patches-4.1/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch Normal file
View File

@@ -0,0 +1,56 @@
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -89,6 +89,11 @@
enable-active-high;
};
};
+
+ gw16083: gw16083@52 {
+ compatible = "gateworks,gw16083";
+ reg = <0x52>;
+ };
};
&fec {
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -266,6 +266,11 @@
};
};
};
+
+ gw16083: gw16083@52 {
+ compatible = "gateworks,gw16083";
+ reg = <0x52>;
+ };
};
&pcie {
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -267,6 +267,11 @@
};
};
};
+
+ gw16083: gw16083@52 {
+ compatible = "gateworks,gw16083";
+ reg = <0x52>;
+ };
};
&pcie {
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -308,6 +308,11 @@
};
};
};
+
+ gw16083: gw16083@52 {
+ compatible = "gateworks,gw16083";
+ reg = <0x52>;
+ };
};
&i2c3 {