add new target 'oxnas'

This is the oxnas target previously developed at http://gitorious.org/openwrt-oxnas Basically, this consolidates the changes and addtionas from http://github.org/kref/linux-oxnas into a new OpenWrt hardware target 'oxnas' adding support for PLX Technology NAS7820/NAS7821/NAS7825/... formally known as Oxford Semiconductor OXE810SE/OXE815/OX820/... For now there are 4 supported boards: Cloud Engines Pogoplug V3 (without PCIe) fully supported Cloud Engines Pogoplug Pro (with PCIe) fully supported MitraStar STG-212 aka ZyXEL NSA-212, aka Medion Akoya P89625 / P89636 / P89626 / P89630, aka Medion MD 86407 / MD 86805 / MD 86517 / MD 86587 fully supported, see http://wiki.openwrt.org/toh/medion/md86587 Shuttle KD-20 partially supported (S-ATA driver lacks support for 2nd port) Signed-off-by: Daniel Golle <daniel@makrotopia.org> SVN-Revision: 43388
2014-11-26 09:00:08 +00:00
parent 40da7aae54
commit 72b58f2eb1
54 changed files with 8328 additions and 0 deletions
--- a/package/kernel/linux/modules/usb.mk
+++ b/package/kernel/linux/modules/usb.mk
@@ -467,6 +467,23 @@ endef
 $(eval $(call KernelPackage,usb-dwc2))


+define KernelPackage/usb2-oxnas
+  TITLE:=OXNAS USB controller driver
+  DEPENDS:=@TARGET_oxnas +kmod-usb2
+  KCONFIG:=CONFIG_USB_EHCI_OXNAS
+  FILES:=$(LINUX_DIR)/drivers/usb/host/ehci-oxnas.ko
+  AUTOLOAD:=$(call AutoLoad,55,ehci-oxnas,1)
+  $(call AddDepends/usb)
+endef
+
+define KernelPackage/usb2-oxnas/description
+ This driver provides USB Device Controller support for the
+ EHCI USB host built-in to the PLXTECH NAS782x SoC
+endef
+
+$(eval $(call KernelPackage,usb2-oxnas))
+
+
 define KernelPackage/usb-acm
  TITLE:=Support for modems/isdn controllers
  KCONFIG:=CONFIG_USB_ACM
--- a/target/linux/oxnas/Makefile
+++ b/target/linux/oxnas/Makefile
@@ -0,0 +1,28 @@
+#
+# Copyright (C) 2013 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+
+ARCH:=arm
+BOARD:=oxnas
+BOARDNAME:=PLXTECH NAS782X
+DEVICE_TYPE:=nas
+FEATURES:=gpio nand pcie usb usbgadget ramdisk rtc squashfs
+CPU_TYPE:=mpcore
+
+MAINTAINER:=Daniel Golle <daniel@makrotopia.org>
+
+KERNEL_PATCHVER:=3.18
+
+include $(INCLUDE_DIR)/target.mk
+
+DEFAULT_PACKAGES += \
+	kmod-button-hotplug kmod-input-gpio-keys-polled kmod-leds-gpio		\
+	kmod-i2c-gpio uboot-envtools uboot-oxnas-ox820
+
+KERNELNAME:=zImage dtbs
+
+$(eval $(call BuildTarget))
--- a/target/linux/oxnas/base-files.mk
+++ b/target/linux/oxnas/base-files.mk
@@ -0,0 +1,3 @@
+define Package/base-files/install-target
+	rm -f $(1)/etc/config/network
+endef
--- a/target/linux/oxnas/base-files/etc/board.d/01_leds
+++ b/target/linux/oxnas/base-files/etc/board.d/01_leds
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+. /lib/functions/uci-defaults-new.sh
+. /lib/oxnas.sh
+
+board=$(oxnas_board_name)
+board_config_update
+
+case $board in
+	stg-212)
+		ucidef_set_led_default "power" "power" "zyxel:blue:status" "1"
+		ucidef_set_led_usbdev "usb" "USB" "$1" "1-1"
+		;;
+	kd20)
+		ucidef_set_led_default "power" "power" "kd20:blue:status" "1"
+		;;
+	pogoplugpro | pogoplugv3)
+		ucidef_set_led_default "power" "power" "pogoplug:blue:internal" "1"
+		;;
+
+esac
+
+board_config_flush
+
+exit 0
--- a/target/linux/oxnas/base-files/etc/board.d/02_network
+++ b/target/linux/oxnas/base-files/etc/board.d/02_network
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+. /lib/functions/uci-defaults-new.sh
+. /lib/functions/system.sh
+
+board_config_update
+
+ucidef_set_interface_lan "eth0"
+
+board_config_flush
+
+exit 0
--- a/target/linux/oxnas/base-files/etc/diag.sh
+++ b/target/linux/oxnas/base-files/etc/diag.sh
@@ -0,0 +1,35 @@
+#!/bin/sh
+# Copyright (C) 2009-2013 OpenWrt.org
+
+. /lib/functions/leds.sh
+. /lib/oxnas.sh
+
+get_status_led() {
+	case $(oxnas_board_name) in
+	stg212)
+		status_led="zyxel:blue:status"
+		;;
+	kd20)
+		status_led="kd20:blue:status"
+		;;
+	pogoplugpro | pogoplugv3)
+		status_led="pogoplug:blue:internal"
+		;;
+	esac
+}
+
+set_state() {
+	get_status_led
+
+	case "$1" in
+	preinit)
+		status_led_blink_preinit
+		;;
+	failsafe)
+		status_led_blink_failsafe
+		;;
+	done)
+		status_led_on
+		;;
+	esac
+}
--- a/target/linux/oxnas/base-files/lib/oxnas.sh
+++ b/target/linux/oxnas/base-files/lib/oxnas.sh
@@ -0,0 +1,48 @@
+#!/bin/sh
+#
+# Copyright (C) 2013 OpenWrt.org
+#
+
+OXNAS_BOARD_NAME=
+OXNAS_MODEL=
+
+oxnas_board_detect() {
+	local machine
+	local name
+
+	machine=$(cat /proc/device-tree/model)
+
+	case "$machine" in
+	*"MitraStar Technology Corp. STG-212"*)
+		name="stg212"
+		;;
+	*"Shuttle KD20"*)
+		name="kd20"
+		;;
+	*"Pogoplug Pro"*)
+		name="pogoplugpro"
+		;;
+	*"Pogoplug V3"*)
+		name="pogoplugv3"
+		;;
+	esac
+
+	[ -z "$name" ] && name="unknown"
+
+	[ -z "$OXNAS_BOARD_NAME" ] && OXNAS_BOARD_NAME="$name"
+	[ -z "$OXNAS_MODEL" ] && OXNAS_MODEL="$machine"
+
+	[ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/"
+
+	echo "$OXNAS_BOARD_NAME" > /tmp/sysinfo/board_name
+	echo "$OXNAS_MODEL" > /tmp/sysinfo/model
+}
+
+oxnas_board_name() {
+	local name
+
+	[ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name)
+	[ -z "$name" ] && name="unknown"
+
+	echo "$name"
+}
--- a/target/linux/oxnas/base-files/lib/preinit/03_preinit_do_oxnas.sh
+++ b/target/linux/oxnas/base-files/lib/preinit/03_preinit_do_oxnas.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+do_oxnas() {
+	. /lib/oxnas.sh
+
+	oxnas_board_detect
+}
+
+boot_hook_add preinit_main do_oxnas
--- a/target/linux/oxnas/base-files/lib/upgrade/platform.sh
+++ b/target/linux/oxnas/base-files/lib/upgrade/platform.sh
@@ -0,0 +1,35 @@
+#
+# Copyright (C) 2014 OpenWrt.org
+#
+
+. /lib/oxnas.sh
+
+RAMFS_COPY_DATA=/lib/oxnas.sh
+
+platform_check_image() {
+	local board=$(oxnas_board_name)
+
+	[ "$ARGC" -gt 1 ] && return 1
+
+	nand_do_platform_check $board $1
+	return $?
+}
+
+platform_do_upgrade() {
+	if [ $$ -ne 1 ]; then
+		echo "not PID 1, upgrade aborted."
+		return 1;
+	fi
+	platform_do_upgrade_phase2 "$1" "$CONF_TAR" "$SAVE_CONFIG"
+}
+
+
+disable_watchdog() {
+	killall watchdog
+	( ps | grep -v 'grep' | grep '/dev/watchdog' ) && {
+		echo 'Could not disable watchdog'
+		return 1
+	}
+}
+
+append sysupgrade_pre_upgrade disable_watchdog
--- a/target/linux/oxnas/config-3.18
+++ b/target/linux/oxnas/config-3.18
@@ -0,0 +1,366 @@
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OXNAS=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+# CONFIG_ARM_CPU_SUSPEND is not set
+CONFIG_ARM_GIC=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ATA=y
+# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
+CONFIG_AUTO_ZRELADDR=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_RPS_TIMER=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="console=ttyS0,115200n8 earlyprintk=serial"
+CONFIG_COMMON_CLK=y
+# CONFIG_COMMON_CLK_PXA is not set
+CONFIG_COMPACTION=y
+CONFIG_CONSOLE_POLL=y
+CONFIG_COREDUMP=y
+CONFIG_CPU_32v6=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_ABRT_EV6=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_PABRT_V6=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_V6K=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_XZ=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEBUG_LL_UART_8250 is not set
+CONFIG_DEBUG_LL_UART_NONE=y
+# CONFIG_DEBUG_LL_UART_PL01X is not set
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_UART_BCM63XX is not set
+# CONFIG_DEBUG_UART_PL01X is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=8
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DIRECT_IO=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CACHE_FIQ_BROADCAST=y
+# CONFIG_DMA_CACHE_RWFO is not set
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+# CONFIG_DW_DMAC_CORE is not set
+# CONFIG_DW_DMAC_PCI is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_FIQ=y
+# CONFIG_FSL_EDMA is not set
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+# CONFIG_GPIO_SYSCON is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZ4=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_LRO=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INET_UDP_DIAG=y
+CONFIG_INPUT=y
+# CONFIG_INPUT_MISC is not set
+# CONFIG_INTEL_SOC_PMIC is not set
+CONFIG_IOMMU_HELPER=y
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_MULTICAST is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_BOOTP is not set
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KERNFS=y
+CONFIG_KGDB=y
+# CONFIG_KGDB_KDB is not set
+CONFIG_KGDB_SERIAL_CONSOLE=y
+# CONFIG_KGDB_TESTS is not set
+# CONFIG_LDM_DEBUG is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LEDS_SYSCON is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+# CONFIG_LEDS_TRIGGER_NETDEV is not set
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACH_OX820=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAILBOX=y
+CONFIG_MDIO_BOARDINFO=y
+# CONFIG_MFD_AXP20X is not set
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_VEXPRESS_SYSREG=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MIGRATION=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MODULE_STRIPPED is not set
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_OXNAS=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UIMAGE_SPLIT=y
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+# CONFIG_NBPFAXI_DMA is not set
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NLS=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=2
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PACKET_DIAG=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_OXNAS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_OXNAS=y
+CONFIG_PLXTECH_RPS=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PPS=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PWM=y
+# CONFIG_PWM_FSL_FTM is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_RAS=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELAY=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_CONTROLLER_OXNAS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SATA_OXNAS=y
+CONFIG_SCHED_HRTICK=y
+CONFIG_SCSI=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_EARLYCON=y
+# CONFIG_SERIAL_KGDB_NMI is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SOCK_DIAG=y
+CONFIG_STMMAC_DA=y
+CONFIG_STMMAC_DEBUG_FS=y
+CONFIG_STMMAC_ETH=y
+# CONFIG_STMMAC_PCI is not set
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_STOP_MACHINE=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SWIOTLB=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TREE_RCU=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_XZ=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UID16=y
+CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h"
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USE_OF=y
+CONFIG_VECTORS_BASE=0xffff0000
+# CONFIG_VEXPRESS_CONFIG is not set
+# CONFIG_VEXPRESS_SYSCFG is not set
+# CONFIG_VFP is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA_FLAG=0
--- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-kd20.dts
+++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-kd20.dts
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2014 Daniel Golle <daniel@makrotopia.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "ox820.dtsi"
+
+/ {
+	model = "Shuttle KD20";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk=serial";
+	};
+
+	pcie-controller@47C00000 {
+		status = "okay";
+	};
+
+	uart@44200000 {
+		status = "okay";
+	};
+
+	sata@45900000 {
+		status = "okay";
+	};
+
+	nand@41000000 {
+		status = "okay";
+
+		partition@0 {
+			label = "boot";
+			reg = <0x00000000 0x00e00000>;
+			/*read-only;*/
+		};
+
+		partition@e00000 {
+			label = "ubi";
+			reg = <0x00e00000 0x07200000>;
+		};
+	};
+
+	ethernet@40400000 {
+		status = "okay";
+		snps,phy-addr = <1>;
+		phy-mode = "rgmii-id";
+	};
+
+	ehci@40200100 {
+		status = "okay";
+	};
+
+	i2c-gpio {
+		compatible = "i2c-gpio";
+		gpios = <&GPIOB 9 0 &GPIOB 10 0>;
+		i2c-gpio,delay-us = <10>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pcf8563: rtc@51 {
+			compatible = "nxp,pcf8563";
+			reg = <0x51>;
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		power {
+			label = "power";
+			gpios = <&GPIOA 10 1>;
+			linux,code = <116>;
+		};
+		reset {
+			label = "reset";
+			gpios = <&GPIOA 11 1>;
+			linux,code = <0x198>;
+		};
+		eject1 {
+			label = "eject1";
+			gpios = <&GPIOA 5 1>;
+			linux,code = <161>;
+		};
+		eject2 {
+			label = "eject2";
+			gpios = <&GPIOA 6 1>;
+			linux,code = <162>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		status {
+			label = "kd20:blue:status";
+			gpios = <&GPIOB 16 0>;
+		};
+		status2 {
+			label = "kd20:red:status";
+			gpios = <&GPIOB 17 0>;
+		};
+		hdd1blue {
+			label = "kd20:blue:hdd1";
+			gpios = <&GPIOA 27 0>;
+		};
+		hdd1red {
+			label = "kd20:red:hdd1";
+			gpios = <&GPIOB 4 0>;
+		};
+		hdd2blue {
+			label = "kd20:blue:hdd2";
+			gpios = <&GPIOB 6 0>;
+		};
+		hdd2red {
+			label = "kd20:red:hdd2";
+			gpios = <&GPIOB 7 0>;
+		};
+		usb {
+			label = "kd20:blue:usb";
+			gpios = <&GPIOB 8 0>;
+		};
+		buzzer {
+			label = "kd20:buzzer";
+			gpios = <&GPIOB 11 0>;
+		};
+	};
+
+	gpio-fan {
+		compatible = "gpio-fan";
+		gpios = <&GPIOA 2 1>;
+	};
+};
--- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts
+++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "ox820.dtsi"
+
+/ {
+	model = "Pogoplug Pro";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk=serial";
+	};
+
+	pcie-controller@47C00000 {
+		status = "okay";
+	};
+
+	uart@44200000 {
+		status = "okay";
+	};
+
+	sata@45900000 {
+		status = "okay";
+	};
+
+	nand@41000000 {
+		status = "okay";
+
+		partition@0 {
+			label = "boot";
+			reg = <0x00000000 0x00e00000>;
+			/*read-only;*/
+		};
+
+		partition@e00000 {
+			label = "ubi";
+			reg = <0x00e00000 0x07200000>;
+		};
+	};
+
+	ethernet@40400000 {
+		status = "okay";
+	};
+
+	ehci@40200100 {
+		status = "okay";
+	};
+
+	pinctrl {
+		leds {
+			pinctrl_leds: leds-0 {
+				plxtech,pins =
+					<0 2 0 0	/* MF_A2 */
+					 1 16 0 0	/* MF_B16 */
+					 1 17 0 0>;	/* MF_B17 */
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_leds>;
+
+		blue {
+			label = "pogoplug:blue:internal";
+			gpios = <&GPIOA 2 0>;
+
+		};
+
+		orange {
+			label = "pogoplug:orange:usr";
+			gpios = <&GPIOB 16 1>;
+		};
+
+		green {
+			label = "pogoplug:green:usr";
+			gpios = <&GPIOB 17 1>;
+		};
+	};
+};
--- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts
+++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2014 Daniel Golle <daniel@makrotopia.org>
+ * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "ox820.dtsi"
+
+/ {
+	model = "Pogoplug V3";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk=serial";
+	};
+
+	uart@44200000 {
+		status = "okay";
+	};
+
+	sata@45900000 {
+		status = "okay";
+	};
+
+	nand@41000000 {
+		status = "okay";
+
+		partition@0 {
+			label = "boot";
+			reg = <0x00000000 0x00e00000>;
+			/*read-only;*/
+		};
+
+		partition@e00000 {
+			label = "ubi";
+			reg = <0x00e00000 0x07200000>;
+		};
+	};
+
+	ethernet@40400000 {
+		status = "okay";
+	};
+
+	ehci@40200100 {
+		status = "okay";
+	};
+
+	pinctrl {
+		leds {
+			pinctrl_leds: leds-0 {
+				plxtech,pins =
+					<0 2 0 0	/* MF_A2 */
+					 1 16 0 0	/* MF_B16 */
+					 1 17 0 0>;	/* MF_B17 */
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_leds>;
+
+		blue {
+			label = "pogoplug:blue:internal";
+			gpios = <&GPIOA 2 0>;
+		};
+
+		orange {
+			label = "pogoplug:orange:usr";
+			gpios = <&GPIOB 16 1>;
+		};
+
+		green {
+			label = "pogoplug:green:usr";
+			gpios = <&GPIOB 17 1>;
+		};
+	};
+
+};
--- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-stg212.dts
+++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-stg212.dts
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2013 OpenWrt.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "ox820.dtsi"
+
+/ {
+	model = "MitraStar Technology Corp. STG-212";
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk=serial";
+	};
+
+	uart@44200000 {
+		status = "okay";
+	};
+
+	sata@45900000 {
+		status = "okay";
+	};
+
+	nand@41000000 {
+		status = "okay";
+
+		partition@0 {
+			label = "boot";
+			reg = <0x00000000 0x00e00000>;
+			/*read-only;*/
+		};
+
+		partition@e00000 {
+			label = "ubi";
+			reg = <0x00e00000 0x07200000>;
+		};
+	};
+
+	ethernet@40400000 {
+		status = "okay";
+	};
+
+	ehci@40200100 {
+		status = "okay";
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		reset {
+			label = "reset";
+			gpios = <&GPIOB 11 1>;
+			linux,code = <0x198>;
+		};
+		copy {
+			label = "copy";
+			gpios = <&GPIOB 13 1>;
+			linux,code = <0x85>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		status {
+			label = "zyxel:blue:status";
+			gpios = <&GPIOB 5 0>;
+		};
+		status2 {
+			label = "zyxel:red:status";
+			gpios = <&GPIOB 6 1>;
+		};
+		copy {
+			label = "zyxel:orange:copy";
+			gpios = <&GPIOB 8 1>;
+		};
+	};
+
+	i2c-gpio {
+		compatible = "i2c-gpio";
+		gpios = <&GPIOB 9 0 &GPIOB 10 0>;
+		i2c-gpio,delay-us = <10>;
+	};
+
+};
--- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi
+++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi
@@ -0,0 +1,342 @@
+/*
+ * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "plxtech,nas7820", "plxtech,nas782x";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &uart0;
+		/* alias to determine bank index */
+		gpio0 = &GPIOA;
+		gpio1 = &GPIOB;
+
+		ethernet0 = &gmac;
+	};
+
+	cpus {
+		cpu@0 {
+			compatible = "arm,arm11mpcore";
+		};
+		cpu@1 {
+			compatible = "arm,arm11mpcore";
+		};
+	};
+
+	gic: gic@47001000 {
+		compatible = "arm,arm11mp-gic";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0x47001000 0x1000>,
+		      <0x47000100 0x0100>;
+	};
+
+	rst: reset-controller@44E00034 {
+		compatible = "plxtech,nas782x-reset";
+		#reset-cells = <1>;
+		reg = <0x44E00034 0x8>; /* currently not used */
+	};
+
+	rps: rps@44400000 {
+		compatible = "plxtech,nas782x-rps";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0x44400000 0x14>;
+		interrupts = <0 5 0x304>;
+	};
+
+	/* external oscillator */
+	osc: oscillator {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency  = <25000000>;
+	};
+
+	sysclk: sysclk {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clock-div = <4>;
+		clock-mult = <1>;
+		clocks = <&osc>;
+	};
+
+	plla: plla@44e001f0 {
+		compatible = "plxtech,nas782x-plla";
+		#clock-cells = <0>;
+		clocks = <&osc>;
+		reg = <0x44e001f0 0x10>;
+	};
+
+	pllb: pllb@44f001f0 {
+		compatible = "plxtech,nas782x-pllb";
+		#clock-cells = <0>;
+		clocks = <&osc>;
+		reg = <0x44f001f0 0x10>;
+		resets = <&rst 31>;
+	};
+
+	stdclk: stdclk {
+		compatible = "plxtech,nas782x-stdclk";
+		#clock-cells = <1>;
+		clocks = <&osc>;
+	};
+
+	twdclk: twdclk {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clock-div = <2>;
+		clock-mult = <1>;
+		clocks = <&plla>;
+	};
+
+	gmacclk: gmacclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency  = <125000000>;
+	};
+
+	pinctrl {
+		/* act as a simple bus, so children will be probed automatically */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "plxtech,nas782x-pinctrl", "simple-bus";
+		ranges;
+
+		plxtech,mux-mask = <
+			 0xFFFFFFFF 0xCC0FFDF9 0xFC000E60 0x0F03F7E0 0xF00C0FE0
+			 0x0003FFFF 0x00037FFF 0x0003FFF8 0x00000F00 0x0003F7F3
+			>;
+
+		GPIOA: gpio@44000000 {
+			compatible = "plxtech,nas782x-gpio";
+			reg = <0x44000000 0x100>, <0x44E00000 0x200>;
+			interrupts = <0 21 0x304>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			#gpio-lines = <32>; /* real gpio pin count */
+		};
+
+		GPIOB: gpio@44100000 {
+			compatible = "plxtech,nas782x-gpio";
+			reg = <0x44100000 0x100>, <0x44F00000 0x200>;
+			interrupts = <0 22 0x304>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			#gpio-lines = <18>; /* real gpio pin count */
+		};
+
+		uart0 {
+			pinctrl_uart0: uart0-0 {
+				plxtech,pins =
+					<0 30 5 0	/* MF_A30 PINMUX_ALT PINMUX_UARTA_SIN */
+					 0 31 5 0>;	/* MF_A31 PINMUX_ALT PINMUX_UARTA_SOUT */
+			};
+		};
+
+		gmac0 {
+			pinctrl_gmac0: gmac0-0 {
+				plxtech,pins =
+					<0 3 1 0	/* MF_A3 PINMUX_2 PINMUX_MACA_MDC */
+					 0 4 1 0>;	/* MF_A4 PINMUX_2 PINMUX_MACA_MDIO */
+			};
+		};
+
+		nand0 {
+			pinctrl_nand0: nand0-0 {
+				plxtech,pins =
+					<0 12 1 0	/* MF_A12 PINMUX_2 PINMUX_STATIC_DATA0 */
+					 0 13 1 0	/* MF_A13 PINMUX_2 PINMUX_STATIC_DATA1 */
+					 0 14 1 0	/* MF_A14 PINMUX_2 PINMUX_STATIC_DATA2 */
+					 0 15 1 0	/* MF_A15 PINMUX_2 PINMUX_STATIC_DATA3 */
+					 0 16 1 0	/* MF_A16 PINMUX_2 PINMUX_STATIC_DATA4 */
+					 0 17 1 0	/* MF_A17 PINMUX_2 PINMUX_STATIC_DATA5 */
+					 0 18 1 0	/* MF_A18 PINMUX_2 PINMUX_STATIC_DATA6 */
+					 0 19 1 0	/* MF_A19 PINMUX_2 PINMUX_STATIC_DATA7 */
+
+					 0 20 1 0	/* MF_A20 PINMUX_2 PINMUX_STATIC_NWE */
+					 0 21 1 0	/* MF_A21 PINMUX_2 PINMUX_STATIC_NOE */
+					 0 22 1 0	/* MF_A22 PINMUX_2 PINMUX_STATIC_NCS */
+					 0 23 1 0	/* MF_A23 PINMUX_2 PINMUX_STATIC_ADDR18 */
+					 0 24 1 0>;	/* MF_A24 PINMUX_2 PINMUX_STATIC_ADDR19 */
+			};
+		};
+	};
+
+	pcie-controller@47C00000 {
+		compatible = "plxtech,nas782x-pcie";
+		device_type = "pci";
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		/*		flag & space	bus address	host address	size */
+		ranges = <	0x82000000	0 0x48000000	0x48000000	0 0x2000000
+				0xC2000000	0 0x4A000000	0x4A000000	0 0x1E00000
+				0x81000000	0 0x4BE00000	0x4BE00000	0 0x0100000
+				0x80000000	0 0x4BF00000	0x4BF00000	0 0x0100000>;
+
+		bus-range = <0x00 0x7f>;
+
+		/*	cfg			inbound translator	phy*/
+		reg =	<0x47C00000 0x1000>,	<0x47D00000 0x100>,	 <0x44A00000 0x10>;
+
+		#interrupt-cells = <1>;
+		/* wild card mask, match all bus address & interrupt specifier */
+		/* format: bus address mask, interrupt specifier mask */
+		/* each bit 1 means need match, 0 means ignored when match */
+		interrupt-map-mask = <0 0 0 0>;
+		/* format: a list of: bus address, interrupt specifier,
+		 * parent interrupt controller & specifier */
+		interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
+
+		gpios = <&GPIOB 12 0>;
+		clocks = <&stdclk 8>, <&pllb>;
+		clock-names = "pcie", "busclk";
+		resets = <&rst 7>, <&rst 14>;
+		reset-names = "pcie", "phy";
+
+		plxtech,pcie-hcsl-bit = <2>;
+		plxtech,pcie-ctrl-offset = <0x120>;
+		plxtech,pcie-outbound-offset = <0x138>;
+		status = "disabled";
+	};
+
+	pcie-controller@47E00000 {
+		compatible = "plxtech,nas782x-pcie";
+		device_type = "pci";
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		/*		flag & space	bus address	host address	size */
+		ranges = <	0x82000000	0 0x4C000000	0x4C000000	0 0x2000000
+				0xC2000000	0 0x4E000000	0x4E000000	0 0x1E00000
+				0x81000000	0 0x4FE00000	0x4FE00000	0 0x0100000
+				0x80000000	0 0x4FF00000	0x4FF00000	0 0x0100000>;
+
+		bus-range = <0x80 0xff>;
+
+		/*	cfg			inbound translator	phy*/
+		reg =	<0x47E00000 0x1000>,	<0x47F00000 0x100>,	<0x44A00000 0x10>;
+
+		#interrupt-cells = <1>;
+		/* wild card mask, match all bus address & interrupt specifier */
+		/* format: bus address mask, interrupt specifier mask */
+		/* each bit 1 means need match, 0 means ignored when match */
+		interrupt-map-mask = <0 0 0 0>;
+		/* format: a list of: bus address, interrupt specifier,
+		 * parent interrupt controller & specifier */
+		interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
+
+		/* gpios = <&GPIOB 12 0>; */
+		clocks = <&stdclk 11>, <&pllb>;
+		clock-names = "pcie", "busclk";
+		resets = <&rst 23>, <&rst 14>;
+		reset-names = "pcie", "phy";
+
+		plxtech,pcie-hcsl-bit = <3>;
+		plxtech,pcie-ctrl-offset = <0x124>;
+		plxtech,pcie-outbound-offset = <0x174>;
+		status = "disabled";
+	};
+
+	local-timer@47000600 {
+		compatible = "arm,arm11mp-twd-timer";
+		reg = <0x47000600 0x20>;
+		interrupts = <1 13 0x304>;	/* percpu, irq 29, cpu mask 3, level high */
+		clocks = <&twdclk>;
+	};
+
+	watchdog@47000620 {
+		compatible = "mpcore_wdt";
+		reg = <0x47000620 0x20>;
+		interrupts = <1 14 0x304>;	/* percpu, irq 30, cpu mask 3, level high */
+		clocks = <&twdclk>;
+	};
+
+	timer@44400200 {
+		compatible = "plxtech,nas782x-rps-timer";
+		reg = <0x44400200 0x40>;
+		clocks = <&sysclk>;
+	};
+
+	uart0: uart@44200000 {
+		compatible = "ns16550a";
+		reg = <0x44200000 0x100>;
+		clock-frequency = <6250000>;
+		interrupts = <0 23 0x304>;
+		reg-shift = <0>;
+		fifo-size = <16>;
+		reg-io-width = <1>;
+		current-speed = <115200>;
+		no-loopback-test;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_uart0>;
+		status = "disabled";
+	};
+
+	sata@45900000 {
+		compatible = "plxtech,nas782x-sata";
+			/*	port		sgdma		core	*/
+		reg = <0x45900000 0x100>, <0x459B0000 0x10>, <0x459E0000 0x2000>,
+			/*	phy		descriptors (optional)	*/
+			<0x44900000 0x0C>, <0x50000000 0x1000>;
+		interrupts = <0 18 0x304>;
+		clocks = <&stdclk 4>;
+		resets = <&rst 11>, <&rst 12>, <&rst 13>;
+		reset-names = "sata", "link", "phy";
+		status = "disabled";
+	};
+
+	nand@41000000 {
+		compatible = "plxtech,nand-nas782x", "gen_nand";
+		reg = <0x41000000 0x100000>, <0x41C00000 0x20>;
+		nand-ecc-mode = "soft";
+		clocks = <&stdclk 9>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_nand0>;
+		resets = <&rst 15>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		status = "disabled";
+	};
+
+	gmac: ethernet@40400000 {
+		compatible = "plxtech,nas782x-gmac", "snps,dwmac";
+		reg = <0x40400000 0x2000>;
+		interrupts = <0 8 0x304>, <0 17 0x304>;
+		interrupt-names = "macirq", "eth_wake_irq";
+		mac-address = [000000000000]; /* Filled in by U-Boot */
+		phy-mode = "rgmii";
+		clocks = <&stdclk 7>, <&gmacclk>;
+		clock-names = "gmac", "stmmaceth";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gmac0>;
+		resets = <&rst 6>;
+		status = "disabled";
+	};
+
+	ehci@40200100 {
+		compatible = "plxtech,nas782x-ehci";
+		reg = <0x40200100 0xf00>;
+		interrupts = <0 7 0x304>;
+		clocks = <&stdclk 6>, <&pllb>, <&stdclk 12>;
+		clock-names = "usb", "refsrc", "phyref";
+		resets = <&rst 4>, <&rst 5>, <&rst 26>;
+		reset-names = "host", "phya", "phyb";
+		/* Otherwise ref300 is used, which is derived from sata phy
+		 * in that case, usb depends on sata initialization */
+		/* FIXME: how to make this dependency explicit ? */
+		plxtch,ehci_use_pllb;
+		status = "disabled";
+	};
+};
--- a/target/linux/oxnas/files/arch/arm/configs/ox820_defconfig
+++ b/target/linux/oxnas/files/arch/arm/configs/ox820_defconfig
@@ -0,0 +1,104 @@
+CONFIG_CROSS_COMPILE="arm-linux-gnueabi-"
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_CGROUPS=y
+CONFIG_NAMESPACES=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_ARCH_OXNAS=y
+# CONFIG_DMA_CACHE_RWFO is not set
+CONFIG_DMA_CACHE_FIQ_BROADCAST=y
+CONFIG_PCI=y
+CONFIG_PCI_OXNAS=y
+CONFIG_SMP=y
+# CONFIG_SMP_ON_UP is not set
+CONFIG_NR_CPUS=2
+CONFIG_HOTPLUG_CPU=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_USE_OF=y
+CONFIG_BINFMT_MISC=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IPV6=y
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
+CONFIG_MAC80211_RC_PID=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_OXNAS=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_ATA=y
+CONFIG_SATA_OXNAS=y
+CONFIG_NETDEVICES=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_DEBUG_FS=y
+CONFIG_STMMAC_DA=y
+CONFIG_ATH_CARDS=y
+CONFIG_ATH9K=y
+CONFIG_ATH9K_LEGACY_RATE_CONTROL=y
+# CONFIG_RTL_CARDS is not set
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_OXNAS=y
+CONFIG_USB_STORAGE=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_COMMON_CLK_DEBUG=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=m
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0x44200000
+CONFIG_DEBUG_UART_VIRT=0xF0000000
+CONFIG_DEBUG_UART_8250_SHIFT=0
+CONFIG_EARLY_PRINTK=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig
@@ -0,0 +1,24 @@
+choice
+	prompt "Oxnas platform type"
+	default MACH_OXNAS
+	depends on ARCH_OXNAS
+
+config MACH_OX820
+	bool "Generic NAS7820 Support"
+	select ARM_GIC
+	select GENERIC_CLOCKEVENTS
+	select CPU_V6K
+	select HAVE_ARM_SCU if SMP
+	select HAVE_ARM_TWD if SMP
+	select HAVE_SMP
+	select PLXTECH_RPS
+	select CLKSRC_OF
+	select CLKSRC_RPS_TIMER
+	select USB_ARCH_HAS_EHCI
+	select PINCTRL_OXNAS
+	select PINCTRL
+	select RESET_CONTROLLER_OXNAS
+	help
+	  Include support for the ox820 platform.
+
+endchoice
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-$(CONFIG_MACH_OX820)		+= mach-ox820.o
+obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
+obj-$(CONFIG_DMA_CACHE_FIQ_BROADCAST)	+= fiq.o
+obj-$(CONFIG_HOTPLUG_CPU)		+= hotplug.o
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile.boot
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile.boot
@@ -0,0 +1,2 @@
+   zreladdr-y	+= 0x60008000
+params_phys-y	:= 0x60000100
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S
@@ -0,0 +1,87 @@
+/*
+ *  Copyright (C) 2012 Gateworks Corporation
+ *      Chris Lang <clang@gateworks.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
+
+#define D_CACHE_LINE_SIZE 32
+
+	.text
+
+/*
+ * R8  - DMA Start Address
+ * R9  - DMA Length
+ * R10 - DMA Direction
+ * R11 - DMA type
+ * R12 - fiq_buffer Address
+*/
+
+	.global	ox820_fiq_end
+ENTRY(ox820_fiq_start)
+	str	r8, [r13]
+
+	ldmia	r12, {r8, r9, r10}
+	and	r11, r10, #0x3000000
+	and	r10, r10, #0xff
+
+	teq	r11, #0x1000000
+	beq	ox820_dma_map_area
+	teq	r11, #0x2000000
+	beq	ox820_dma_unmap_area
+	/* fall through */
+ox820_dma_flush_range:
+	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
+1:
+	mcr	p15, 0, r8, c7, c14, 1		@ clean & invalidate D line
+	add	r8, r8, #D_CACHE_LINE_SIZE
+	cmp	r8, r9
+	blo	1b
+	/* fall through */
+ox820_fiq_exit:
+	mov	r8, #0
+	str	r8, [r12, #8]
+	mcr	p15, 0, r8, c7, c10, 4		@ drain write buffer
+	subs	pc, lr, #4
+
+ox820_dma_map_area:
+	add	r9, r9, r8
+	teq	r10, #DMA_FROM_DEVICE
+	beq	ox820_dma_inv_range
+	teq	r10, #DMA_TO_DEVICE
+	bne	ox820_dma_flush_range
+	/* fall through */
+ox820_dma_clean_range:
+	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
+1:
+	mcr	p15, 0, r8, c7, c10, 1		@ clean D line
+	add	r8, r8, #D_CACHE_LINE_SIZE
+	cmp	r8, r9
+	blo	1b
+	b	ox820_fiq_exit
+
+ox820_dma_unmap_area:
+	add	r9, r9, r8
+	teq	r10, #DMA_TO_DEVICE
+	beq	ox820_fiq_exit
+	/* fall through */
+ox820_dma_inv_range:
+	tst	r8, #D_CACHE_LINE_SIZE - 1
+	bic	r8, r8, #D_CACHE_LINE_SIZE - 1
+	mcrne	p15, 0, r8, c7, c10, 1		@ clean D line
+	tst	r9, #D_CACHE_LINE_SIZE - 1
+	bic	r9, r9, #D_CACHE_LINE_SIZE - 1
+	mcrne	p15, 0, r9, c7, c14, 1		@ clean & invalidate D line
+1:
+	mcr	p15, 0, r8, c7, c6, 1		@ invalidate D line
+	add	r8, r8, #D_CACHE_LINE_SIZE
+	cmp	r8, r9
+	blo	1b
+	b	ox820_fiq_exit
+
+ox820_fiq_end:
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/headsmp.S
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/headsmp.S
@@ -0,0 +1,27 @@
+/*
+ *  linux/arch/arm/mach-ox820/headsmp.S
+ *
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+	__INIT
+
+/*
+ * OX820 specific entry point for secondary CPUs.
+ */
+ENTRY(ox820_secondary_startup)
+	mov r4, #0
+	/* invalidate both caches and branch target cache */
+	mcr p15, 0, r4, c7, c7, 0
+	/*
+	 * we've been released from the holding pen: secondary_stack
+	 * should now contain the SVC stack for this core
+	 */
+	b	secondary_startup
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/hotplug.c
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/hotplug.c
@@ -0,0 +1,112 @@
+/*
+ *  linux/arch/arm/mach-realview/hotplug.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+
+#include <asm/cp15.h>
+#include <asm/smp_plat.h>
+#include <mach/smp.h>
+
+static inline void cpu_enter_lowpower(void)
+{
+	unsigned int v;
+
+	asm volatile(
+	"	mcr	p15, 0, %1, c7, c5, 0\n"
+	"	mcr	p15, 0, %1, c7, c10, 4\n"
+	/*
+	 * Turn off coherency
+	 */
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	bic	%0, %0, #0x20\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	"	mrc	p15, 0, %0, c1, c0, 0\n"
+	"	bic	%0, %0, %2\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	  : "=&r" (v)
+	  : "r" (0), "Ir" (CR_C)
+	  : "cc");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+	unsigned int v;
+
+	asm volatile("mrc	p15, 0, %0, c1, c0, 0\n"
+	"	orr	%0, %0, %1\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	orr	%0, %0, #0x20\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	  : "=&r" (v)
+	  : "Ir" (CR_C)
+	  : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+{
+	/*
+	 * there is no power-control hardware on this platform, so all
+	 * we can do is put the core into WFI; this is safe as the calling
+	 * code will have already disabled interrupts
+	 */
+	for (;;) {
+		/*
+		 * here's the WFI
+		 */
+		asm(".word	0xe320f003\n"
+		    :
+		    :
+		    : "memory", "cc");
+
+		if (read_pen_release() == cpu_logical_map(cpu)) {
+			/*
+			 * OK, proper wakeup, we're done
+			 */
+			break;
+		}
+
+		/*
+		 * Getting here, means that we have come out of WFI without
+		 * having been woken up - this shouldn't happen
+		 *
+		 * Just note it happening - when we're woken, we can report
+		 * its occurrence.
+		 */
+		(*spurious)++;
+	}
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __ref ox820_cpu_die(unsigned int cpu)
+{
+	int spurious = 0;
+
+	/*
+	 * we're ready for shutdown now, so do it
+	 */
+	cpu_enter_lowpower();
+	platform_do_lowpower(cpu, &spurious);
+
+	/*
+	 * bring this CPU back into the world of cache
+	 * coherency, and then restore interrupts
+	 */
+	cpu_leave_lowpower();
+
+	if (spurious)
+		pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+}
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/hardware.h
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/hardware.h
@@ -0,0 +1,233 @@
+/*
+ * arch/arm/mach-0x820/include/mach/hardware.h
+ *
+ * Copyright (C) 2009 Oxford Semiconductor Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/io.h>
+#include <mach/iomap.h>
+
+/*
+ * Location of flags and vectors in SRAM for controlling the booting of the
+ * secondary ARM11 processors.
+ */
+
+#define OXNAS_SCU_BASE_VA		OXNAS_PERCPU_BASE_VA
+#define OXNAS_GICN_BASE_VA(n)		(OXNAS_PERCPU_BASE_VA + 0x200 + n*0x100)
+
+#define HOLDINGPEN_CPU			IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8)
+#define HOLDINGPEN_LOCATION		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4)
+
+/**
+ * System block reset and clock control
+ */
+#define SYS_CTRL_PCI_STAT		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x20)
+#define SYSCTRL_CLK_STAT		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x24)
+#define SYS_CTRL_CLK_SET_CTRL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x2C)
+#define SYS_CTRL_CLK_CLR_CTRL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x30)
+#define SYS_CTRL_RST_SET_CTRL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x34)
+#define SYS_CTRL_RST_CLR_CTRL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x38)
+
+#define SYS_CTRL_PLLSYS_CTRL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x48)
+#define SYS_CTRL_CLK_CTRL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x64)
+#define SYS_CTRL_PLLSYS_KEY_CTRL	IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x6C)
+#define SYS_CTRL_GMAC_CTRL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x78)
+#define SYS_CTRL_GMAC_DELAY_CTRL	IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x100)
+
+/* Scratch registers */
+#define SYS_CTRL_SCRATCHWORD0		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4)
+#define SYS_CTRL_SCRATCHWORD1		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8)
+#define SYS_CTRL_SCRATCHWORD2		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xcc)
+#define SYS_CTRL_SCRATCHWORD3		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xd0)
+
+#define SYS_CTRL_PLLA_CTRL0		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F0)
+#define SYS_CTRL_PLLA_CTRL1		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F4)
+#define SYS_CTRL_PLLA_CTRL2		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F8)
+#define SYS_CTRL_PLLA_CTRL3		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1FC)
+
+#define SYS_CTRL_USBHSMPH_CTRL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x40)
+#define SYS_CTRL_USBHSMPH_STAT		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x44)
+#define SYS_CTRL_REF300_DIV		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xF8)
+#define SYS_CTRL_USBHSPHY_CTRL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x84)
+#define SYS_CTRL_USB_CTRL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x90)
+
+/* pcie */
+#define SYS_CTRL_HCSL_CTRL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x114)
+
+/* System control multi-function pin function selection */
+#define SYS_CTRL_SECONDARY_SEL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x14)
+#define SYS_CTRL_TERTIARY_SEL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x8c)
+#define SYS_CTRL_QUATERNARY_SEL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x94)
+#define SYS_CTRL_DEBUG_SEL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x9c)
+#define SYS_CTRL_ALTERNATIVE_SEL	IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xa4)
+#define SYS_CTRL_PULLUP_SEL		IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xac)
+
+/* Secure control multi-function pin function selection */
+#define SEC_CTRL_SECONDARY_SEL		IOMEM(OXNAS_SECCRTL_BASE_VA + 0x14)
+#define SEC_CTRL_TERTIARY_SEL		IOMEM(OXNAS_SECCRTL_BASE_VA + 0x8c)
+#define SEC_CTRL_QUATERNARY_SEL		IOMEM(OXNAS_SECCRTL_BASE_VA + 0x94)
+#define SEC_CTRL_DEBUG_SEL		IOMEM(OXNAS_SECCRTL_BASE_VA + 0x9c)
+#define SEC_CTRL_ALTERNATIVE_SEL	IOMEM(OXNAS_SECCRTL_BASE_VA + 0xa4)
+#define SEC_CTRL_PULLUP_SEL		IOMEM(OXNAS_SECCRTL_BASE_VA + 0xac)
+
+#define SEC_CTRL_COPRO_CTRL		IOMEM(OXNAS_SECCRTL_BASE_VA + 0x68)
+#define SEC_CTRL_SECURE_CTRL		IOMEM(OXNAS_SECCRTL_BASE_VA + 0x98)
+#define SEC_CTRL_LEON_DEBUG		IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF0)
+#define SEC_CTRL_PLLB_DIV_CTRL		IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF8)
+#define SEC_CTRL_PLLB_CTRL0		IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F0)
+#define SEC_CTRL_PLLB_CTRL1		IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4)
+#define SEC_CTRL_PLLB_CTRL8		IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4)
+
+#define RPSA_IRQ_SOFT			IOMEM(OXNAS_RPSA_BASE_VA + 0x10)
+#define RPSA_FIQ_ENABLE			IOMEM(OXNAS_RPSA_BASE_VA + 0x108)
+#define RPSA_FIQ_DISABLE		IOMEM(OXNAS_RPSA_BASE_VA + 0x10C)
+#define RPSA_FIQ_IRQ_TO_FIQ		IOMEM(OXNAS_RPSA_BASE_VA + 0x1FC)
+
+#define RPSC_IRQ_SOFT			IOMEM(OXNAS_RPSC_BASE_VA + 0x10)
+#define RPSC_FIQ_ENABLE			IOMEM(OXNAS_RPSC_BASE_VA + 0x108)
+#define RPSC_FIQ_DISABLE		IOMEM(OXNAS_RPSC_BASE_VA + 0x10C)
+#define RPSC_FIQ_IRQ_TO_FIQ		IOMEM(OXNAS_RPSC_BASE_VA + 0x1FC)
+
+#define RPSA_TIMER2_VAL			IOMEM(OXNAS_RPSA_BASE_VA + 0x224)
+
+#define REF300_DIV_INT_SHIFT		8
+#define REF300_DIV_FRAC_SHIFT		0
+#define REF300_DIV_INT(val)		((val) << REF300_DIV_INT_SHIFT)
+#define REF300_DIV_FRAC(val)		((val) << REF300_DIV_FRAC_SHIFT)
+
+#define USBHSPHY_SUSPENDM_MANUAL_ENABLE		16
+#define USBHSPHY_SUSPENDM_MANUAL_STATE		15
+#define USBHSPHY_ATE_ESET			14
+#define USBHSPHY_TEST_DIN			6
+#define USBHSPHY_TEST_ADD			2
+#define USBHSPHY_TEST_DOUT_SEL			1
+#define USBHSPHY_TEST_CLK			0
+
+#define USB_CTRL_USBAPHY_CKSEL_SHIFT	5
+#define USB_CLK_XTAL0_XTAL1		(0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+#define USB_CLK_XTAL0			(1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+#define USB_CLK_INTERNAL		(2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+
+#define USBAMUX_DEVICE			BIT(4)
+
+#define USBPHY_REFCLKDIV_SHIFT		2
+#define USB_PHY_REF_12MHZ		(0 << USBPHY_REFCLKDIV_SHIFT)
+#define USB_PHY_REF_24MHZ		(1 << USBPHY_REFCLKDIV_SHIFT)
+#define USB_PHY_REF_48MHZ		(2 << USBPHY_REFCLKDIV_SHIFT)
+
+#define USB_CTRL_USB_CKO_SEL_BIT	0
+
+#define USB_INT_CLK_XTAL		0
+#define USB_INT_CLK_REF300		2
+#define USB_INT_CLK_PLLB		3
+
+#define SYS_CTRL_GMAC_CKEN_RX_IN	14
+#define SYS_CTRL_GMAC_CKEN_RXN_OUT	13
+#define SYS_CTRL_GMAC_CKEN_RX_OUT	12
+#define SYS_CTRL_GMAC_CKEN_TX_IN	10
+#define SYS_CTRL_GMAC_CKEN_TXN_OUT	9
+#define SYS_CTRL_GMAC_CKEN_TX_OUT	8
+#define SYS_CTRL_GMAC_RX_SOURCE		7
+#define SYS_CTRL_GMAC_TX_SOURCE		6
+#define SYS_CTRL_GMAC_LOW_TX_SOURCE	4
+#define SYS_CTRL_GMAC_AUTO_TX_SOURCE	3
+#define SYS_CTRL_GMAC_RGMII		2
+#define SYS_CTRL_GMAC_SIMPLE_MUX	1
+#define SYS_CTRL_GMAC_CKEN_GTX		0
+#define SYS_CTRL_GMAC_TX_VARDELAY_SHIFT		0
+#define SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT	8
+#define SYS_CTRL_GMAC_RX_VARDELAY_SHIFT		16
+#define SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT	24
+#define SYS_CTRL_GMAC_TX_VARDELAY(d)	((d)<<SYS_CTRL_GMAC_TX_VARDELAY_SHIFT)
+#define SYS_CTRL_GMAC_TXN_VARDELAY(d)	((d)<<SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT)
+#define SYS_CTRL_GMAC_RX_VARDELAY(d)	((d)<<SYS_CTRL_GMAC_RX_VARDELAY_SHIFT)
+#define SYS_CTRL_GMAC_RXN_VARDELAY(d)	((d)<<SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT)
+
+#define PLLB_BYPASS			1
+#define PLLB_ENSAT			3
+#define PLLB_OUTDIV			4
+#define PLLB_REFDIV			8
+#define PLLB_DIV_INT_SHIFT		8
+#define PLLB_DIV_FRAC_SHIFT		0
+#define PLLB_DIV_INT(val)		((val) << PLLB_DIV_INT_SHIFT)
+#define PLLB_DIV_FRAC(val)		((val) << PLLB_DIV_FRAC_SHIFT)
+
+#define SYS_CTRL_CKCTRL_PCI_DIV_BIT	0
+#define SYS_CTRL_CKCTRL_SLOW_BIT	8
+
+#define SYS_CTRL_UART2_DEQ_EN		0
+#define SYS_CTRL_UART3_DEQ_EN		1
+#define SYS_CTRL_UART3_IQ_EN		2
+#define SYS_CTRL_UART4_IQ_EN		3
+#define SYS_CTRL_UART4_NOT_PCI_MODE	4
+
+#define SYS_CTRL_PCI_CTRL1_PCI_STATIC_RQ_BIT	11
+
+#define PLLA_REFDIV_MASK		0x3F
+#define PLLA_REFDIV_SHIFT		8
+#define PLLA_OUTDIV_MASK		0x7
+#define PLLA_OUTDIV_SHIFT		4
+
+/* bit numbers of clock control register */
+#define SYS_CTRL_CLK_COPRO		0
+#define SYS_CTRL_CLK_DMA		1
+#define SYS_CTRL_CLK_CIPHER		2
+#define SYS_CTRL_CLK_SD			3
+#define SYS_CTRL_CLK_SATA		4
+#define SYS_CTRL_CLK_I2S		5
+#define SYS_CTRL_CLK_USBHS		6
+#define SYS_CTRL_CLK_MACA		7
+#define SYS_CTRL_CLK_MAC		SYS_CTRL_CLK_MACA
+#define SYS_CTRL_CLK_PCIEA		8
+#define SYS_CTRL_CLK_STATIC		9
+#define SYS_CTRL_CLK_MACB		10
+#define SYS_CTRL_CLK_PCIEB		11
+#define SYS_CTRL_CLK_REF600		12
+#define SYS_CTRL_CLK_USBDEV		13
+#define SYS_CTRL_CLK_DDR		14
+#define SYS_CTRL_CLK_DDRPHY		15
+#define SYS_CTRL_CLK_DDRCK		16
+
+
+/* bit numbers of reset control register */
+#define SYS_CTRL_RST_SCU		0
+#define SYS_CTRL_RST_COPRO		1
+#define SYS_CTRL_RST_ARM0		2
+#define SYS_CTRL_RST_ARM1		3
+#define SYS_CTRL_RST_USBHS		4
+#define SYS_CTRL_RST_USBHSPHYA		5
+#define SYS_CTRL_RST_MACA		6
+#define SYS_CTRL_RST_MAC		SYS_CTRL_RST_MACA
+#define SYS_CTRL_RST_PCIEA		7
+#define SYS_CTRL_RST_SGDMA		8
+#define SYS_CTRL_RST_CIPHER		9
+#define SYS_CTRL_RST_DDR		10
+#define SYS_CTRL_RST_SATA		11
+#define SYS_CTRL_RST_SATA_LINK		12
+#define SYS_CTRL_RST_SATA_PHY		13
+#define SYS_CTRL_RST_PCIEPHY		14
+#define SYS_CTRL_RST_STATIC		15
+#define SYS_CTRL_RST_GPIO		16
+#define SYS_CTRL_RST_UART1		17
+#define SYS_CTRL_RST_UART2		18
+#define SYS_CTRL_RST_MISC		19
+#define SYS_CTRL_RST_I2S		20
+#define SYS_CTRL_RST_SD			21
+#define SYS_CTRL_RST_MACB		22
+#define SYS_CTRL_RST_PCIEB		23
+#define SYS_CTRL_RST_VIDEO		24
+#define SYS_CTRL_RST_DDR_PHY		25
+#define SYS_CTRL_RST_USBHSPHYB		26
+#define SYS_CTRL_RST_USBDEV		27
+#define SYS_CTRL_RST_ARMDBG		29
+#define SYS_CTRL_RST_PLLA		30
+#define SYS_CTRL_RST_PLLB		31
+
+#endif
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/iomap.h
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/iomap.h
@@ -0,0 +1,33 @@
+#ifndef __MACH_OXNAS_IOMAP_H
+#define __MACH_OXNAS_IOMAP_H
+
+#include <linux/sizes.h>
+
+#define OXNAS_UART1_BASE	0x44200000
+#define OXNAS_UART1_SIZE	SZ_32
+#define OXNAS_UART1_BASE_VA	0xF0000000
+
+#define OXNAS_UART2_BASE	0x44300000
+#define OXNAS_UART2_SIZE	SZ_32
+
+#define OXNAS_PERCPU_BASE	0x47000000
+#define OXNAS_PERCPU_SIZE	SZ_8K
+#define OXNAS_PERCPU_BASE_VA	0xF0002000
+
+#define OXNAS_SYSCRTL_BASE	0x44E00000
+#define OXNAS_SYSCRTL_SIZE	SZ_4K
+#define OXNAS_SYSCRTL_BASE_VA	0xF0004000
+
+#define OXNAS_SECCRTL_BASE	0x44F00000
+#define OXNAS_SECCRTL_SIZE	SZ_4K
+#define OXNAS_SECCRTL_BASE_VA	0xF0005000
+
+#define OXNAS_RPSA_BASE		0x44400000
+#define OXNAS_RPSA_SIZE		SZ_4K
+#define OXNAS_RPSA_BASE_VA	0xF0006000
+
+#define OXNAS_RPSC_BASE		0x44500000
+#define OXNAS_RPSC_SIZE		SZ_4K
+#define OXNAS_RPSC_BASE_VA	0xF0007000
+
+#endif
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/irqs.h
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/irqs.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#define IRQ_SOFT	1
+#define NR_IRQS		160
+
+#endif
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/smp.h
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/smp.h
@@ -0,0 +1,34 @@
+/*
+ * smp.h
+ *
+ *  Created on: Sep 24, 2013
+ *      Author: mahaijun
+ */
+
+#ifndef _NAS782X_SMP_H_
+#define _NAS782X_SMP_H_
+
+#include <mach/hardware.h>
+
+extern void ox820_secondary_startup(void);
+extern void ox820_cpu_die(unsigned int cpu);
+
+static inline void write_pen_release(int val)
+{
+	writel(val, HOLDINGPEN_CPU);
+}
+
+static inline int read_pen_release(void)
+{
+	return readl(HOLDINGPEN_CPU);
+}
+
+extern struct smp_operations ox820_smp_ops;
+
+extern unsigned char ox820_fiq_start, ox820_fiq_end;
+extern void v6_dma_map_area(const void *, size_t, int);
+extern void v6_dma_unmap_area(const void *, size_t, int);
+extern void v6_dma_flush_range(const void *, const void *);
+extern void v6_flush_kern_dcache_area(void *, size_t);
+
+#endif /* _NAS782X_SMP_H_ */
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/timex.h
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/timex.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+#define CLOCK_TICK_RATE		6250000
+
+#endif
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/uncompress.h
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/uncompress.h
@@ -0,0 +1,32 @@
+/* linux/include/asm-arm/arch-oxnas/uncompress.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#define OXNAS_UART1_BASE 0x44200000
+
+static inline void putc(int c)
+{
+	static volatile unsigned char *uart =
+		(volatile unsigned char *)OXNAS_UART1_BASE;
+
+	while (!(uart[5] & 0x20)) {	/* LSR reg THR empty bit */
+		barrier();
+	}
+	uart[0] = c;			/* THR register */
+}
+
+static inline void flush(void)
+{
+}
+
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/utils.h
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/utils.h
@@ -0,0 +1,34 @@
+#ifndef _NAS782X_UTILS_H
+#define _NAS782X_UTILS_H
+
+#include <linux/io.h>
+#include <mach/hardware.h>
+
+static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
+{
+	u32 val = readl_relaxed(p);
+
+	val &= ~mask;
+	writel_relaxed(val, p);
+}
+
+static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
+{
+	u32 val = readl_relaxed(p);
+
+	val |= mask;
+	writel_relaxed(val, p);
+}
+
+static inline void oxnas_register_value_mask(void __iomem *p,
+					     unsigned mask, unsigned new_value)
+{
+	/* TODO sanity check mask & new_value = new_value */
+	u32 val = readl_relaxed(p);
+
+	val &= ~mask;
+	val |= new_value;
+	writel_relaxed(val, p);
+}
+
+#endif /* _NAS782X_UTILS_H */
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/mach-ox820.c
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/mach-ox820.c
@@ -0,0 +1,284 @@
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/bug.h>
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/stmmac.h>
+#include <linux/slab.h>
+#include <linux/gfp.h>
+#include <linux/reset.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+#include <asm/mach/arch.h>
+#include <asm/page.h>
+#include <mach/iomap.h>
+#include <mach/hardware.h>
+#include <mach/utils.h>
+#include <mach/smp.h>
+
+static struct map_desc ox820_io_desc[] __initdata = {
+	{
+		.virtual = (unsigned long)OXNAS_PERCPU_BASE_VA,
+		.pfn = __phys_to_pfn(OXNAS_PERCPU_BASE),
+		.length = OXNAS_PERCPU_SIZE,
+		.type = MT_DEVICE,
+	},
+	{
+		.virtual = (unsigned long)OXNAS_SYSCRTL_BASE_VA,
+		.pfn = __phys_to_pfn(OXNAS_SYSCRTL_BASE),
+		.length = OXNAS_SYSCRTL_SIZE,
+		.type = MT_DEVICE,
+	},
+	{
+		.virtual = (unsigned long)OXNAS_SECCRTL_BASE_VA,
+		.pfn = __phys_to_pfn(OXNAS_SECCRTL_BASE),
+		.length = OXNAS_SECCRTL_SIZE,
+		.type = MT_DEVICE,
+	},
+	{
+		.virtual = (unsigned long)OXNAS_RPSA_BASE_VA,
+		.pfn = __phys_to_pfn(OXNAS_RPSA_BASE),
+		.length = OXNAS_RPSA_SIZE,
+		.type = MT_DEVICE,
+	},
+	{
+		.virtual = (unsigned long)OXNAS_RPSC_BASE_VA,
+		.pfn = __phys_to_pfn(OXNAS_RPSC_BASE),
+		.length = OXNAS_RPSC_SIZE,
+		.type = MT_DEVICE,
+	},
+};
+
+void __init ox820_map_common_io(void)
+{
+	debug_ll_io_init();
+	iotable_init(ox820_io_desc, ARRAY_SIZE(ox820_io_desc));
+}
+
+struct plat_gmac_data {
+	struct plat_stmmacenet_data stmmac;
+	struct clk *clk;
+};
+
+void *ox820_gmac_setup(struct platform_device *pdev)
+{
+	struct plat_gmac_data *pdata = pdev->dev.platform_data;
+
+	pdata->clk = clk_get(&pdev->dev, "gmac");
+	return (void *) pdata->clk;
+};
+
+int ox820_gmac_init(struct platform_device *pdev, void *priv)
+{
+	int ret;
+	unsigned value;
+
+	ret = device_reset(&pdev->dev);
+	if (ret)
+		return ret;
+
+	if (IS_ERR(priv))
+		return PTR_ERR(priv);
+	clk_prepare_enable(priv);
+
+	value = readl(SYS_CTRL_GMAC_CTRL);
+
+	/* Enable GMII_GTXCLK to follow GMII_REFCLK, required for gigabit PHY */
+	value |= BIT(SYS_CTRL_GMAC_CKEN_GTX);
+	/* Use simple mux for 25/125 Mhz clock switching */
+	value |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX);
+	/* set auto switch tx clock source */
+	value |= BIT(SYS_CTRL_GMAC_AUTO_TX_SOURCE);
+	/* enable tx & rx vardelay */
+	value |= BIT(SYS_CTRL_GMAC_CKEN_TX_OUT);
+	value |= BIT(SYS_CTRL_GMAC_CKEN_TXN_OUT);
+	value |= BIT(SYS_CTRL_GMAC_CKEN_TX_IN);
+	value |= BIT(SYS_CTRL_GMAC_CKEN_RX_OUT);
+	value |= BIT(SYS_CTRL_GMAC_CKEN_RXN_OUT);
+	value |= BIT(SYS_CTRL_GMAC_CKEN_RX_IN);
+	writel(value, SYS_CTRL_GMAC_CTRL);
+
+	/* set tx & rx vardelay */
+	value = 0;
+	value |= SYS_CTRL_GMAC_TX_VARDELAY(4);
+	value |= SYS_CTRL_GMAC_TXN_VARDELAY(2);
+	value |= SYS_CTRL_GMAC_RX_VARDELAY(10);
+	value |= SYS_CTRL_GMAC_RXN_VARDELAY(8);
+	writel(value, SYS_CTRL_GMAC_DELAY_CTRL);
+
+	return 0;
+}
+
+void ox820_gmac_exit(struct platform_device *pdev, void *priv)
+{
+	struct reset_control *rstc;
+
+	clk_disable_unprepare(priv);
+	clk_put(priv);
+
+	rstc = reset_control_get(&pdev->dev, NULL);
+	if (!IS_ERR(rstc)) {
+		reset_control_assert(rstc);
+		reset_control_put(rstc);
+	}
+}
+
+static int __init ox820_ether_init(void)
+{
+	struct device_node *node;
+	struct platform_device *pdev;
+	struct plat_gmac_data *pdata;
+
+	node = of_find_compatible_node(NULL, NULL, "plxtech,nas782x-gmac");
+	if (!node)
+		return -ENOENT;
+
+	pdev = of_find_device_by_node(node);
+	of_node_put(node);
+
+	if (!pdev)
+		return -EINVAL;
+
+	pdata = kzalloc(sizeof(struct plat_gmac_data), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	pdata->stmmac.setup = ox820_gmac_setup;
+	pdata->stmmac.init = ox820_gmac_init;
+	pdata->stmmac.exit = ox820_gmac_exit;
+	pdev->dev.platform_data = pdata;
+
+	return 0;
+}
+
+static void __init ox820_dt_init(void)
+{
+	int ret;
+
+	ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
+					NULL);
+
+	if (ret) {
+		pr_err("of_platform_populate failed: %d\n", ret);
+		BUG();
+	}
+
+	ret = ox820_ether_init();
+
+	if (ret)
+		pr_info("ox820_ether_init failed: %d\n", ret);
+}
+
+static void __init ox820_timer_init(void)
+{
+	of_clk_init(NULL);
+	clocksource_of_init();
+}
+
+void ox820_init_early(void)
+{
+
+}
+
+void ox820_assert_system_reset(enum reboot_mode mode, const char *cmd)
+{
+	u32 value;
+
+/* Assert reset to cores as per power on defaults
+ * Don't touch the DDR interface as things will come to an impromptu stop
+ * NB Possibly should be asserting reset for PLLB, but there are timing
+ *    concerns here according to the docs */
+	value = BIT(SYS_CTRL_RST_COPRO)		|
+		BIT(SYS_CTRL_RST_USBHS)		|
+		BIT(SYS_CTRL_RST_USBHSPHYA)	|
+		BIT(SYS_CTRL_RST_MACA)		|
+		BIT(SYS_CTRL_RST_PCIEA)		|
+		BIT(SYS_CTRL_RST_SGDMA)		|
+		BIT(SYS_CTRL_RST_CIPHER)	|
+		BIT(SYS_CTRL_RST_SATA)		|
+		BIT(SYS_CTRL_RST_SATA_LINK)	|
+		BIT(SYS_CTRL_RST_SATA_PHY)	|
+		BIT(SYS_CTRL_RST_PCIEPHY)	|
+		BIT(SYS_CTRL_RST_STATIC)	|
+		BIT(SYS_CTRL_RST_UART1)		|
+		BIT(SYS_CTRL_RST_UART2)		|
+		BIT(SYS_CTRL_RST_MISC)		|
+		BIT(SYS_CTRL_RST_I2S)		|
+		BIT(SYS_CTRL_RST_SD)		|
+		BIT(SYS_CTRL_RST_MACB)		|
+		BIT(SYS_CTRL_RST_PCIEB)		|
+		BIT(SYS_CTRL_RST_VIDEO)		|
+		BIT(SYS_CTRL_RST_USBHSPHYB)	|
+		BIT(SYS_CTRL_RST_USBDEV);
+
+	writel(value, SYS_CTRL_RST_SET_CTRL);
+
+	/* Release reset to cores as per power on defaults */
+	writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL);
+
+	/* Disable clocks to cores as per power-on defaults - must leave DDR
+	 * related clocks enabled otherwise we'll stop rather abruptly. */
+	value =
+		BIT(SYS_CTRL_CLK_COPRO)		|
+		BIT(SYS_CTRL_CLK_DMA)		|
+		BIT(SYS_CTRL_CLK_CIPHER)	|
+		BIT(SYS_CTRL_CLK_SD)		|
+		BIT(SYS_CTRL_CLK_SATA)		|
+		BIT(SYS_CTRL_CLK_I2S)		|
+		BIT(SYS_CTRL_CLK_USBHS)		|
+		BIT(SYS_CTRL_CLK_MAC)		|
+		BIT(SYS_CTRL_CLK_PCIEA)		|
+		BIT(SYS_CTRL_CLK_STATIC)	|
+		BIT(SYS_CTRL_CLK_MACB)		|
+		BIT(SYS_CTRL_CLK_PCIEB)		|
+		BIT(SYS_CTRL_CLK_REF600)	|
+		BIT(SYS_CTRL_CLK_USBDEV);
+
+	writel(value, SYS_CTRL_CLK_CLR_CTRL);
+
+	/* Enable clocks to cores as per power-on defaults */
+
+	/* Set sys-control pin mux'ing as per power-on defaults */
+	writel(0, SYS_CTRL_SECONDARY_SEL);
+	writel(0, SYS_CTRL_TERTIARY_SEL);
+	writel(0, SYS_CTRL_QUATERNARY_SEL);
+	writel(0, SYS_CTRL_DEBUG_SEL);
+	writel(0, SYS_CTRL_ALTERNATIVE_SEL);
+	writel(0, SYS_CTRL_PULLUP_SEL);
+
+	writel(0, SYS_CTRL_SECONDARY_SEL);
+	writel(0, SYS_CTRL_TERTIARY_SEL);
+	writel(0, SYS_CTRL_QUATERNARY_SEL);
+	writel(0, SYS_CTRL_DEBUG_SEL);
+	writel(0, SYS_CTRL_ALTERNATIVE_SEL);
+	writel(0, SYS_CTRL_PULLUP_SEL);
+
+	/* No need to save any state, as the ROM loader can determine whether
+	 * reset is due to power cycling or programatic action, just hit the
+	 * (self-clearing) CPU reset bit of the block reset register */
+	value =
+		BIT(SYS_CTRL_RST_SCU) |
+		BIT(SYS_CTRL_RST_ARM0) |
+		BIT(SYS_CTRL_RST_ARM1);
+
+	writel(value, SYS_CTRL_RST_SET_CTRL);
+}
+
+static const char * const ox820_dt_board_compat[] = {
+	"plxtech,nas7820",
+	"plxtech,nas7821",
+	"plxtech,nas7825",
+	NULL
+};
+
+DT_MACHINE_START(OX820_DT, "PLXTECH NAS782X SoC (Flattened Device Tree)")
+	.map_io		= ox820_map_common_io,
+	.smp		= smp_ops(ox820_smp_ops),
+	.init_early	= ox820_init_early,
+	.init_time	= ox820_timer_init,
+	.init_machine	= ox820_dt_init,
+	.restart	= ox820_assert_system_reset,
+	.dt_compat	= ox820_dt_board_compat,
+MACHINE_END
--- a/target/linux/oxnas/files/arch/arm/mach-oxnas/platsmp.c
+++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/platsmp.c
@@ -0,0 +1,315 @@
+/*
+ *  arch/arm/mach-ox820/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/cache.h>
+#include <asm/cacheflush.h>
+#include <asm/smp_scu.h>
+#include <asm/tlbflush.h>
+#include <asm/cputype.h>
+#include <linux/delay.h>
+#include <asm/fiq.h>
+
+#include <linux/irqchip/arm-gic.h>
+#include <mach/iomap.h>
+#include <mach/smp.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+#ifdef CONFIG_DMA_CACHE_FIQ_BROADCAST
+
+#define FIQ_GENERATE		0x00000002
+#define OXNAS_MAP_AREA		0x01000000
+#define OXNAS_UNMAP_AREA	0x02000000
+#define OXNAS_FLUSH_RANGE	0x03000000
+
+struct fiq_req {
+	union {
+		struct {
+			const void *addr;
+			size_t size;
+		} map;
+		struct {
+			const void *addr;
+			size_t size;
+		} unmap;
+		struct {
+			const void *start;
+			const void *end;
+		} flush;
+	};
+	volatile uint flags;
+	void __iomem *reg;
+} ____cacheline_aligned;
+
+static struct fiq_handler fh = {
+	.name = "oxnas-fiq"
+};
+
+DEFINE_PER_CPU(struct fiq_req, fiq_data);
+
+static inline void __cpuinit ox820_set_fiq_regs(unsigned int cpu)
+{
+	struct pt_regs FIQ_regs;
+	struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu);
+
+	FIQ_regs.ARM_r8 = 0;
+	FIQ_regs.ARM_ip = (unsigned int)fiq_req;
+	FIQ_regs.ARM_sp = (int)(cpu ? RPSC_IRQ_SOFT : RPSA_IRQ_SOFT);
+	fiq_req->reg = cpu ? RPSC_IRQ_SOFT : RPSA_IRQ_SOFT;
+
+	set_fiq_regs(&FIQ_regs);
+}
+
+static void __init ox820_init_fiq(void)
+{
+	void *fiqhandler_start;
+	unsigned int fiqhandler_length;
+	int ret;
+
+	fiqhandler_start = &ox820_fiq_start;
+	fiqhandler_length = &ox820_fiq_end - &ox820_fiq_start;
+
+	ret = claim_fiq(&fh);
+
+	if (ret)
+		return;
+
+	set_fiq_handler(fiqhandler_start, fiqhandler_length);
+
+	writel(IRQ_SOFT, RPSA_FIQ_IRQ_TO_FIQ);
+	writel(1, RPSA_FIQ_ENABLE);
+	writel(IRQ_SOFT, RPSC_FIQ_IRQ_TO_FIQ);
+	writel(1, RPSC_FIQ_ENABLE);
+}
+
+void fiq_dma_map_area(const void *addr, size_t size, int dir)
+{
+	unsigned long flags;
+	struct fiq_req *req;
+
+	raw_local_irq_save(flags);
+	/* currently, not possible to take cpu0 down, so only check cpu1 */
+	if (!cpu_online(1)) {
+		raw_local_irq_restore(flags);
+		v6_dma_map_area(addr, size, dir);
+		return;
+	}
+
+	req = this_cpu_ptr(&fiq_data);
+	req->map.addr = addr;
+	req->map.size = size;
+	req->flags = dir | OXNAS_MAP_AREA;
+	smp_mb();
+
+	writel_relaxed(FIQ_GENERATE, req->reg);
+
+	v6_dma_map_area(addr, size, dir);
+	while (req->flags)
+		barrier();
+
+	raw_local_irq_restore(flags);
+}
+
+void fiq_dma_unmap_area(const void *addr, size_t size, int dir)
+{
+	unsigned long flags;
+	struct fiq_req *req;
+
+	raw_local_irq_save(flags);
+	/* currently, not possible to take cpu0 down, so only check cpu1 */
+	if (!cpu_online(1)) {
+		raw_local_irq_restore(flags);
+		v6_dma_unmap_area(addr, size, dir);
+		return;
+	}
+
+	req = this_cpu_ptr(&fiq_data);
+	req->unmap.addr = addr;
+	req->unmap.size = size;
+	req->flags = dir | OXNAS_UNMAP_AREA;
+	smp_mb();
+
+	writel_relaxed(FIQ_GENERATE, req->reg);
+
+	v6_dma_unmap_area(addr, size, dir);
+	while (req->flags)
+		barrier();
+
+	raw_local_irq_restore(flags);
+}
+
+void fiq_dma_flush_range(const void *start, const void *end)
+{
+	unsigned long flags;
+	struct fiq_req *req;
+
+	raw_local_irq_save(flags);
+	/* currently, not possible to take cpu0 down, so only check cpu1 */
+	if (!cpu_online(1)) {
+		raw_local_irq_restore(flags);
+		v6_dma_flush_range(start, end);
+		return;
+	}
+
+	req = this_cpu_ptr(&fiq_data);
+
+	req->flush.start = start;
+	req->flush.end = end;
+	req->flags = OXNAS_FLUSH_RANGE;
+	smp_mb();
+
+	writel_relaxed(FIQ_GENERATE, req->reg);
+
+	v6_dma_flush_range(start, end);
+
+	while (req->flags)
+		barrier();
+
+	raw_local_irq_restore(flags);
+}
+
+void fiq_flush_kern_dcache_area(void *addr, size_t size)
+{
+	fiq_dma_flush_range(addr, addr + size);
+}
+#else
+
+#define ox820_set_fiq_regs(cpu)	do {} while (0) /* nothing */
+#define ox820_init_fiq()	do {} while (0) /* nothing */
+
+#endif /* DMA_CACHE_FIQ_BROADCAST */
+
+static DEFINE_SPINLOCK(boot_lock);
+
+void __cpuinit ox820_secondary_init(unsigned int cpu)
+{
+	/*
+	 * Setup Secondary Core FIQ regs
+	 */
+	ox820_set_fiq_regs(1);
+
+	/*
+	 * let the primary processor know we're out of the
+	 * pen, then head off into the C entry point
+	 */
+	write_pen_release(-1);
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+int __cpuinit ox820_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long timeout;
+
+	/*
+	 * Set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+	spin_lock(&boot_lock);
+
+	/*
+	 * This is really belt and braces; we hold unintended secondary
+	 * CPUs in the holding pen until we're ready for them.  However,
+	 * since we haven't sent them a soft interrupt, they shouldn't
+	 * be there.
+	 */
+	write_pen_release(cpu);
+
+	writel(1, IOMEM(OXNAS_GICN_BASE_VA(cpu) + GIC_CPU_CTRL));
+
+	/*
+	 * Send the secondary CPU a soft interrupt, thereby causing
+	 * the boot monitor to read the system wide flags register,
+	 * and branch to the address found there.
+	 */
+
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+	timeout = jiffies + (1 * HZ);
+	while (time_before(jiffies, timeout)) {
+		smp_rmb();
+		if (read_pen_release() == -1)
+			break;
+
+		udelay(10);
+	}
+
+	/*
+	 * now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return read_pen_release() != -1 ? -ENOSYS : 0;
+}
+
+void *scu_base_addr(void)
+{
+	return IOMEM(OXNAS_SCU_BASE_VA);
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+static void __init ox820_smp_init_cpus(void)
+{
+	void __iomem *scu_base = scu_base_addr();
+	unsigned int i, ncores;
+
+	ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+
+	/* sanity check */
+	if (ncores > nr_cpu_ids) {
+		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+			ncores, nr_cpu_ids);
+		ncores = nr_cpu_ids;
+	}
+
+	for (i = 0; i < ncores; i++)
+		set_cpu_possible(i, true);
+}
+
+static void __init ox820_smp_prepare_cpus(unsigned int max_cpus)
+{
+
+	scu_enable(scu_base_addr());
+
+	/*
+	 * Write the address of secondary startup into the
+	 * system-wide flags register. The BootMonitor waits
+	 * until it receives a soft interrupt, and then the
+	 * secondary CPU branches to this address.
+	 */
+	writel(virt_to_phys(ox820_secondary_startup),
+					HOLDINGPEN_LOCATION);
+	ox820_init_fiq();
+
+	ox820_set_fiq_regs(0);
+}
+
+struct smp_operations ox820_smp_ops __initdata = {
+	.smp_init_cpus		= ox820_smp_init_cpus,
+	.smp_prepare_cpus	= ox820_smp_prepare_cpus,
+	.smp_secondary_init	= ox820_secondary_init,
+	.smp_boot_secondary	= ox820_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+	.cpu_die		= ox820_cpu_die,
+#endif
+};
--- a/target/linux/oxnas/files/drivers/ata/sata_oxnas.c
+++ b/target/linux/oxnas/files/drivers/ata/sata_oxnas.c
--- a/target/linux/oxnas/files/drivers/clk/clk-oxnas.c
+++ b/target/linux/oxnas/files/drivers/clk/clk-oxnas.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) 2010 Broadcom
+ * Copyright (C) 2012 Stephen Warren
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/delay.h>
+#include <linux/stringify.h>
+#include <linux/reset.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/utils.h>
+
+#define MHZ (1000 * 1000)
+
+static unsigned long plla_clk_recalc_rate(struct clk_hw *hw,
+	unsigned long parent_rate)
+{
+	unsigned long fin = parent_rate;
+	unsigned long pll0;
+	unsigned long fbdiv, refdiv, outdiv;
+
+	pll0 = readl_relaxed(SYS_CTRL_PLLA_CTRL0);
+	refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK;
+	refdiv += 1;
+	outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK;
+	outdiv += 1;
+	fbdiv = readl_relaxed(SYS_CTRL_PLLA_CTRL1);
+
+	/* seems we will not be here when pll is bypassed, so ignore this
+	 * case */
+
+	return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ;
+}
+
+static const char *pll_clk_parents[] = {
+	"oscillator",
+};
+
+static struct clk_ops plla_ops = {
+	.recalc_rate = plla_clk_recalc_rate,
+};
+
+static struct clk_init_data clk_plla_init = {
+	.name = "plla",
+	.ops = &plla_ops,
+	.parent_names = pll_clk_parents,
+	.num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_hw plla_hw = {
+	.init = &clk_plla_init,
+};
+
+static struct device_node *node_pllb;
+
+int pllb_clk_enable(struct clk_hw *hw)
+{
+	struct reset_control *rstc;
+
+	rstc = of_reset_control_get(node_pllb, NULL);
+	if (IS_ERR(rstc))
+		return PTR_ERR(rstc);
+
+	/* put PLL into bypass */
+	oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
+	wmb();
+	udelay(10);
+	reset_control_assert(rstc);
+	udelay(10);
+	/* set PLL B control information */
+	writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV),
+				SEC_CTRL_PLLB_CTRL0);
+	reset_control_deassert(rstc);
+	reset_control_put(rstc);
+	udelay(100);
+	oxnas_register_clear_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
+
+	return 0;
+}
+
+void pllb_clk_disable(struct clk_hw *hw)
+{
+	struct reset_control *rstc;
+
+	/* put PLL into bypass */
+	oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
+	wmb();
+	udelay(10);
+
+	rstc = of_reset_control_get(node_pllb, NULL);
+	if (!IS_ERR(rstc))
+		reset_control_assert(rstc);
+}
+
+static struct clk_ops pllb_ops = {
+	.enable = pllb_clk_enable,
+	.disable = pllb_clk_disable,
+};
+
+static struct clk_init_data clk_pllb_init = {
+	.name = "pllb",
+	.ops = &pllb_ops,
+	.parent_names = pll_clk_parents,
+	.num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_hw pllb_hw = {
+	.init = &clk_pllb_init,
+};
+
+/* standard gate clock */
+struct clk_std {
+	struct clk_hw hw;
+	signed char bit;
+};
+
+#define NUM_STD_CLKS 17
+#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
+
+static int std_clk_is_enabled(struct clk_hw *hw)
+{
+	struct clk_std *std = to_stdclk(hw);
+
+	return readl_relaxed(SYSCTRL_CLK_STAT) & BIT(std->bit);
+}
+
+static int std_clk_enable(struct clk_hw *hw)
+{
+	struct clk_std *std = to_stdclk(hw);
+
+	writel(BIT(std->bit), SYS_CTRL_CLK_SET_CTRL);
+	return 0;
+}
+
+static void std_clk_disable(struct clk_hw *hw)
+{
+	struct clk_std *std = to_stdclk(hw);
+
+	writel(BIT(std->bit), SYS_CTRL_CLK_CLR_CTRL);
+}
+
+static struct clk_ops std_clk_ops = {
+	.enable = std_clk_enable,
+	.disable = std_clk_disable,
+	.is_enabled = std_clk_is_enabled,
+};
+
+static const char *std_clk_parents[] = {
+	"oscillator",
+};
+
+static const char *eth_parents[] = {
+	"gmacclk",
+};
+
+#define DECLARE_STD_CLKP(__clk, __bit, __parent)	\
+static struct clk_init_data clk_##__clk##_init = {	\
+	.name = __stringify(__clk),			\
+	.ops = &std_clk_ops,				\
+	.parent_names = __parent,		\
+	.num_parents = ARRAY_SIZE(__parent),	\
+};							\
+							\
+static struct clk_std clk_##__clk = {			\
+	.bit = __bit,					\
+	.hw = {						\
+		.init = &clk_##__clk##_init,		\
+	},						\
+}
+
+#define DECLARE_STD_CLK(__clk, __bit) DECLARE_STD_CLKP(__clk, __bit, \
+							std_clk_parents)
+
+DECLARE_STD_CLK(leon, 0);
+DECLARE_STD_CLK(dma_sgdma, 1);
+DECLARE_STD_CLK(cipher, 2);
+DECLARE_STD_CLK(sd, 3);
+DECLARE_STD_CLK(sata, 4);
+DECLARE_STD_CLK(audio, 5);
+DECLARE_STD_CLK(usbmph, 6);
+DECLARE_STD_CLKP(etha, 7, eth_parents);
+DECLARE_STD_CLK(pciea, 8);
+DECLARE_STD_CLK(static, 9);
+DECLARE_STD_CLK(ethb, 10);
+DECLARE_STD_CLK(pcieb, 11);
+DECLARE_STD_CLK(ref600, 12);
+DECLARE_STD_CLK(usbdev, 13);
+
+struct clk_hw *std_clk_hw_tbl[] = {
+	&clk_leon.hw,
+	&clk_dma_sgdma.hw,
+	&clk_cipher.hw,
+	&clk_sd.hw,
+	&clk_sata.hw,
+	&clk_audio.hw,
+	&clk_usbmph.hw,
+	&clk_etha.hw,
+	&clk_pciea.hw,
+	&clk_static.hw,
+	&clk_ethb.hw,
+	&clk_pcieb.hw,
+	&clk_ref600.hw,
+	&clk_usbdev.hw,
+};
+
+struct clk *std_clk_tbl[ARRAY_SIZE(std_clk_hw_tbl)];
+
+static struct clk_onecell_data std_clk_data;
+
+void __init oxnas_init_stdclk(struct device_node *np)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(std_clk_hw_tbl); i++) {
+		std_clk_tbl[i] = clk_register(NULL, std_clk_hw_tbl[i]);
+		BUG_ON(IS_ERR(std_clk_tbl[i]));
+	}
+	std_clk_data.clks = std_clk_tbl;
+	std_clk_data.clk_num = ARRAY_SIZE(std_clk_tbl);
+	of_clk_add_provider(np, of_clk_src_onecell_get, &std_clk_data);
+}
+CLK_OF_DECLARE(oxnas_pllstd, "plxtech,nas782x-stdclk", oxnas_init_stdclk);
+
+void __init oxnas_init_plla(struct device_node *np)
+{
+	struct clk *clk;
+
+	clk = clk_register(NULL, &plla_hw);
+	BUG_ON(IS_ERR(clk));
+	/* mark it as enabled */
+	clk_prepare_enable(clk);
+	of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla);
+
+void __init oxnas_init_pllb(struct device_node *np)
+{
+	struct clk *clk;
+
+	node_pllb = np;
+
+	clk = clk_register(NULL, &pllb_hw);
+	BUG_ON(IS_ERR(clk));
+	of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb);
--- a/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c
+++ b/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c
@@ -0,0 +1,96 @@
+/*
+ * arch/arm/mach-ox820/rps-time.c
+ *
+ * Copyright (C) 2009 Oxford Semiconductor Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/sched_clock.h>
+#include <mach/hardware.h>
+
+enum {
+	TIMER_LOAD = 0,
+	TIMER_CURR = 4,
+	TIMER_CTRL = 8,
+	TIMER_CLRINT = 0xC,
+
+	TIMER_BITS = 24,
+
+	TIMER_MAX_VAL = (1 << TIMER_BITS) - 1,
+
+	TIMER_PERIODIC = (1 << 6),
+	TIMER_ENABLE = (1 << 7),
+
+	TIMER_DIV1  = (0 << 2),
+	TIMER_DIV16  = (1 << 2),
+	TIMER_DIV256  = (2 << 2),
+
+	TIMER1_OFFSET = 0,
+	TIMER2_OFFSET = 0x20,
+
+};
+
+static u64 notrace rps_read_sched_clock(void)
+{
+	return ~readl_relaxed(RPSA_TIMER2_VAL);
+}
+
+static void __init rps_clocksource_init(void __iomem *base, ulong ref_rate)
+{
+	int ret;
+	ulong clock_rate;
+	/* use prescale 16 */
+	clock_rate = ref_rate / 16;
+
+	iowrite32(TIMER_MAX_VAL, base + TIMER_LOAD);
+	iowrite32(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16,
+			base + TIMER_CTRL);
+
+	ret = clocksource_mmio_init(base + TIMER_CURR, "rps_clocksource_timer",
+					clock_rate, 250, TIMER_BITS,
+					clocksource_mmio_readl_down);
+	if (ret)
+		panic("can't register clocksource\n");
+
+	sched_clock_register(rps_read_sched_clock, TIMER_BITS, clock_rate);
+}
+
+static void __init rps_timer_init(struct device_node *np)
+{
+	struct clk *refclk;
+	unsigned long ref_rate;
+	void __iomem *base;
+
+	refclk = of_clk_get(np, 0);
+
+	if (IS_ERR(refclk) || clk_prepare_enable(refclk))
+		panic("rps_timer_init: failed to get refclk\n");
+	ref_rate = clk_get_rate(refclk);
+
+	base = of_iomap(np, 0);
+	if (!base)
+		panic("rps_timer_init: failed to map io\n");
+
+	rps_clocksource_init(base + TIMER2_OFFSET, ref_rate);
+}
+
+CLOCKSOURCE_OF_DECLARE(nas782x, "plxtech,nas782x-rps-timer", rps_timer_init);
--- a/target/linux/oxnas/files/drivers/irqchip/irq-rps.c
+++ b/target/linux/oxnas/files/drivers/irqchip/irq-rps.c
@@ -0,0 +1,146 @@
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include "irqchip.h"
+
+struct rps_chip_data {
+	void __iomem *base;
+	struct irq_chip chip;
+	struct irq_domain *domain;
+} rps_data;
+
+enum {
+	RPS_IRQ_BASE = 64,
+	RPS_IRQ_COUNT = 32,
+	PRS_HWIRQ_BASE = 0,
+
+	RPS_STATUS = 0,
+	RPS_RAW_STATUS = 4,
+	RPS_UNMASK = 8,
+	RPS_MASK = 0xc,
+};
+
+/*
+ * Routines to acknowledge, disable and enable interrupts
+ */
+static void rps_mask_irq(struct irq_data *d)
+{
+	struct rps_chip_data *chip_data = irq_data_get_irq_chip_data(d);
+	u32 mask = BIT(d->hwirq);
+
+	iowrite32(mask, chip_data->base + RPS_MASK);
+}
+
+static void rps_unmask_irq(struct irq_data *d)
+{
+	struct rps_chip_data *chip_data = irq_data_get_irq_chip_data(d);
+	u32 mask = BIT(d->hwirq);
+
+	iowrite32(mask, chip_data->base + RPS_UNMASK);
+}
+
+static struct irq_chip rps_chip = {
+	.name			= "RPS",
+	.irq_mask		= rps_mask_irq,
+	.irq_unmask		= rps_unmask_irq,
+};
+
+static int rps_irq_domain_xlate(struct irq_domain *d,
+				struct device_node *controller,
+				const u32 *intspec, unsigned int intsize,
+				unsigned long *out_hwirq,
+				unsigned int *out_type)
+{
+	if (d->of_node != controller)
+		return -EINVAL;
+	if (intsize < 1)
+		return -EINVAL;
+
+	*out_hwirq = intspec[0];
+	/* Honestly I do not know the type */
+	*out_type = IRQ_TYPE_LEVEL_HIGH;
+
+	return 0;
+}
+
+static int rps_irq_domain_map(struct irq_domain *d, unsigned int irq,
+				irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(irq, &rps_chip, handle_level_irq);
+	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+	irq_set_chip_data(irq, d->host_data);
+	return 0;
+}
+
+const struct irq_domain_ops rps_irq_domain_ops = {
+	.map = rps_irq_domain_map,
+	.xlate = rps_irq_domain_xlate,
+};
+
+static void rps_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
+{
+	struct rps_chip_data *chip_data = irq_get_handler_data(irq);
+	struct irq_chip *chip = irq_get_chip(irq);
+	unsigned int cascade_irq, rps_irq;
+	u32 status;
+
+	chained_irq_enter(chip, desc);
+
+	status = ioread32(chip_data->base + RPS_STATUS);
+	rps_irq = __ffs(status);
+	cascade_irq = irq_find_mapping(chip_data->domain, rps_irq);
+
+	if (unlikely(rps_irq >= RPS_IRQ_COUNT))
+		handle_bad_irq(cascade_irq, desc);
+	else
+		generic_handle_irq(cascade_irq);
+
+	chained_irq_exit(chip, desc);
+}
+
+#ifdef CONFIG_OF
+int __init rps_of_init(struct device_node *node, struct device_node *parent)
+{
+	void __iomem *rps_base;
+	int irq_start = RPS_IRQ_BASE;
+	int irq_base;
+	int irq;
+
+	if (WARN_ON(!node))
+		return -ENODEV;
+
+	rps_base = of_iomap(node, 0);
+	WARN(!rps_base, "unable to map rps registers\n");
+	rps_data.base = rps_base;
+
+	irq_base = irq_alloc_descs(irq_start, 0, RPS_IRQ_COUNT, numa_node_id());
+	if (IS_ERR_VALUE(irq_base)) {
+		WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
+		     irq_start);
+		irq_base = irq_start;
+	}
+
+	rps_data.domain = irq_domain_add_legacy(node, RPS_IRQ_COUNT, irq_base,
+			PRS_HWIRQ_BASE, &rps_irq_domain_ops, &rps_data);
+
+	if (WARN_ON(!rps_data.domain))
+		return -ENOMEM;
+
+	if (parent) {
+		irq = irq_of_parse_and_map(node, 0);
+		if (irq_set_handler_data(irq, &rps_data) != 0)
+			BUG();
+		irq_set_chained_handler(irq, rps_handle_cascade_irq);
+	}
+	return 0;
+
+}
+
+IRQCHIP_DECLARE(nas782x, "plxtech,nas782x-rps", rps_of_init);
+#endif
--- a/target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c
+++ b/target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c
@@ -0,0 +1,102 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/mtd/nand.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <mach/utils.h>
+
+/* nand commands */
+#define NAND_CMD_ALE		BIT(18)
+#define NAND_CMD_CLE		BIT(19)
+#define NAND_CMD_CS		0
+#define NAND_CMD_RESET		0xff
+#define NAND_CMD		(NAND_CMD_CS | NAND_CMD_CLE)
+#define NAND_ADDR		(NAND_CMD_CS | NAND_CMD_ALE)
+#define NAND_DATA		(NAND_CMD_CS)
+
+static void oxnas_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		nandaddr &= ~(NAND_CMD | NAND_ADDR);
+		if (ctrl & NAND_CLE)
+			nandaddr |= NAND_CMD;
+		else if (ctrl & NAND_ALE)
+			nandaddr |= NAND_ADDR;
+		this->IO_ADDR_W = (void __iomem *) nandaddr;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, (void __iomem *) nandaddr);
+}
+
+static int oxnas_nand_probe(struct platform_device *pdev)
+{
+	/* enable clock and release static block reset */
+	struct clk *clk = of_clk_get(pdev->dev.of_node, 0);
+
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	clk_prepare_enable(clk);
+	device_reset(&pdev->dev);
+
+	return 0;
+}
+
+/* allow users to override the partition in DT using the cmdline */
+static const char * part_probes[] = { "cmdlinepart", "ofpart", NULL };
+
+static struct platform_nand_data oxnas_nand_data = {
+	.chip = {
+		.nr_chips		= 1,
+		.chip_delay		= 30,
+		.part_probe_types	= part_probes,
+	},
+	.ctrl = {
+		.probe		= oxnas_nand_probe,
+		.cmd_ctrl	= oxnas_cmd_ctrl,
+	}
+};
+
+/*
+ * Try to find the node inside the DT. If it is available attach out
+ * platform_nand_data
+ */
+static int __init oxnas_register_nand(void)
+{
+	struct device_node *node;
+	struct platform_device *pdev;
+
+	node = of_find_compatible_node(NULL, NULL, "plxtech,nand-nas782x");
+	if (!node)
+		return -ENOENT;
+	pdev = of_find_device_by_node(node);
+	if (!pdev)
+		return -EINVAL;
+	pdev->dev.platform_data = &oxnas_nand_data;
+	of_node_put(node);
+	return 0;
+}
+
+subsys_initcall(oxnas_register_nand);
+
+static const struct of_device_id oxnas_nand_ids[] = {
+	{ .compatible = "plxtech,nand-nas782x"},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, oxnas_nand_ids);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Ma Haijun");
+MODULE_DESCRIPTION("NAND glue for Oxnas platforms");
+MODULE_ALIAS("platform:oxnas_nand");
--- a/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c
+++ b/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c
@@ -0,0 +1,676 @@
+/*
+ * PCIe driver for PLX NAS782X SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/mbus.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <mach/iomap.h>
+#include <mach/hardware.h>
+#include <mach/utils.h>
+
+#define VERSION_ID_MAGIC		0x082510b5
+#define LINK_UP_TIMEOUT_SECONDS		1
+#define NUM_CONTROLLERS			1
+
+enum {
+	PCIE_DEVICE_TYPE_MASK = 0x0F,
+	PCIE_DEVICE_TYPE_ENDPOINT = 0,
+	PCIE_DEVICE_TYPE_LEGACY_ENDPOINT = 1,
+	PCIE_DEVICE_TYPE_ROOT = 4,
+
+	PCIE_LTSSM = BIT(4),
+	PCIE_READY_ENTR_L23 = BIT(9),
+	PCIE_LINK_UP = BIT(11),
+	PCIE_OBTRANS = BIT(12),
+};
+
+enum {
+	HCSL_BIAS_ON = BIT(0),
+	HCSL_PCIE_EN = BIT(1),
+	HCSL_PCIEA_EN = BIT(2),
+	HCSL_PCIEB_EN = BIT(3),
+};
+
+enum {
+	/* pcie phy reg offset */
+	PHY_ADDR = 0,
+	PHY_DATA = 4,
+	/* phy data reg bits */
+	READ_EN = BIT(16),
+	WRITE_EN = BIT(17),
+	CAP_DATA = BIT(18),
+};
+
+/* core config registers */
+enum {
+	PCI_CONFIG_VERSION_DEVICEID = 0,
+	PCI_CONFIG_COMMAND_STATUS = 4,
+};
+
+/* inbound config registers */
+enum {
+	IB_ADDR_XLATE_ENABLE = 0xFC,
+
+	/* bits */
+	ENABLE_IN_ADDR_TRANS = BIT(0),
+};
+
+/* outbound config registers, offset relative to PCIE_POM0_MEM_ADDR */
+enum {
+	PCIE_POM0_MEM_ADDR	= 0,
+	PCIE_POM1_MEM_ADDR	= 4,
+	PCIE_IN0_MEM_ADDR	= 8,
+	PCIE_IN1_MEM_ADDR	= 12,
+	PCIE_IN_IO_ADDR		= 16,
+	PCIE_IN_CFG0_ADDR	= 20,
+	PCIE_IN_CFG1_ADDR	= 24,
+	PCIE_IN_MSG_ADDR	= 28,
+	PCIE_IN0_MEM_LIMIT	= 32,
+	PCIE_IN1_MEM_LIMIT	= 36,
+	PCIE_IN_IO_LIMIT	= 40,
+	PCIE_IN_CFG0_LIMIT	= 44,
+	PCIE_IN_CFG1_LIMIT	= 48,
+	PCIE_IN_MSG_LIMIT	= 52,
+	PCIE_AHB_SLAVE_CTRL	= 56,
+
+	PCIE_SLAVE_BE_SHIFT	= 22,
+};
+
+#define ADDR_VAL(val)	((val) & 0xFFFF)
+#define DATA_VAL(val)	((val) & 0xFFFF)
+
+#define PCIE_SLAVE_BE(val)	((val) << PCIE_SLAVE_BE_SHIFT)
+#define PCIE_SLAVE_BE_MASK	PCIE_SLAVE_BE(0xF)
+
+struct oxnas_pcie_shared {
+	/* seems all access are serialized, no lock required */
+	int refcount;
+};
+
+/* Structure representing one PCIe interfaces */
+struct oxnas_pcie {
+	void __iomem *cfgbase;
+	void __iomem *base;
+	void __iomem *inbound;
+	void __iomem *outbound;
+	void __iomem *pcie_ctrl;
+
+	int haslink;
+	struct platform_device *pdev;
+	struct resource io;
+	struct resource cfg;
+	struct resource pre_mem;	/* prefetchable */
+	struct resource non_mem;	/* non-prefetchable */
+	struct resource busn;		/* max available bus numbers */
+	int card_reset;			/* gpio pin, optional */
+	unsigned hcsl_en;		/* hcsl pci enable bit */
+	struct clk *clk;
+	struct clk *busclk;		/* for pcie bus, actually the PLLB */
+	void *private_data[1];
+	spinlock_t lock;
+};
+
+static struct oxnas_pcie_shared pcie_shared = {
+	.refcount = 0,
+};
+
+static inline struct oxnas_pcie *sys_to_pcie(struct pci_sys_data *sys)
+{
+	return sys->private_data;
+}
+
+
+static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes)
+{
+	oxnas_register_value_mask(pcie->outbound + PCIE_AHB_SLAVE_CTRL,
+				  PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes));
+	wmb();
+}
+
+static int oxnas_pcie_link_up(struct oxnas_pcie *pcie)
+{
+	unsigned long end;
+
+	/* Poll for PCIE link up */
+	end = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ);
+	while (!time_after(jiffies, end)) {
+		if (readl(pcie->pcie_ctrl) & PCIE_LINK_UP)
+			return 1;
+	}
+	return 0;
+}
+
+static void __init oxnas_pcie_setup_hw(struct oxnas_pcie *pcie)
+{
+	/* We won't have any inbound address translation. This allows PCI
+	 * devices to access anywhere in the AHB address map. Might be regarded
+	 * as a bit dangerous, but let's get things working before we worry
+	 * about that
+	 */
+	oxnas_register_clear_mask(pcie->inbound + IB_ADDR_XLATE_ENABLE,
+				  ENABLE_IN_ADDR_TRANS);
+	wmb();
+
+	/*
+	 * Program outbound translation windows
+	 *
+	 * Outbound window is what is referred to as "PCI client" region in HRM
+	 *
+	 * Could use the larger alternative address space to get >>64M regions
+	 * for graphics cards etc., but will not bother at this point.
+	 *
+	 * IP bug means that AMBA window size must be a power of 2
+	 *
+	 * Set mem0 window for first 16MB of outbound window non-prefetchable
+	 * Set mem1 window for second 16MB of outbound window prefetchable
+	 * Set io window for next 16MB of outbound window
+	 * Set cfg0 for final 1MB of outbound window
+	 *
+	 * Ignore mem1, cfg1 and msg windows for now as no obvious use cases for
+	 * 820 that would need them
+	 *
+	 * Probably ideally want no offset between mem0 window start as seen by
+	 * ARM and as seen on PCI bus and get Linux to assign memory regions to
+	 * PCI devices using the same "PCI client" region start address as seen
+	 * by ARM
+	 */
+
+	/* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */
+	writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_IN0_MEM_ADDR);
+	writel_relaxed(pcie->non_mem.end, pcie->outbound + PCIE_IN0_MEM_LIMIT);
+	writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_POM0_MEM_ADDR);
+
+	/* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */
+	writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_IN1_MEM_ADDR);
+	writel_relaxed(pcie->pre_mem.end, pcie->outbound + PCIE_IN1_MEM_LIMIT);
+	writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_POM1_MEM_ADDR);
+
+	/* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/
+	writel_relaxed(pcie->io.start,	pcie->outbound + PCIE_IN_IO_ADDR);
+	writel_relaxed(pcie->io.end,	pcie->outbound + PCIE_IN_IO_LIMIT);
+
+	/* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/
+	writel_relaxed(pcie->cfg.start,	pcie->outbound + PCIE_IN_CFG0_ADDR);
+	writel_relaxed(pcie->cfg.end, pcie->outbound + PCIE_IN_CFG0_LIMIT);
+	wmb();
+
+	/* Enable outbound address translation */
+	oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_OBTRANS);
+	wmb();
+
+	/*
+	 * Program PCIe command register for core to:
+	 *  enable memory space
+	 *  enable bus master
+	 *  enable io
+	 */
+	writel_relaxed(7, pcie->base + PCI_CONFIG_COMMAND_STATUS);
+	/* which is which */
+	wmb();
+}
+
+static unsigned oxnas_pcie_cfg_to_offset(
+	struct pci_sys_data *sys,
+	unsigned char bus_number,
+	unsigned int devfn,
+	int where)
+{
+	unsigned int function = PCI_FUNC(devfn);
+	unsigned int slot = PCI_SLOT(devfn);
+	unsigned char bus_number_offset;
+
+	bus_number_offset = bus_number - sys->busnr;
+
+	/*
+	 * We'll assume for now that the offset, function, slot, bus encoding
+	 * should map onto linear, contiguous addresses in PCIe config space,
+	 * albeit that the majority will be unused as only slot 0 is valid for
+	 * any PCIe bus and most devices have only function 0
+	 *
+	 * Could be that PCIe in fact works by not encoding the slot number into
+	 * the config space address as it's known that only slot 0 is valid.
+	 * We'll have to experiment if/when we get a PCIe switch connected to
+	 * the PCIe host
+	 */
+	return (bus_number_offset << 20) | (slot << 15) | (function << 12) |
+		(where & ~3);
+}
+
+/* PCI configuration space write function */
+static int oxnas_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+			      int where, int size, u32 val)
+{
+	unsigned long flags;
+	struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
+	unsigned offset;
+	u32 value;
+	u32 lanes;
+
+	/* Only a single device per bus for PCIe point-to-point links */
+	if (PCI_SLOT(devfn) > 0)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	if (!pcie->haslink)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
+					  where);
+
+	value = val << (8 * (where & 3));
+	lanes = (0xf >> (4-size)) << (where & 3);
+	/* it race with mem and io write, but the possibility is low, normally
+	 * all config writes happens at driver initialize stage, wont interleave
+	 * with others.
+	 * and many pcie cards use dword (4bytes) access mem/io access only,
+	 * so not bother to copy that ugly work-around now. */
+	spin_lock_irqsave(&pcie->lock, flags);
+	set_out_lanes(pcie, lanes);
+	writel_relaxed(value, pcie->cfgbase + offset);
+	set_out_lanes(pcie, 0xf);
+	spin_unlock_irqrestore(&pcie->lock, flags);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+/* PCI configuration space read function */
+static int oxnas_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+			      int size, u32 *val)
+{
+	struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
+	unsigned offset;
+	u32 value;
+	u32 left_bytes, right_bytes;
+
+	/* Only a single device per bus for PCIe point-to-point links */
+	if (PCI_SLOT(devfn) > 0) {
+		*val = 0xffffffff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+
+	if (!pcie->haslink) {
+		*val = 0xffffffff;
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+
+	offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
+					  where);
+	value = readl_relaxed(pcie->cfgbase + offset);
+	left_bytes = where & 3;
+	right_bytes = 4 - left_bytes - size;
+	value <<= right_bytes * 8;
+	value >>= (left_bytes + right_bytes) * 8;
+	*val = value;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops oxnas_pcie_ops = {
+	.read = oxnas_pcie_rd_conf,
+	.write = oxnas_pcie_wr_conf,
+};
+
+static int __init oxnas_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+	struct oxnas_pcie *pcie = sys_to_pcie(sys);
+
+	pci_add_resource_offset(&sys->resources, &pcie->non_mem, sys->mem_offset);
+	pci_add_resource_offset(&sys->resources, &pcie->pre_mem, sys->mem_offset);
+	pci_add_resource_offset(&sys->resources, &pcie->io, sys->io_offset);
+	pci_add_resource(&sys->resources, &pcie->busn);
+	if (sys->busnr == 0) { /* default one */
+		sys->busnr = pcie->busn.start;
+	}
+	/* do not use devm_ioremap_resource, it does not like cfg resource */
+	pcie->cfgbase = devm_ioremap(&pcie->pdev->dev, pcie->cfg.start,
+				     resource_size(&pcie->cfg));
+	if (!pcie->cfgbase)
+		return -ENOMEM;
+
+	oxnas_pcie_setup_hw(pcie);
+
+	return 1;
+}
+
+static void __init oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie)
+{
+	struct hw_pci hw;
+	int i;
+
+	memset(&hw, 0, sizeof(hw));
+	for (i = 0; i < NUM_CONTROLLERS; i++)
+		pcie->private_data[i] = pcie;
+
+	hw.nr_controllers = NUM_CONTROLLERS;
+/* I think use stack pointer is a bad idea though it is valid in this case */
+	hw.private_data   = pcie->private_data;
+	hw.setup          = oxnas_pcie_setup;
+	hw.map_irq        = of_irq_parse_and_map_pci;
+	hw.ops            = &oxnas_pcie_ops;
+
+	/* pass dev to maintain of tree, interrupt mapping rely on this */
+	pci_common_init_dev(dev, &hw);
+}
+
+void oxnas_pcie_init_shared_hw(struct platform_device *pdev,
+			       void __iomem *phybase)
+{
+	struct reset_control *rstc;
+	int ret;
+
+	/* generate clocks from HCSL buffers, shared parts */
+	writel(HCSL_BIAS_ON|HCSL_PCIE_EN, SYS_CTRL_HCSL_CTRL);
+
+	/* Ensure PCIe PHY is properly reset */
+	rstc = reset_control_get(&pdev->dev, "phy");
+	if (IS_ERR(rstc)) {
+		ret = PTR_ERR(rstc);
+	} else {
+		ret = reset_control_reset(rstc);
+		reset_control_put(rstc);
+	}
+
+	if (ret) {
+		dev_err(&pdev->dev, "phy reset failed %d\n", ret);
+		return;
+	}
+
+	/* Enable PCIe Pre-Emphasis: What these value means? */
+
+	writel(ADDR_VAL(0x0014), phybase + PHY_ADDR);
+	writel(DATA_VAL(0xce10) | CAP_DATA, phybase + PHY_DATA);
+	writel(DATA_VAL(0xce10) | WRITE_EN, phybase + PHY_DATA);
+
+	writel(ADDR_VAL(0x2004), phybase + PHY_ADDR);
+	writel(DATA_VAL(0x82c7) | CAP_DATA, phybase + PHY_DATA);
+	writel(DATA_VAL(0x82c7) | WRITE_EN, phybase + PHY_DATA);
+}
+
+static int oxnas_pcie_shared_init(struct platform_device *pdev)
+{
+	if (++pcie_shared.refcount == 1) {
+		/* we are the first */
+		struct device_node *np = pdev->dev.of_node;
+		void __iomem *phy = of_iomap(np, 2);
+		if (!phy) {
+			--pcie_shared.refcount;
+			return -ENOMEM;
+		}
+		oxnas_pcie_init_shared_hw(pdev, phy);
+		iounmap(phy);
+		return 0;
+	} else {
+		return 0;
+	}
+}
+
+#if 0
+/* maybe we will call it when enter low power state */
+static void oxnas_pcie_shared_deinit(struct platform_device *pdev)
+{
+	if (--pcie_shared.refcount == 0) {
+		/* no cleanup needed */;
+	}
+}
+#endif
+
+static int __init
+oxnas_pcie_map_registers(struct platform_device *pdev,
+			 struct device_node *np,
+			 struct oxnas_pcie *pcie)
+{
+	struct resource regs;
+	int ret = 0;
+	u32 outbound_ctrl_offset;
+	u32 pcie_ctrl_offset;
+
+	/* 2 is reserved for shared phy */
+	ret = of_address_to_resource(np, 0, &regs);
+	if (ret)
+		return -EINVAL;
+	pcie->base = devm_ioremap_resource(&pdev->dev, &regs);
+	if (!pcie->base)
+		return -ENOMEM;
+
+	ret = of_address_to_resource(np, 1, &regs);
+	if (ret)
+		return -EINVAL;
+	pcie->inbound = devm_ioremap_resource(&pdev->dev, &regs);
+	if (!pcie->inbound)
+		return -ENOMEM;
+
+
+	if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
+				 &outbound_ctrl_offset))
+		return -EINVAL;
+	/* SYSCRTL is shared by too many drivers, so is mapped by board file */
+	pcie->outbound = IOMEM(OXNAS_SYSCRTL_BASE_VA + outbound_ctrl_offset);
+
+	if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
+				 &pcie_ctrl_offset))
+		return -EINVAL;
+	pcie->pcie_ctrl = IOMEM(OXNAS_SYSCRTL_BASE_VA + pcie_ctrl_offset);
+
+	return 0;
+}
+
+static int __init oxnas_pcie_init_res(struct platform_device *pdev,
+				      struct oxnas_pcie *pcie,
+				      struct device_node *np)
+{
+	struct of_pci_range range;
+	struct of_pci_range_parser parser;
+	int ret;
+
+	if (of_pci_range_parser_init(&parser, np))
+		return -EINVAL;
+
+	/* Get the I/O and memory ranges from DT */
+	for_each_of_pci_range(&parser, &range) {
+
+		unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
+		if (restype == IORESOURCE_IO) {
+			of_pci_range_to_resource(&range, np, &pcie->io);
+			pcie->io.name = "I/O";
+		}
+		if (restype == IORESOURCE_MEM) {
+			if (range.flags & IORESOURCE_PREFETCH) {
+				of_pci_range_to_resource(&range, np, &pcie->pre_mem);
+				pcie->pre_mem.name = "PRE MEM";
+			} else {
+				of_pci_range_to_resource(&range, np, &pcie->non_mem);
+				pcie->non_mem.name = "NON MEM";
+			}
+
+		}
+		if (restype == 0)
+			of_pci_range_to_resource(&range, np, &pcie->cfg);
+	}
+
+	/* Get the bus range */
+	ret = of_pci_parse_bus_range(np, &pcie->busn);
+
+	if (ret) {
+		dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
+			ret);
+		return ret;
+	}
+
+	pcie->card_reset = of_get_gpio(np, 0);
+	if (pcie->card_reset < 0)
+		dev_info(&pdev->dev, "card reset gpio pin not exists\n");
+
+	if (of_property_read_u32(np, "plxtech,pcie-hcsl-bit", &pcie->hcsl_en))
+		return -EINVAL;
+
+	pcie->clk = of_clk_get_by_name(np, "pcie");
+	if (IS_ERR(pcie->clk)) {
+		return PTR_ERR(pcie->clk);
+	}
+
+	pcie->busclk = of_clk_get_by_name(np, "busclk");
+	if (IS_ERR(pcie->busclk)) {
+		clk_put(pcie->clk);
+		return PTR_ERR(pcie->busclk);
+	}
+
+	return 0;
+}
+
+static void oxnas_pcie_init_hw(struct platform_device *pdev,
+			       struct oxnas_pcie *pcie)
+{
+	u32 version_id;
+	int ret;
+
+	clk_prepare_enable(pcie->busclk);
+
+	/* reset PCIe cards use hard-wired gpio pin */
+	if (pcie->card_reset >= 0 &&
+	    !gpio_direction_output(pcie->card_reset, 0)) {
+		wmb();
+		mdelay(10);
+		/* must tri-state the pin to pull it up */
+		gpio_direction_input(pcie->card_reset);
+		wmb();
+		mdelay(100);
+	}
+
+	oxnas_register_set_mask(SYS_CTRL_HCSL_CTRL, BIT(pcie->hcsl_en));
+
+	/* core */
+	ret = device_reset(&pdev->dev);
+	if (ret) {
+		dev_err(&pdev->dev, "core reset failed %d\n", ret);
+		return;
+	}
+
+	/* Start PCIe core clocks */
+	clk_prepare_enable(pcie->clk);
+
+	version_id = readl_relaxed(pcie->base + PCI_CONFIG_VERSION_DEVICEID);
+	dev_info(&pdev->dev, "PCIe version/deviceID 0x%x\n", version_id);
+
+	if (version_id != VERSION_ID_MAGIC) {
+		dev_info(&pdev->dev, "PCIe controller not found\n");
+		pcie->haslink = 0;
+		return;
+	}
+
+	/* allow entry to L23 state */
+	oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_READY_ENTR_L23);
+
+	/* Set PCIe core into RootCore mode */
+	oxnas_register_value_mask(pcie->pcie_ctrl, PCIE_DEVICE_TYPE_MASK,
+				  PCIE_DEVICE_TYPE_ROOT);
+	wmb();
+
+	/* Bring up the PCI core */
+	oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_LTSSM);
+	wmb();
+}
+
+static int __init oxnas_pcie_probe(struct platform_device *pdev)
+{
+	struct oxnas_pcie *pcie;
+	struct device_node *np = pdev->dev.of_node;
+	int ret;
+
+	pcie = devm_kzalloc(&pdev->dev, sizeof(struct oxnas_pcie),
+			    GFP_KERNEL);
+	if (!pcie)
+		return -ENOMEM;
+
+	pcie->pdev = pdev;
+	pcie->haslink = 1;
+	spin_lock_init(&pcie->lock);
+
+	ret = oxnas_pcie_init_res(pdev, pcie, np);
+	if (ret)
+		return ret;
+	if (pcie->card_reset >= 0) {
+		ret = gpio_request_one(pcie->card_reset, GPIOF_DIR_IN,
+				       dev_name(&pdev->dev));
+		if (ret) {
+			dev_err(&pdev->dev, "cannot request gpio pin %d\n",
+				pcie->card_reset);
+			return ret;
+		}
+	}
+
+	ret = oxnas_pcie_map_registers(pdev, np, pcie);
+	if (ret) {
+		dev_err(&pdev->dev, "cannot map registers\n");
+		goto err_free_gpio;
+	}
+
+	ret = oxnas_pcie_shared_init(pdev);
+	if (ret)
+		goto err_free_gpio;
+
+	/* if hw not found, haslink cleared */
+	oxnas_pcie_init_hw(pdev, pcie);
+
+	if (pcie->haslink && oxnas_pcie_link_up(pcie)) {
+		pcie->haslink = 1;
+		dev_info(&pdev->dev, "link up\n");
+	} else {
+		pcie->haslink = 0;
+		dev_info(&pdev->dev, "link down\n");
+	}
+	/* should we register our controller even when pcie->haslink is 0 ? */
+	/* register the controller with framework */
+	oxnas_pcie_enable(&pdev->dev, pcie);
+
+	return 0;
+
+err_free_gpio:
+	if (pcie->card_reset)
+		gpio_free(pcie->card_reset);
+
+	return ret;
+}
+
+static const struct of_device_id oxnas_pcie_of_match_table[] = {
+	{ .compatible = "plxtech,nas782x-pcie", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, oxnas_pcie_of_match_table);
+
+static struct platform_driver oxnas_pcie_driver = {
+	.driver = {
+		.owner = THIS_MODULE,
+		.name = "oxnas-pcie",
+		.of_match_table =
+		   of_match_ptr(oxnas_pcie_of_match_table),
+	},
+};
+
+static int __init oxnas_pcie_init(void)
+{
+	return platform_driver_probe(&oxnas_pcie_driver,
+				     oxnas_pcie_probe);
+}
+
+subsys_initcall(oxnas_pcie_init);
+
+MODULE_AUTHOR("Ma Haijun <mahaijuns@gmail.com>");
+MODULE_DESCRIPTION("NAS782x PCIe driver");
+MODULE_LICENSE("GPLv2");
--- a/target/linux/oxnas/files/drivers/pinctrl/pinctrl-oxnas.c
+++ b/target/linux/oxnas/files/drivers/pinctrl/pinctrl-oxnas.c
--- a/target/linux/oxnas/files/drivers/reset/reset-ox820.c
+++ b/target/linux/oxnas/files/drivers/reset/reset-ox820.c
@@ -0,0 +1,107 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <mach/hardware.h>
+
+static int ox820_reset_reset(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	writel(BIT(id), SYS_CTRL_RST_SET_CTRL);
+	writel(BIT(id), SYS_CTRL_RST_CLR_CTRL);
+	return 0;
+}
+
+static int ox820_reset_assert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	writel(BIT(id), SYS_CTRL_RST_SET_CTRL);
+
+	return 0;
+}
+
+static int ox820_reset_deassert(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	writel(BIT(id), SYS_CTRL_RST_CLR_CTRL);
+
+	return 0;
+}
+
+static struct reset_control_ops ox820_reset_ops = {
+	.reset		= ox820_reset_reset,
+	.assert		= ox820_reset_assert,
+	.deassert	= ox820_reset_deassert,
+};
+
+static const struct of_device_id ox820_reset_dt_ids[] = {
+	 { .compatible = "plxtech,nas782x-reset", },
+	 { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, ox820_reset_dt_ids);
+
+struct reset_controller_dev rcdev;
+
+static int ox820_reset_probe(struct platform_device *pdev)
+{
+	struct reset_controller_dev *rcdev;
+
+	rcdev = devm_kzalloc(&pdev->dev, sizeof(*rcdev), GFP_KERNEL);
+	if (!rcdev)
+		return -ENOMEM;
+
+	/* note: reset controller is statically mapped */
+
+	rcdev->owner = THIS_MODULE;
+	rcdev->nr_resets = 32;
+	rcdev->ops = &ox820_reset_ops;
+	rcdev->of_node = pdev->dev.of_node;
+	reset_controller_register(rcdev);
+	platform_set_drvdata(pdev, rcdev);
+
+	return 0;
+}
+
+static int ox820_reset_remove(struct platform_device *pdev)
+{
+	struct reset_controller_dev *rcdev = platform_get_drvdata(pdev);
+
+	reset_controller_unregister(rcdev);
+
+	return 0;
+}
+
+static struct platform_driver ox820_reset_driver = {
+	.probe	= ox820_reset_probe,
+	.remove	= ox820_reset_remove,
+	.driver = {
+		.name		= "ox820-reset",
+		.owner		= THIS_MODULE,
+		.of_match_table	= ox820_reset_dt_ids,
+	},
+};
+
+static int __init ox820_reset_init(void)
+{
+	return platform_driver_probe(&ox820_reset_driver,
+				     ox820_reset_probe);
+}
+/*
+ * reset controller does not support probe deferral, so it has to be
+ * initialized before any user, in particular, PCIE uses subsys_initcall.
+ */
+arch_initcall(ox820_reset_init);
+
+MODULE_AUTHOR("Ma Haijun");
+MODULE_LICENSE("GPL");
--- a/target/linux/oxnas/files/drivers/usb/host/ehci-oxnas.c
+++ b/target/linux/oxnas/files/drivers/usb/host/ehci-oxnas.c
@@ -0,0 +1,316 @@
+/*
+ * drivers/usb/host/ehci-oxnas.c
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <mach/hardware.h>
+#include <mach/utils.h>
+
+#include "ehci.h"
+
+struct oxnas_hcd {
+	struct clk *clk;
+	struct clk *refsrc;
+	struct clk *phyref;
+	int use_pllb;
+	int use_phya;
+	struct reset_control *rst_host;
+	struct reset_control *rst_phya;
+	struct reset_control *rst_phyb;
+};
+
+#define DRIVER_DESC "Oxnas On-Chip EHCI Host Controller"
+
+static struct hc_driver __read_mostly oxnas_hc_driver;
+
+static void start_oxnas_usb_ehci(struct oxnas_hcd *oxnas)
+{
+	u32 reg;
+
+	if (oxnas->use_pllb) {
+		/* enable pllb */
+		clk_prepare_enable(oxnas->refsrc);
+		/* enable ref600 */
+		clk_prepare_enable(oxnas->phyref);
+		/* 600MHz pllb divider for 12MHz */
+		writel(PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0),
+			SEC_CTRL_PLLB_DIV_CTRL);
+
+	} else {
+		/* ref 300 divider for 12MHz */
+		writel(REF300_DIV_INT(25) | REF300_DIV_FRAC(0),
+			SYS_CTRL_REF300_DIV);
+	}
+
+	/* Ensure the USB block is properly reset */
+	reset_control_reset(oxnas->rst_host);
+	reset_control_reset(oxnas->rst_phya);
+	reset_control_reset(oxnas->rst_phyb);
+
+	/* Force the high speed clock to be generated all the time, via serial
+	 programming of the USB HS PHY */
+	writel((2UL << USBHSPHY_TEST_ADD) |
+		   (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
+
+	writel((1UL << USBHSPHY_TEST_CLK) |
+		   (2UL << USBHSPHY_TEST_ADD) |
+		   (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
+
+	writel((0xfUL << USBHSPHY_TEST_ADD) |
+		   (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
+
+	writel((1UL << USBHSPHY_TEST_CLK) |
+		   (0xfUL << USBHSPHY_TEST_ADD) |
+		   (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
+
+	if (oxnas->use_pllb) /* use pllb clock */
+		writel(USB_CLK_INTERNAL | USB_INT_CLK_PLLB, SYS_CTRL_USB_CTRL);
+	else /* use ref300 derived clock */
+		writel(USB_CLK_INTERNAL | USB_INT_CLK_REF300,
+			SYS_CTRL_USB_CTRL);
+
+	if (oxnas->use_phya) {
+		/* Configure USB PHYA as a host */
+		reg = readl(SYS_CTRL_USB_CTRL);
+		reg &= ~USBAMUX_DEVICE;
+		writel(reg, SYS_CTRL_USB_CTRL);
+	}
+
+	/* Enable the clock to the USB block */
+	clk_prepare_enable(oxnas->clk);
+}
+
+static void stop_oxnas_usb_ehci(struct oxnas_hcd *oxnas)
+{
+	reset_control_assert(oxnas->rst_host);
+	reset_control_assert(oxnas->rst_phya);
+	reset_control_assert(oxnas->rst_phyb);
+
+	if (oxnas->use_pllb) {
+		clk_disable_unprepare(oxnas->phyref);
+		clk_disable_unprepare(oxnas->refsrc);
+	}
+	clk_disable_unprepare(oxnas->clk);
+}
+
+static int ehci_oxnas_reset(struct usb_hcd *hcd)
+{
+	#define  txttfill_tuning	reserved2[0]
+
+	struct ehci_hcd	*ehci;
+	u32 tmp;
+	int retval = ehci_setup(hcd);
+	if (retval)
+		return retval;
+
+	ehci = hcd_to_ehci(hcd);
+	tmp = ehci_readl(ehci, &ehci->regs->txfill_tuning);
+	tmp &= ~0x00ff0000;
+	tmp |= 0x003f0000; /* set burst pre load count to 0x40 (63 * 4 bytes)  */
+	tmp |= 0x16; /* set sheduler overhead to 22 * 1.267us (HS) or 22 * 6.33us (FS/LS)*/
+	ehci_writel(ehci, tmp,  &ehci->regs->txfill_tuning);
+
+	tmp = ehci_readl(ehci, &ehci->regs->txttfill_tuning);
+	tmp |= 0x2; /* set sheduler overhead to 2 * 6.333us */
+	ehci_writel(ehci, tmp,  &ehci->regs->txttfill_tuning);
+
+	return retval;
+}
+
+static int ehci_oxnas_drv_probe(struct platform_device *ofdev)
+{
+	struct device_node *np = ofdev->dev.of_node;
+	struct usb_hcd *hcd;
+	struct ehci_hcd *ehci;
+	struct resource res;
+	struct oxnas_hcd *oxnas;
+	int irq, err;
+	struct reset_control *rstc;
+
+	if (usb_disabled())
+		return -ENODEV;
+
+	if (!ofdev->dev.dma_mask)
+		ofdev->dev.dma_mask = &ofdev->dev.coherent_dma_mask;
+	if (!ofdev->dev.coherent_dma_mask)
+		ofdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+
+	hcd = usb_create_hcd(&oxnas_hc_driver,	&ofdev->dev,
+					dev_name(&ofdev->dev));
+	if (!hcd)
+		return -ENOMEM;
+
+	err = of_address_to_resource(np, 0, &res);
+	if (err)
+		goto err_res;
+
+	hcd->rsrc_start = res.start;
+	hcd->rsrc_len = resource_size(&res);
+
+	hcd->regs = devm_ioremap_resource(&ofdev->dev, &res);
+	if (IS_ERR(hcd->regs)) {
+		dev_err(&ofdev->dev, "devm_ioremap_resource failed\n");
+		err = PTR_ERR(hcd->regs);
+		goto err_ioremap;
+	}
+
+	oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv;
+
+	oxnas->use_pllb = of_property_read_bool(np, "plxtch,ehci_use_pllb");
+	oxnas->use_phya = of_property_read_bool(np, "plxtch,ehci_use_phya");
+
+	oxnas->clk = of_clk_get_by_name(np, "usb");
+	if (IS_ERR(oxnas->clk)) {
+		err = PTR_ERR(oxnas->clk);
+		goto err_clk;
+	}
+
+	if (oxnas->use_pllb) {
+		oxnas->refsrc = of_clk_get_by_name(np, "refsrc");
+		if (IS_ERR(oxnas->refsrc)) {
+			err = PTR_ERR(oxnas->refsrc);
+			goto err_refsrc;
+		}
+		oxnas->phyref = of_clk_get_by_name(np, "phyref");
+		if (IS_ERR(oxnas->refsrc)) {
+			err = PTR_ERR(oxnas->refsrc);
+			goto err_phyref;
+		}
+
+	} else {
+		oxnas->refsrc = NULL;
+		oxnas->phyref = NULL;
+	}
+
+	rstc = devm_reset_control_get(&ofdev->dev, "host");
+	if (IS_ERR(rstc)) {
+		err = PTR_ERR(rstc);
+		goto err_rst;
+	}
+	oxnas->rst_host = rstc;
+
+	rstc = devm_reset_control_get(&ofdev->dev, "phya");
+	if (IS_ERR(rstc)) {
+		err = PTR_ERR(rstc);
+		goto err_rst;
+	}
+	oxnas->rst_phya = rstc;
+
+	rstc = devm_reset_control_get(&ofdev->dev, "phyb");
+	if (IS_ERR(rstc)) {
+		err = PTR_ERR(rstc);
+		goto err_rst;
+	}
+	oxnas->rst_phyb = rstc;
+
+	irq = irq_of_parse_and_map(np, 0);
+	if (!irq) {
+		dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
+		err = -EBUSY;
+		goto err_irq;
+	}
+
+	hcd->has_tt = 1;
+	ehci = hcd_to_ehci(hcd);
+	ehci->caps = hcd->regs;
+
+	start_oxnas_usb_ehci(oxnas);
+
+	err = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_DISABLED);
+	if (err)
+		goto err_hcd;
+
+	return 0;
+
+err_hcd:
+	stop_oxnas_usb_ehci(oxnas);
+err_irq:
+err_rst:
+	if (oxnas->phyref)
+		clk_put(oxnas->phyref);
+err_phyref:
+	if (oxnas->refsrc)
+		clk_put(oxnas->refsrc);
+err_refsrc:
+	clk_put(oxnas->clk);
+err_clk:
+err_ioremap:
+err_res:
+	usb_put_hcd(hcd);
+
+	return err;
+}
+
+static int ehci_oxnas_drv_remove(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+	struct oxnas_hcd *oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv;
+
+	usb_remove_hcd(hcd);
+	if (oxnas->use_pllb) {
+		clk_disable_unprepare(oxnas->phyref);
+		clk_put(oxnas->phyref);
+		clk_disable_unprepare(oxnas->refsrc);
+		clk_put(oxnas->refsrc);
+	}
+	clk_disable_unprepare(oxnas->clk);
+	usb_put_hcd(hcd);
+
+	return 0;
+}
+
+static const struct of_device_id oxnas_ehci_dt_ids[] = {
+	{ .compatible = "plxtch,nas782x-ehci" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, oxnas_ehci_dt_ids);
+
+static struct platform_driver ehci_oxnas_driver = {
+	.probe		= ehci_oxnas_drv_probe,
+	.remove		= ehci_oxnas_drv_remove,
+	.shutdown	= usb_hcd_platform_shutdown,
+	.driver.name	= "oxnas-ehci",
+	.driver.of_match_table	= oxnas_ehci_dt_ids,
+};
+
+static const struct ehci_driver_overrides oxnas_overrides __initconst = {
+	.reset = ehci_oxnas_reset,
+	.extra_priv_size = sizeof(struct oxnas_hcd),
+};
+
+static int __init ehci_oxnas_init(void)
+{
+	if (usb_disabled())
+		return -ENODEV;
+
+	ehci_init_driver(&oxnas_hc_driver, &oxnas_overrides);
+	return platform_driver_register(&ehci_oxnas_driver);
+}
+module_init(ehci_oxnas_init);
+
+static void __exit ehci_oxnas_cleanup(void)
+{
+	platform_driver_unregister(&ehci_oxnas_driver);
+}
+module_exit(ehci_oxnas_cleanup);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_ALIAS("platform:oxnas-ehci");
+MODULE_LICENSE("GPL");
--- a/target/linux/oxnas/image/Makefile
+++ b/target/linux/oxnas/image/Makefile
@@ -0,0 +1,135 @@
+#
+# Copyright (C) 2013 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+STG212_UBI_OPTS = -m 2048 -p 128KiB -s 512
+STG212_UBIFS_OPTS = -m 2048 -e 126KiB -c 4096
+
+KD20_UBI_OPTS = -m 2048 -p 128KiB -s 512
+KD20_UBIFS_OPTS = -m 2048 -e 126KiB -c 4096
+
+POGOPLUG_PRO_UBI_OPTS = -m 2048 -p 128KiB -s 512
+POGOPLUG_PRO_UBIFS_OPTS = -m 2048 -e 126KiB -c 4096
+
+POGOPLUG_V3_UBI_OPTS = -m 2048 -p 128KiB -s 512
+POGOPLUG_V3_UBIFS_OPTS = -m 2048 -e 126KiB -c 4096
+
+KDIR_TMP:=$(KDIR)/tmp
+VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux
+UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage
+
+define sanitize_profile_name
+$(shell echo $(PROFILE) | tr '[:upper:]' '[:lower:]' | sed 's/_/-/g')
+endef
+
+define Image/BuildKernel/Template
+	$(CP) $(LINUX_DIR)/arch/arm/boot/dts/ox820-$(1).dtb $(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb
+
+	$(call Image/BuildKernel/MkFIT,$(1),$(KDIR)/zImage,$(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb,none,0x60008000,0x60008000)
+	$(CP) $(KDIR)/fit-$(1).itb $(BIN_DIR)/$(IMG_PREFIX)-$(1)-fit-uImage.bin
+
+ ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
+	$(call Image/BuildKernel/MkFIT,$(1),$(KDIR)/zImage-initramfs,$(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb,none,0x60008000,0x60008000,-initramfs)
+	$(CP) $(KDIR)/fit-$(1)-initramfs.itb $(BIN_DIR)/$(IMG_PREFIX)-$(1)-fit-uImage-initramfs.itb
+	if [ -e "$(BIN_DIR)/$(IMG_PREFIX)-ox820-u-boot.bin" ]; then \
+	( dd if=$(BIN_DIR)/$(IMG_PREFIX)-ox820-u-boot.bin bs=128k conv=sync ; dd if=$(KDIR)/fit-$(1)-initramfs.itb bs=128k conv=sync ) \
+		> $(BIN_DIR)/$(IMG_PREFIX)-$(1)-u-boot-initramfs.itb; \
+	fi
+ endif
+
+	$(CP) $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-zImage
+	$(call Image/BuildKernel/MkuImage, \
+		none, 0x60008000, 0x60008000, \
+		$(BIN_DIR)/$(IMG_PREFIX)-zImage, \
+		$(BIN_DIR)/$(IMG_PREFIX)-uImage \
+	)
+
+ ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
+	$(CP) $(KDIR)/zImage-initramfs $(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs
+	$(call Image/BuildKernel/MkuImage, \
+		none, 0x60008000, 0x60008000, \
+		$(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs, \
+		$(BIN_DIR)/$(IMG_PREFIX)-uImage-initramfs \
+	)
+ endif
+endef
+
+define Image/InstallKernel/Template
+
+ ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_KERNEL),)
+	$(INSTALL_DIR) $(TARGET_DIR)/boot
+   ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_UIMAGE),)
+	$(CP) $(BIN_DIR)/$(IMG_PREFIX)-uImage $(TARGET_DIR)/boot/
+	ln -sf $(IMG_PREFIX)-uImage $(TARGET_DIR)/boot/uImage
+   endif
+   ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_ZIMAGE),)
+	$(CP) $(BIN_DIR)/$(IMG_PREFIX)-zImage $(TARGET_DIR)/boot/
+	ln -sf $(IMG_PREFIX)-zImage $(TARGET_DIR)/boot/zImage
+   endif
+   ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_FIT),)
+	$(CP) $(BIN_DIR)/$(IMG_PREFIX)-$(1)-fit-uImage.itb $(TARGET_DIR)/boot/
+	ln -sf $(IMG_PREFIX)-$(1)-fit-uImage.itb $(TARGET_DIR)/boot/uImage.itb
+   endif
+ endif
+
+ ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_DTB),)
+	$(INSTALL_DIR) $(TARGET_DIR)/boot
+  ifneq ($(1),)
+	$(CP) $(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb $(TARGET_DIR)/boot/
+	ln -sf $(IMG_PREFIX)-$(1).dtb $(TARGET_DIR)/boot/$(1).dtb
+  endif
+ endif
+endef
+
+define Image/Build/squashfs
+	$(call Image/Build/SysupgradeNAND,$(call sanitize_profile_name),$(1),$(KDIR)/fit-$(call sanitize_profile_name).itb)
+	$(call Image/Build/UbinizeImage,$(call sanitize_profile_name),--uboot-env --kernel $(KDIR)/fit-$(call sanitize_profile_name).itb,$(1),$($(PROFILE)_UBI_OPTS))
+endef
+
+define Image/mkfs/targz
+
+	$(TAR) -czpf $(BIN_DIR)/$(IMG_PREFIX)-$(call sanitize_profile_name)-rootfs.tar.gz --numeric-owner --owner=0 --group=0 -C $(TARGET_DIR)/ .
+endef
+
+define Image/Build/ubifs
+
+ ifneq ($($(PROFILE)_UBIFS_OPTS),)
+	$(call Image/Build/SysupgradeNAND,$(call sanitize_profile_name),ubifs,$(KDIR)/fit-$(call sanitize_profile_name).itb)
+	$(call Image/Build/UbinizeImage,$(call sanitize_profile_name),--uboot-env --kernel $(KDIR)/fit-$(call sanitize_profile_name).itb,ubifs,$($(PROFILE)_UBI_OPTS))
+ endif
+
+endef
+
+Image/BuildKernel/Template/POGOPLUG_PRO=$(call Image/BuildKernel/Template,pogoplug-pro)
+Image/InstallKernel/Template/POGOPLUG_PRO=$(call Image/InstallKernel/Template,pogoplug-pro)
+
+Image/BuildKernel/Template/POGOPLUG_V3=$(call Image/BuildKernel/Template,pogoplug-v3)
+Image/InstallKernel/Template/POGOPLUG_V3=$(call Image/InstallKernel/Template,pogoplug-v3)
+
+Image/BuildKernel/Template/STG212=$(call Image/BuildKernel/Template,stg212)
+Image/InstallKernel/Template/STG212=$(call Image/InstallKernel/Template,stg212)
+
+Image/BuildKernel/Template/KD20=$(call Image/BuildKernel/Template,kd20)
+Image/InstallKernel/Template/KD20=$(call Image/InstallKernel/Template,kd20)
+
+define Image/BuildKernel
+	$(call Image/BuildKernel/Template/$(PROFILE))
+endef
+
+define Image/InstallKernel
+	$(call Image/InstallKernel/Template/$(PROFILE))
+endef
+
+define Image/Build
+	$(if $(Image/Build/$(1)), \
+		$(call Image/Build/$(1),$(1)), \
+		$(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(call sanitize_profile_name)-$(1).img \
+	)
+endef
+
+$(eval $(call BuildImage))
--- a/target/linux/oxnas/patches-3.18/010-arm_introduce-dma-fiq-irq-broadcast.patch
+++ b/target/linux/oxnas/patches-3.18/010-arm_introduce-dma-fiq-irq-broadcast.patch
@@ -0,0 +1,62 @@
+Index: linux-3.18-rc4/arch/arm/include/asm/glue-cache.h
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/include/asm/glue-cache.h
+++ linux-3.18-rc4/arch/arm/include/asm/glue-cache.h
+@@ -156,11 +156,19 @@ static inline void nop_dma_unmap_area(co
+ #define __cpuc_flush_user_range		__glue(_CACHE,_flush_user_cache_range)
+ #define __cpuc_coherent_kern_range	__glue(_CACHE,_coherent_kern_range)
+ #define __cpuc_coherent_user_range	__glue(_CACHE,_coherent_user_range)
+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
+ #define __cpuc_flush_dcache_area	__glue(_CACHE,_flush_kern_dcache_area)
+ 
+ #define dmac_map_area			__glue(_CACHE,_dma_map_area)
+ #define dmac_unmap_area			__glue(_CACHE,_dma_unmap_area)
+ #define dmac_flush_range		__glue(_CACHE,_dma_flush_range)
+#else
+#define __cpuc_flush_dcache_area	__glue(fiq,_flush_kern_dcache_area)
+
+#define dmac_map_area			__glue(fiq,_dma_map_area)
+#define dmac_unmap_area			__glue(fiq,_dma_unmap_area)
+#define dmac_flush_range		__glue(fiq,_dma_flush_range)
+#endif /* CONFIG_DMA_CACHE_FIQ_BROADCAST */
+ #endif
+ 
+ #endif
+Index: linux-3.18-rc4/arch/arm/mm/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/mm/Kconfig
+++ linux-3.18-rc4/arch/arm/mm/Kconfig
+@@ -843,6 +843,17 @@ config DMA_CACHE_RWFO
+ 	  in hardware, other workarounds are needed (e.g. cache
+ 	  maintenance broadcasting in software via FIQ).
+ 
+config DMA_CACHE_FIQ_BROADCAST
+	bool "Enable fiq broadcast DMA cache maintenance"
+	depends on CPU_V6K && SMP
+	select FIQ
+	help
+	  The Snoop Control Unit on ARM11MPCore does not detect the
+	  cache maintenance operations and the dma_{map,unmap}_area()
+	  functions may leave stale cache entries on other CPUs. By
+	  enabling this option, fiq broadcast in the ARMv6
+	  DMA cache maintenance functions is performed.
+
+ config OUTER_CACHE
+ 	bool
+ 
+Index: linux-3.18-rc4/arch/arm/mm/flush.c
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/mm/flush.c
+++ linux-3.18-rc4/arch/arm/mm/flush.c
+@@ -314,7 +314,11 @@ void flush_dcache_page(struct page *page
+ 
+ 	mapping = page_mapping(page);
+ 
+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
+ 	if (!cache_ops_need_broadcast() &&
+#else
+	if (
+#endif
+ 	    mapping && !page_mapped(page))
+ 		clear_bit(PG_dcache_clean, &page->flags);
+ 	else {
--- a/target/linux/oxnas/patches-3.18/250-add-plxtech-vendor-prefix.patch
+++ b/target/linux/oxnas/patches-3.18/250-add-plxtech-vendor-prefix.patch
@@ -0,0 +1,12 @@
+Index: linux-3.18-rc4/Documentation/devicetree/bindings/vendor-prefixes.txt
+===================================================================
+--- linux-3.18-rc4.orig/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ linux-3.18-rc4/Documentation/devicetree/bindings/vendor-prefixes.txt
+@@ -113,6 +113,7 @@ panasonic	Panasonic Corporation
+ phytec	PHYTEC Messtechnik GmbH
+ picochip	Picochip Ltd
+ plathome	Plat'Home Co., Ltd.
+plxtech	PLX Technology, Inc.
+ pixcir  PIXCIR MICROELECTRONICS Co., Ltd
+ powervr	PowerVR (deprecated, use img)
+ qca	Qualcomm Atheros, Inc.
--- a/target/linux/oxnas/patches-3.18/300-introduce-oxnas-platform.patch
+++ b/target/linux/oxnas/patches-3.18/300-introduce-oxnas-platform.patch
@@ -0,0 +1,79 @@
+Index: linux-3.18-rc4/arch/arm/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/Kconfig
+++ linux-3.18-rc4/arch/arm/Kconfig
+@@ -369,6 +369,17 @@ config ARCH_VERSATILE
+ 	help
+ 	  This enables support for ARM Ltd Versatile board.
+ 
+config ARCH_OXNAS
+	bool "Oxford Semiconductor 815/820/825 NAS SoC"
+	select ARCH_REQUIRE_GPIOLIB
+	select CLKDEV_LOOKUP
+	select GENERIC_CLOCKEVENTS
+	select COMMON_CLK
+	select MIGHT_HAVE_PCI
+	select ARCH_HAS_RESET_CONTROLLER
+	help
+		This enables support for Oxsemi 815/820/825 NAS SoC
+
+ config ARCH_AT91
+ 	bool "Atmel AT91"
+ 	select ARCH_REQUIRE_GPIOLIB
+@@ -922,6 +933,8 @@ source "arch/arm/mach-omap2/Kconfig"
+ 
+ source "arch/arm/mach-orion5x/Kconfig"
+ 
+source "arch/arm/mach-oxnas/Kconfig"
+
+ source "arch/arm/mach-picoxcell/Kconfig"
+ 
+ source "arch/arm/mach-pxa/Kconfig"
+Index: linux-3.18-rc4/arch/arm/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/Makefile
+++ linux-3.18-rc4/arch/arm/Makefile
+@@ -187,6 +187,7 @@ machine-$(CONFIG_ARCH_NSPIRE)		+= nspire
+ machine-$(CONFIG_ARCH_OMAP1)		+= omap1
+ machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
+ machine-$(CONFIG_ARCH_ORION5X)		+= orion5x
+machine-$(CONFIG_ARCH_OXNAS)		+= oxnas
+ machine-$(CONFIG_ARCH_PICOXCELL)	+= picoxcell
+ machine-$(CONFIG_ARCH_PXA)		+= pxa
+ machine-$(CONFIG_ARCH_QCOM)		+= qcom
+Index: linux-3.18-rc4/arch/arm/boot/dts/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/boot/dts/Makefile
+++ linux-3.18-rc4/arch/arm/boot/dts/Makefile
+@@ -352,6 +352,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += orion5x-la
+ 	orion5x-lacie-ethernet-disk-mini-v2.dtb \
+ 	orion5x-maxtor-shared-storage-2.dtb \
+ 	orion5x-rd88f5182-nas.dtb
+dtb-$(CONFIG_ARCH_OXNAS) += ox820-pogoplug-pro.dtb
+ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
+ dtb-$(CONFIG_ARCH_QCOM) += \
+ 	qcom-apq8064-cm-qs600.dtb \
+Index: linux-3.18-rc4/arch/arm/tools/mach-types
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/tools/mach-types
+++ linux-3.18-rc4/arch/arm/tools/mach-types
+@@ -228,6 +228,7 @@ edb9302a		MACH_EDB9302A		EDB9302A		1127
+ edb9307a		MACH_EDB9307A		EDB9307A		1128
+ omap_3430sdp		MACH_OMAP_3430SDP	OMAP_3430SDP		1138
+ vstms			MACH_VSTMS		VSTMS			1140
+ox820			MACH_OX820		OX820			1152
+ micro9m			MACH_MICRO9M		MICRO9M			1169
+ bug			MACH_BUG		BUG			1179
+ at91sam9263ek		MACH_AT91SAM9263EK	AT91SAM9263EK		1202
+Index: linux-3.18-rc4/drivers/clk/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/clk/Makefile
+++ linux-3.18-rc4/drivers/clk/Makefile
+@@ -29,6 +29,7 @@ obj-$(CONFIG_COMMON_CLK_MAX77802)	+= clk
+ obj-$(CONFIG_ARCH_MOXART)		+= clk-moxart.o
+ obj-$(CONFIG_ARCH_NOMADIK)		+= clk-nomadik.o
+ obj-$(CONFIG_ARCH_NSPIRE)		+= clk-nspire.o
+obj-$(CONFIG_ARCH_OXNAS)		+= clk-oxnas.o
+ obj-$(CONFIG_COMMON_CLK_PALMAS)		+= clk-palmas.o
+ obj-$(CONFIG_CLK_PPC_CORENET)		+= clk-ppc-corenet.o
+ obj-$(CONFIG_COMMON_CLK_RK808)		+= clk-rk808.o
--- a/target/linux/oxnas/patches-3.18/310-oxnas-clocksource.patch
+++ b/target/linux/oxnas/patches-3.18/310-oxnas-clocksource.patch
@@ -0,0 +1,29 @@
+Index: linux-3.18-rc4/drivers/clocksource/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/clocksource/Kconfig
+++ linux-3.18-rc4/drivers/clocksource/Kconfig
+@@ -156,6 +156,12 @@ config VF_PIT_TIMER
+ 	help
+ 	  Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
+ 
+config CLKSRC_RPS_TIMER
+	def_bool y if ARCH_OXNAS
+	select CLKSRC_MMIO
+	help
+	  This option enables support for the oxnas rps timers.
+
+ config SYS_SUPPORTS_SH_CMT
+         bool
+ 
+Index: linux-3.18-rc4/drivers/clocksource/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/clocksource/Makefile
+++ linux-3.18-rc4/drivers/clocksource/Makefile
+@@ -36,6 +36,7 @@ obj-$(CONFIG_CLKSRC_EFM32)	+= time-efm32
+ obj-$(CONFIG_CLKSRC_EXYNOS_MCT)	+= exynos_mct.o
+ obj-$(CONFIG_CLKSRC_SAMSUNG_PWM)	+= samsung_pwm_timer.o
+ obj-$(CONFIG_FSL_FTM_TIMER)	+= fsl_ftm_timer.o
+obj-$(CONFIG_CLKSRC_RPS_TIMER)	+= oxnas_rps_timer.o
+ obj-$(CONFIG_VF_PIT_TIMER)	+= vf_pit_timer.o
+ obj-$(CONFIG_CLKSRC_QCOM)	+= qcom-timer.o
+ obj-$(CONFIG_MTK_TIMER)		+= mtk_timer.o
--- a/target/linux/oxnas/patches-3.18/320-oxnas-irqchip.patch
+++ b/target/linux/oxnas/patches-3.18/320-oxnas-irqchip.patch
@@ -0,0 +1,40 @@
+Index: linux-3.18-rc4/drivers/irqchip/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/irqchip/Kconfig
+++ linux-3.18-rc4/drivers/irqchip/Kconfig
+@@ -15,6 +15,11 @@ config ARM_GIC_V3
+ 	select IRQ_DOMAIN
+ 	select MULTI_IRQ_HANDLER
+ 
+config PLXTECH_RPS
+	def_bool y if ARHC_OXNAS
+	depends on ARCH_OXNAS
+	select IRQ_DOMAIN
+
+ config ARM_NVIC
+ 	bool
+ 	select IRQ_DOMAIN
+Index: linux-3.18-rc4/drivers/irqchip/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/irqchip/Makefile
+++ linux-3.18-rc4/drivers/irqchip/Makefile
+@@ -28,6 +28,7 @@ obj-$(CONFIG_IMGPDC_IRQ)		+= irq-imgpdc.
+ obj-$(CONFIG_SIRF_IRQ)			+= irq-sirfsoc.o
+ obj-$(CONFIG_RENESAS_INTC_IRQPIN)	+= irq-renesas-intc-irqpin.o
+ obj-$(CONFIG_RENESAS_IRQC)		+= irq-renesas-irqc.o
+obj-$(CONFIG_PLXTECH_RPS)		+= irq-rps.o
+ obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o
+ obj-$(CONFIG_ARCH_NSPIRE)		+= irq-zevio.o
+ obj-$(CONFIG_ARCH_VT8500)		+= irq-vt8500.o
+Index: linux-3.18-rc4/drivers/irqchip/irq-gic.c
+===================================================================
+--- linux-3.18-rc4.orig/drivers/irqchip/irq-gic.c
+++ linux-3.18-rc4/drivers/irqchip/irq-gic.c
+@@ -1044,6 +1044,7 @@ IRQCHIP_DECLARE(gic_400, "arm,gic-400",
+ IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
+ IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
+ IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
+IRQCHIP_DECLARE(arm11_mpcore_gic, "arm,arm11mp-gic", gic_of_init);
+ IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
+ IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
+ 
--- a/target/linux/oxnas/patches-3.18/330-oxnas-pinctrl.patch
+++ b/target/linux/oxnas/patches-3.18/330-oxnas-pinctrl.patch
@@ -0,0 +1,32 @@
+Index: linux-3.18-rc4/drivers/pinctrl/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/pinctrl/Kconfig
+++ linux-3.18-rc4/drivers/pinctrl/Kconfig
+@@ -67,6 +67,15 @@ config PINCTRL_AT91
+ 	help
+ 	  Say Y here to enable the at91 pinctrl driver
+ 
+config PINCTRL_OXNAS
+	bool "OXNAS pinctrl driver"
+	depends on OF
+	depends on ARCH_OXNAS
+	select PINMUX
+	select PINCONF
+	help
+	  Say Y here to enable the oxnas pinctrl driver
+
+ config PINCTRL_BAYTRAIL
+ 	bool "Intel Baytrail GPIO pin control"
+ 	depends on GPIOLIB && ACPI && X86
+Index: linux-3.18-rc4/drivers/pinctrl/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/pinctrl/Makefile
+++ linux-3.18-rc4/drivers/pinctrl/Makefile
+@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_BCM2835)	+= pinctrl
+ obj-$(CONFIG_PINCTRL_BAYTRAIL)	+= pinctrl-baytrail.o
+ obj-$(CONFIG_PINCTRL_BCM281XX)	+= pinctrl-bcm281xx.o
+ obj-$(CONFIG_PINCTRL_FALCON)	+= pinctrl-falcon.o
+obj-$(CONFIG_PINCTRL_OXNAS)	+= pinctrl-oxnas.o
+ obj-$(CONFIG_PINCTRL_PALMAS)	+= pinctrl-palmas.o
+ obj-$(CONFIG_PINCTRL_ROCKCHIP)	+= pinctrl-rockchip.o
+ obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o
--- a/target/linux/oxnas/patches-3.18/340-oxnas-pcie.patch
+++ b/target/linux/oxnas/patches-3.18/340-oxnas-pcie.patch
@@ -0,0 +1,26 @@
+Index: linux-3.18-rc4/drivers/pci/host/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/pci/host/Kconfig
+++ linux-3.18-rc4/drivers/pci/host/Kconfig
+@@ -91,4 +91,9 @@ config PCI_XGENE
+ 	  There are 5 internal PCIe ports available. Each port is GEN3 capable
+ 	  and have varied lanes from x1 to x8.
+ 
+config PCI_OXNAS
+	bool "PLX Oxnas PCIe controller"
+	depends on ARCH_OXNAS
+	select PCIEPORTBUS
+
+ endmenu
+Index: linux-3.18-rc4/drivers/pci/host/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/pci/host/Makefile
+++ linux-3.18-rc4/drivers/pci/host/Makefile
+@@ -3,6 +3,7 @@ obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
+ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
+ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
+ obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
+obj-$(CONFIG_PCI_OXNAS) += pcie-oxnas.o
+ obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
+ obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
+ obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o
--- a/target/linux/oxnas/patches-3.18/350-oxnas-reset.patch
+++ b/target/linux/oxnas/patches-3.18/350-oxnas-reset.patch
@@ -0,0 +1,24 @@
+Index: linux-3.18-rc4/drivers/reset/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/reset/Kconfig
+++ linux-3.18-rc4/drivers/reset/Kconfig
+@@ -12,4 +12,9 @@ menuconfig RESET_CONTROLLER
+ 
+ 	  If unsure, say no.
+ 
+config RESET_CONTROLLER_OXNAS
+	bool
+	select RESET_CONTROLLER
+
+ source "drivers/reset/sti/Kconfig"
+
+Index: linux-3.18-rc4/drivers/reset/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/reset/Makefile
+++ linux-3.18-rc4/drivers/reset/Makefile
+@@ -1,4 +1,5 @@
+ obj-$(CONFIG_RESET_CONTROLLER) += core.o
+obj-$(CONFIG_RESET_CONTROLLER_OXNAS) += reset-ox820.o
+ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
+ obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
+ obj-$(CONFIG_ARCH_STI) += sti/
--- a/target/linux/oxnas/patches-3.18/400-oxnas-nand.patch
+++ b/target/linux/oxnas/patches-3.18/400-oxnas-nand.patch
@@ -0,0 +1,28 @@
+Index: linux-3.18-rc4/drivers/mtd/nand/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/mtd/nand/Kconfig
+++ linux-3.18-rc4/drivers/mtd/nand/Kconfig
+@@ -516,4 +516,12 @@ config MTD_NAND_XWAY
+ 	  Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
+ 	  to the External Bus Unit (EBU).
+ 
+config MTD_NAND_OXNAS
+	tristate "Support for NAND on Plxtech NAS782X SoC"
+	depends on ARCH_OXNAS
+	select MTD_NAND_PLATFORM
+	help
+	  Enables support for NAND Flash chips on Plxtech NAS782X SoCs. NAND is attached
+	  to the STATIC Unit.
+
+ endif # MTD_NAND
+Index: linux-3.18-rc4/drivers/mtd/nand/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/mtd/nand/Makefile
+++ linux-3.18-rc4/drivers/mtd/nand/Makefile
+@@ -50,5 +50,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740)		+= jz4740
+ obj-$(CONFIG_MTD_NAND_GPMI_NAND)	+= gpmi-nand/
+ obj-$(CONFIG_MTD_NAND_XWAY)		+= xway_nand.o
+ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash/
+obj-$(CONFIG_MTD_NAND_OXNAS)		+= oxnas_nand.o
+ 
+ nand-objs := nand_base.o nand_bbt.o nand_timings.o
--- a/target/linux/oxnas/patches-3.18/500-oxnas-sata.patch
+++ b/target/linux/oxnas/patches-3.18/500-oxnas-sata.patch
@@ -0,0 +1,30 @@
+Index: linux-3.18-rc4/drivers/ata/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/ata/Kconfig
+++ linux-3.18-rc4/drivers/ata/Kconfig
+@@ -385,6 +385,13 @@ config SATA_VITESSE
+ 
+ 	  If unsure, say N.
+ 
+config SATA_OXNAS
+	tristate "PLXTECH NAS782X SATA support"
+	help
+	  This option enables support for Nas782x Serial ATA controller.
+
+	  If unsure, say N.
+
+ comment "PATA SFF controllers with BMDMA"
+ 
+ config PATA_ALI
+Index: linux-3.18-rc4/drivers/ata/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/ata/Makefile
+++ linux-3.18-rc4/drivers/ata/Makefile
+@@ -37,6 +37,7 @@ obj-$(CONFIG_SATA_SVW)		+= sata_svw.o
+ obj-$(CONFIG_SATA_ULI)		+= sata_uli.o
+ obj-$(CONFIG_SATA_VIA)		+= sata_via.o
+ obj-$(CONFIG_SATA_VITESSE)	+= sata_vsc.o
+obj-$(CONFIG_SATA_OXNAS)	+= sata_oxnas.o
+ 
+ # SFF PATA w/ BMDMA
+ obj-$(CONFIG_PATA_ALI)		+= pata_ali.o
--- a/target/linux/oxnas/patches-3.18/800-oxnas-ehci.patch
+++ b/target/linux/oxnas/patches-3.18/800-oxnas-ehci.patch
@@ -0,0 +1,30 @@
+Index: linux-3.18-rc4/drivers/usb/host/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/usb/host/Kconfig
+++ linux-3.18-rc4/drivers/usb/host/Kconfig
+@@ -302,6 +302,13 @@ config USB_OCTEON_EHCI
+ 	  USB 2.0 device support.  All CN6XXX based chips with USB are
+ 	  supported.
+ 
+config USB_EHCI_OXNAS
+	tristate "OXNAS EHCI Module"
+	depends on USB_EHCI_HCD && ARCH_OXNAS
+	select USB_EHCI_ROOT_HUB_TT
+	---help---
+	  Enable support for the OX820 SOC's on-chip EHCI controller.
+
+ endif # USB_EHCI_HCD
+ 
+ config USB_OXU210HP_HCD
+Index: linux-3.18-rc4/drivers/usb/host/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/usb/host/Makefile
+++ linux-3.18-rc4/drivers/usb/host/Makefile
+@@ -44,6 +44,7 @@ obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-
+ obj-$(CONFIG_USB_EHCI_MSM)	+= ehci-msm.o
+ obj-$(CONFIG_USB_EHCI_TEGRA)	+= ehci-tegra.o
+ obj-$(CONFIG_USB_W90X900_EHCI)	+= ehci-w90x900.o
+obj-$(CONFIG_USB_EHCI_OXNAS)	+= ehci-oxnas.o
+ 
+ obj-$(CONFIG_USB_OXU210HP_HCD)	+= oxu210hp-hcd.o
+ obj-$(CONFIG_USB_ISP116X_HCD)	+= isp116x-hcd.o
--- a/target/linux/oxnas/patches-3.18/900-more-boards.patch
+++ b/target/linux/oxnas/patches-3.18/900-more-boards.patch
@@ -0,0 +1,16 @@
+Index: linux-3.18-rc4/arch/arm/boot/dts/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/boot/dts/Makefile
+++ linux-3.18-rc4/arch/arm/boot/dts/Makefile
+@@ -352,7 +352,10 @@ dtb-$(CONFIG_ARCH_ORION5X) += orion5x-la
+ 	orion5x-lacie-ethernet-disk-mini-v2.dtb \
+ 	orion5x-maxtor-shared-storage-2.dtb \
+ 	orion5x-rd88f5182-nas.dtb
+-dtb-$(CONFIG_ARCH_OXNAS) += ox820-pogoplug-pro.dtb
+dtb-$(CONFIG_ARCH_OXNAS) += ox820-pogoplug-pro.dtb \
+	ox820-pogoplug-v3.dtb \
+	ox820-stg212.dtb \
+	ox820-kd20.dtb
+ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
+ dtb-$(CONFIG_ARCH_QCOM) += \
+ 	qcom-apq8064-cm-qs600.dtb \
--- a/target/linux/oxnas/profiles/100-Generic.mk
+++ b/target/linux/oxnas/profiles/100-Generic.mk
@@ -0,0 +1,53 @@
+#
+# Copyright (C) 2014 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+define Profile/POGOPLUG_PRO
+  NAME:=PogoPlug Pro
+  PACKAGES:= \
+	uboot-envtools kmod-usb2-oxnas
+endef
+
+define Profile/POGOPLUG_PRO/Description
+ Profile with built-in ox820 PogoPlug Pro device-tree
+ (board with miniPCIe slot)
+endef
+
+define Profile/POGOPLUG_V3
+  NAME:=PogoPlug V3
+  PACKAGES:= \
+	uboot-envtools kmod-usb2-oxnas
+endef
+
+define Profile/POGOPLUG_V3/Description
+ Profile with built-in ox820 PogoPlug V3 device-tree
+ (board without miniPCIe slot)
+endef
+
+define Profile/STG212
+  NAME:=MitraStar STG-212
+  PACKAGES:= \
+	uboot-envtools kmod-usb2-oxnas
+endef
+
+define Profile/STG212/Description
+ Profile with built-in ox820 STG-212 device-tree
+endef
+
+define Profile/KD20
+  NAME:=Shuttle KD20
+  PACKAGES:= \
+	uboot-envtools kmod-usb2-oxnas kmod-usb3 kmod-rtc-pcf8563
+endef
+
+define Profile/KD20/Description
+ Profile with built-in ox820 KD20 device-tree
+endef
+
+$(eval $(call Profile,POGOPLUG_PRO))
+$(eval $(call Profile,POGOPLUG_V3))
+$(eval $(call Profile,STG212))
+$(eval $(call Profile,KD20))