kernel: backport MediaTek Ethernet PHY driver
Add support for MediaTek Gigabit Ethernet PHYs found in MT7530 and MT7531. Fix some link up/down issues. The errornous check for the PHY mode which broke things with MT7531 has been removed as suggested by patch net: phy: mediatek: remove PHY mode check on MT7531 As a result, things are working fine now on MT7622+MT7531 as well. Signed-off-by: DENG Qingfang <dqfext@gmail.com> Tested-by: Daniel Golle <daniel@makrotopia.org> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
This commit is contained in:
DENG Qingfang
committed by
Daniel Golle
Daniel Golle
parent
64125ed1d0
commit
73fd9f79ce
@@ -0,0 +1,159 @@
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From e40d2cca01893c1941f5959b14bb0cd0d4f4d099 Mon Sep 17 00:00:00 2001
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From: DENG Qingfang <dqfext@gmail.com>
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Date: Wed, 19 May 2021 11:31:59 +0800
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Subject: [PATCH] net: phy: add MediaTek Gigabit Ethernet PHY driver
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Add support for MediaTek Gigabit Ethernet PHYs found in MT7530 and
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MT7531 switches.
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The initialization procedure is from the vendor driver, but due to lack
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of documentation, the function of some register values remains unknown.
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Signed-off-by: DENG Qingfang <dqfext@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/phy/Kconfig | 5 ++
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drivers/net/phy/Makefile | 1 +
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drivers/net/phy/mediatek-ge.c | 116 ++++++++++++++++++++++++++++++++++
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3 files changed, 122 insertions(+)
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create mode 100644 drivers/net/phy/mediatek-ge.c
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -201,6 +201,11 @@ config MARVELL_10G_PHY
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help
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Support for the Marvell Alaska MV88X3310 and compatible PHYs.
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+config MEDIATEK_GE_PHY
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+ tristate "MediaTek PHYs"
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+ help
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+ Supports the MediaTek switch integrated PHYs.
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+
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config MICREL_PHY
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tristate "Micrel PHYs"
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help
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--- a/drivers/net/phy/Makefile
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+++ b/drivers/net/phy/Makefile
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@@ -63,6 +63,7 @@ obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c
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obj-$(CONFIG_LXT_PHY) += lxt.o
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obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o
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obj-$(CONFIG_MARVELL_PHY) += marvell.o
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+obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
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obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
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obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
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obj-$(CONFIG_MICREL_PHY) += micrel.o
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--- /dev/null
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+++ b/drivers/net/phy/mediatek-ge.c
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@@ -0,0 +1,113 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+#include <linux/bitfield.h>
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+#include <linux/module.h>
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+#include <linux/phy.h>
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+
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+#define MTK_T10_TEST_CONTROL 0x145
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+#define MTK_PHY_TP_MASK GENMASK(4, 3)
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+#define MTK_PHY_TP_AUTO 0
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+#define MTK_PHY_TP_MDI 2
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+#define MTK_PHY_TP_MDIX 3
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+
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+#define MTK_EXT_PAGE_ACCESS 0x1f
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+#define MTK_PHY_PAGE_STANDARD 0x0000
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+#define MTK_PHY_PAGE_EXTENDED 0x0001
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+#define MTK_PHY_PAGE_EXTENDED_2 0x0002
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+#define MTK_PHY_PAGE_EXTENDED_3 0x0003
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+#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
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+#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
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+
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+static int mtk_gephy_read_page(struct phy_device *phydev)
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+{
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+ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
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+}
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+
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+static int mtk_gephy_write_page(struct phy_device *phydev, int page)
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+{
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+ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
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+}
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+
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+static void mtk_gephy_config_init(struct phy_device *phydev)
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+{
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+ /* Disable EEE */
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+ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
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+
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+ /* Enable HW auto downshift */
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+ phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
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+
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+ /* Increase SlvDPSready time */
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+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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+ __phy_write(phydev, 0x10, 0xafae);
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+ __phy_write(phydev, 0x12, 0x2f);
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+ __phy_write(phydev, 0x10, 0x8fae);
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+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
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+
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+ /* Adjust 100_mse_threshold */
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
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+
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+ /* Disable mcc */
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
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+}
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+
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+static int mt7530_phy_config_init(struct phy_device *phydev)
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+{
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+ mtk_gephy_config_init(phydev);
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+
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+ /* Increase post_update_timer */
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+ phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
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+
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+ return 0;
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+}
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+
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+static int mt7531_phy_config_init(struct phy_device *phydev)
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+{
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+ mtk_gephy_config_init(phydev);
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+
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+ /* PHY link down power saving enable */
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+ phy_set_bits(phydev, 0x17, BIT(4));
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+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
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+
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+ /* Set TX Pair delay selection */
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
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+
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+ return 0;
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+}
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+
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+static struct phy_driver mtk_gephy_driver[] = {
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+ {
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+ PHY_ID_MATCH_EXACT(0x03a29412),
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+ .name = "MediaTek MT7530 PHY",
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+ .config_init = mt7530_phy_config_init,
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+ /* Interrupts are handled by the switch, not the PHY
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+ * itself.
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+ */
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+ .config_intr = genphy_no_config_intr,
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+ .ack_interrupt = genphy_no_ack_interrupt,
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+ .suspend = genphy_suspend,
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+ .resume = genphy_resume,
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+ .read_page = mtk_gephy_read_page,
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+ .write_page = mtk_gephy_write_page,
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+ },
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+ {
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+ PHY_ID_MATCH_EXACT(0x03a29441),
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+ .name = "MediaTek MT7531 PHY",
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+ .config_init = mt7531_phy_config_init,
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+ /* Interrupts are handled by the switch, not the PHY
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+ * itself.
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+ */
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+ .config_intr = genphy_no_config_intr,
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+ .ack_interrupt = genphy_no_ack_interrupt,
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+ .suspend = genphy_suspend,
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+ .resume = genphy_resume,
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+ .read_page = mtk_gephy_read_page,
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+ .write_page = mtk_gephy_write_page,
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+ },
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+};
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+
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+module_phy_driver(mtk_gephy_driver);
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+
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+static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
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+ { PHY_ID_MATCH_VENDOR(0x03a29400) },
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+ { }
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+};
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@@ -3181,6 +3181,7 @@ CONFIG_MAY_USE_DEVLINK=y
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# CONFIG_MDIO_THUNDER is not set
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# CONFIG_MDIO_XPCS is not set
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# CONFIG_MD_FAULTY is not set
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# CONFIG_MEDIATEK_GE_PHY is not set
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# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
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# CONFIG_MEDIA_ATTACH is not set
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# CONFIG_MEDIA_CAMERA_SUPPORT is not set
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@@ -228,6 +228,7 @@ CONFIG_MAGIC_SYSRQ=y
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CONFIG_MDIO_BUS=y
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CONFIG_MDIO_DEVICE=y
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CONFIG_MDIO_DEVRES=y
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CONFIG_MEDIATEK_GE_PHY=y
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CONFIG_MEDIATEK_MT6577_AUXADC=y
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CONFIG_MEDIATEK_WATCHDOG=y
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CONFIG_MEMFD_CREATE=y
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@@ -368,6 +368,7 @@ CONFIG_MDIO_BUS=y
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CONFIG_MDIO_DEVICE=y
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CONFIG_MDIO_DEVRES=y
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CONFIG_MDIO_GPIO=y
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CONFIG_MEDIATEK_GE_PHY=y
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CONFIG_MEDIATEK_MT6577_AUXADC=y
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CONFIG_MEDIATEK_WATCHDOG=y
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CONFIG_MEMFD_CREATE=y
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@@ -114,6 +114,7 @@ CONFIG_LZO_COMPRESS=y
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CONFIG_LZO_DECOMPRESS=y
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CONFIG_MDIO_BUS=y
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CONFIG_MDIO_DEVICE=y
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CONFIG_MEDIATEK_GE_PHY=y
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CONFIG_MEMFD_CREATE=y
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CONFIG_MFD_SYSCON=y
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CONFIG_MIGRATION=y
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