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change danube 2 ifxmips

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SVN-Revision: 9821
This commit is contained in:
John Crispin
2007-12-22 00:17:22 +00:00
parent 285395cfca
commit 7af3296c76
31 changed files with 1846 additions and 1845 deletions
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234
target/linux/ifxmips/files/include/asm-mips/danube/danube.h
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@@ -17,13 +17,13 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_H__
#define _DANUBE_H__
#ifndef _IFXMIPS_H__
#define _IFXMIPS_H__
/*------------ GENERAL */
#define BOARD_SYSTEM_TYPE "DANUBE"
#define BOARD_SYSTEM_TYPE "IFXMIPS"
#define IOPORT_RESOURCE_START 0x10000000
#define IOPORT_RESOURCE_END 0xffffffff
@@ -33,15 +33,15 @@
/*------------ ASC1 */
#define DANUBE_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00)
#define IFXMIPS_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00)
/* FIFO status register */
#define DANUBE_ASC1_FSTAT ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0048))
#define IFXMIPS_ASC1_FSTAT ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0048))
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
/* ASC1 transmit buffer */
#define DANUBE_ASC1_TBUF ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0020))
#define IFXMIPS_ASC1_TBUF ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0020))
/* channel operating modes */
#define ASCOPT_CSIZE 0x3
@@ -53,43 +53,43 @@
#define ASCOPT_CREAD 0x20
/* hardware modified control register */
#define DANUBE_ASC1_WHBSTATE ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0018))
#define IFXMIPS_ASC1_WHBSTATE ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0018))
/* receive buffer register */
#define DANUBE_ASC1_RBUF ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0024))
#define IFXMIPS_ASC1_RBUF ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0024))
/* status register */
#define DANUBE_ASC1_STATE ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0014))
#define IFXMIPS_ASC1_STATE ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0014))
/* interrupt control */
#define DANUBE_ASC1_IRNCR ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F8))
#define IFXMIPS_ASC1_IRNCR ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F8))
#define ASC_IRNCR_TIR 0x4
#define ASC_IRNCR_RIR 0x2
#define ASC_IRNCR_EIR 0x4
/* clock control */
#define DANUBE_ASC1_CLC ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0000))
#define IFXMIPS_ASC1_CLC ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0000))
#define DANUBE_ASC1_CLC_DISS 0x2
#define IFXMIPS_ASC1_CLC_DISS 0x2
/* port input select register */
#define DANUBE_ASC1_PISEL ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0004))
#define IFXMIPS_ASC1_PISEL ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0004))
/* tx fifo */
#define DANUBE_ASC1_TXFCON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0044))
#define IFXMIPS_ASC1_TXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0044))
/* rx fifo */
#define DANUBE_ASC1_RXFCON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0040))
#define IFXMIPS_ASC1_RXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0040))
/* control */
#define DANUBE_ASC1_CON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0010))
#define IFXMIPS_ASC1_CON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0010))
/* timer reload */
#define DANUBE_ASC1_BG ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0050))
#define IFXMIPS_ASC1_BG ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0050))
/* int enable */
#define DANUBE_ASC1_IRNREN ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F4))
#define IFXMIPS_ASC1_IRNREN ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F4))
#define ASC_IRNREN_RX_BUF 0x8
#define ASC_IRNREN_TX_BUF 0x4
@@ -99,54 +99,54 @@
/*------------ RCU */
#define DANUBE_RCU_BASE_ADDR 0xBF203000
#define IFXMIPS_RCU_BASE_ADDR 0xBF203000
/* reset request */
#define DANUBE_RCU_REQ ((u32*)(DANUBE_RCU_BASE_ADDR + 0x0010))
#define DANUBE_RST_ALL 0x40000000
#define IFXMIPS_RCU_REQ ((u32*)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
#define IFXMIPS_RST_ALL 0x40000000
/*------------ MCD */
#define DANUBE_MCD_BASE_ADDR (KSEG1 + 0x1F106000)
#define IFXMIPS_MCD_BASE_ADDR (KSEG1 + 0x1F106000)
/* chip id */
#define DANUBE_MCD_CHIPID ((u32*)(DANUBE_MCD_BASE_ADDR + 0x0028))
#define IFXMIPS_MCD_CHIPID ((u32*)(IFXMIPS_MCD_BASE_ADDR + 0x0028))
/*------------ GPTU */
#define DANUBE_GPTU_BASE_ADDR 0xB8000300
#define IFXMIPS_GPTU_BASE_ADDR 0xB8000300
/* clock control register */
#define DANUBE_GPTU_GPT_CLC ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0000))
#define IFXMIPS_GPTU_GPT_CLC ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0000))
/* captur reload register */
#define DANUBE_GPTU_GPT_CAPREL ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0030))
#define IFXMIPS_GPTU_GPT_CAPREL ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0030))
/* timer 6 control register */
#define DANUBE_GPTU_GPT_T6CON ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0020))
#define IFXMIPS_GPTU_GPT_T6CON ((u32*)(IFXMIPS_GPTU_BASE_ADDR + 0x0020))
/*------------ EBU */
#define DANUBE_EBU_BASE_ADDR 0xBE105300
#define IFXMIPS_EBU_BASE_ADDR 0xBE105300
/* bus configuration register */
#define DANUBE_EBU_BUSCON0 ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0060))
#define DANUBE_EBU_PCC_CON ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0090))
#define DANUBE_EBU_PCC_IEN ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A4))
#define DANUBE_EBU_PCC_ISTAT ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A0))
#define IFXMIPS_EBU_BUSCON0 ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0060))
#define IFXMIPS_EBU_PCC_CON ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x0090))
#define IFXMIPS_EBU_PCC_IEN ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A4))
#define IFXMIPS_EBU_PCC_ISTAT ((u32*)(IFXMIPS_EBU_BASE_ADDR + 0x00A0))
/*------------ CGU */
#define DANUBE_CGU_BASE_ADDR 0xBF103000
#define IFXMIPS_CGU_BASE_ADDR 0xBF103000
/* clock mux */
#define DANUBE_CGU_SYS ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0010))
#define DANUBE_CGU_IFCCR ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0018))
#define DANUBE_CGU_PCICR ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0034))
#define IFXMIPS_CGU_SYS ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
#define IFXMIPS_CGU_IFCCR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
#define IFXMIPS_CGU_PCICR ((u32*)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
#define CLOCK_60M 60000000
#define CLOCK_83M 83333333
@@ -158,42 +158,42 @@
/*------------ CGU */
#define DANUBE_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
#define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
#define DANUBE_PMU_PWDCR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x001C))
#define DANUBE_PMU_PWDSR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x0020))
#define IFXMIPS_PMU_PWDCR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x001C))
#define IFXMIPS_PMU_PWDSR ((u32*)(IFXMIPS_PMU_BASE_ADDR + 0x0020))
/*------------ ICU */
#define DANUBE_ICU_BASE_ADDR 0xBF880200
#define IFXMIPS_ICU_BASE_ADDR 0xBF880200
#define DANUBE_ICU_IM0_ISR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0000))
#define DANUBE_ICU_IM0_IER ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0008))
#define DANUBE_ICU_IM0_IOSR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0010))
#define DANUBE_ICU_IM0_IRSR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0018))
#define DANUBE_ICU_IM0_IMR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0020))
#define IFXMIPS_ICU_IM0_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0000))
#define IFXMIPS_ICU_IM0_IER ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0008))
#define IFXMIPS_ICU_IM0_IOSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0010))
#define IFXMIPS_ICU_IM0_IRSR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0018))
#define IFXMIPS_ICU_IM0_IMR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0020))
#define DANUBE_ICU_IM1_ISR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0028))
#define IFXMIPS_ICU_IM1_ISR ((u32*)(IFXMIPS_ICU_BASE_ADDR + 0x0028))
#define DANUBE_ICU_OFFSET (DANUBE_ICU_IM1_ISR - DANUBE_ICU_IM0_ISR)
#define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR)
/*------------ ETOP */
#define DANUBE_PPE32_BASE_ADDR 0xBE180000
#define IFXMIPS_PPE32_BASE_ADDR 0xBE180000
#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600
#define DANUBE_PPE32_MEM_MAP (DANUBE_PPE32_BASE_ADDR + 0x10000 )
#define IFXMIPS_PPE32_MEM_MAP (IFXMIPS_PPE32_BASE_ADDR + 0x10000 )
#define MII_MODE 1
#define REV_MII_MODE 2
/* mdio access */
#define DANUBE_PPE32_MDIO_ACC ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1804))
#define IFXMIPS_PPE32_MDIO_ACC ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1804))
#define MDIO_ACC_REQUEST 0x80000000
#define MDIO_ACC_READ 0x40000000
@@ -204,38 +204,38 @@
#define MDIO_ACC_VAL_MASK 0xffff
/* configuration */
#define DANUBE_PPE32_CFG ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1808))
#define IFXMIPS_PPE32_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1808))
#define PPE32_MII_MASK 0xfffffffc
#define PPE32_MII_NORMAL 0x8
#define PPE32_MII_REVERSE 0xe
/* packet length */
#define DANUBE_PPE32_IG_PLEN_CTRL ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1820))
#define IFXMIPS_PPE32_IG_PLEN_CTRL ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1820))
#define PPE32_PLEN_OVER 0x5ee
#define PPE32_PLEN_UNDER 0x400000
/* enet */
#define DANUBE_PPE32_ENET_MAC_CFG ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1840))
#define IFXMIPS_PPE32_ENET_MAC_CFG ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1840))
#define PPE32_CGEN 0x800
/*------------ DMA */
#define DANUBE_DMA_BASE_ADDR 0xBE104100
#define IFXMIPS_DMA_BASE_ADDR 0xBE104100
#define DANUBE_DMA_CS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x18))
#define DANUBE_DMA_CIE ((u32*)(DANUBE_DMA_BASE_ADDR + 0x2C))
#define DANUBE_DMA_IRNEN ((u32*)(DANUBE_DMA_BASE_ADDR + 0xf4))
#define DANUBE_DMA_CCTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x1C))
#define DANUBE_DMA_CIS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x28))
#define DANUBE_DMA_CDLEN ((u32*)(DANUBE_DMA_BASE_ADDR + 0x24))
#define DANUBE_DMA_PS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x40))
#define DANUBE_DMA_PCTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x44))
#define DANUBE_DMA_CTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x10))
#define DANUBE_DMA_CPOLL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x14))
#define DANUBE_DMA_CDBA ((u32*)(DANUBE_DMA_BASE_ADDR + 0x20))
#define IFXMIPS_DMA_CS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x18))
#define IFXMIPS_DMA_CIE ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x2C))
#define IFXMIPS_DMA_IRNEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0xf4))
#define IFXMIPS_DMA_CCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x1C))
#define IFXMIPS_DMA_CIS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x28))
#define IFXMIPS_DMA_CDLEN ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x24))
#define IFXMIPS_DMA_PS ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x40))
#define IFXMIPS_DMA_PCTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x44))
#define IFXMIPS_DMA_CTRL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x10))
#define IFXMIPS_DMA_CPOLL ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x14))
#define IFXMIPS_DMA_CDBA ((u32*)(IFXMIPS_DMA_BASE_ADDR + 0x20))
/*------------ PCI */
@@ -273,82 +273,82 @@
/*------------ WDT */
#define DANUBE_WDT_BASE_ADDR (KSEG1 + 0x1F880000)
#define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000)
#define DANUBE_BIU_WDT_CR ((u32*)(DANUBE_WDT_BASE_ADDR + 0x03F0))
#define DANUBE_BIU_WDT_SR ((u32*)(DANUBE_WDT_BASE_ADDR + 0x03F8))
#define IFXMIPS_BIU_WDT_CR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F0))
#define IFXMIPS_BIU_WDT_SR ((u32*)(IFXMIPS_WDT_BASE_ADDR + 0x03F8))
#define DANUBE_BIU_WDT_CR_GEN (1 << 31)
#define DANUBE_BIU_WDT_CR_DSEN (1 << 30)
#define DANUBE_BIU_WDT_CR_LPEN (1 << 29)
#define IFXMIPS_BIU_WDT_CR_GEN (1 << 31)
#define IFXMIPS_BIU_WDT_CR_DSEN (1 << 30)
#define IFXMIPS_BIU_WDT_CR_LPEN (1 << 29)
#define DANUBE_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
#define DANUBE_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1))
#define DANUBE_BIU_WDT_CR_PWL_SET(value) ((((1 << 2) - 1) & (value)) << 26)
#define DANUBE_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16)
#define DANUBE_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
#define DANUBE_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
#define IFXMIPS_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
#define IFXMIPS_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1))
#define IFXMIPS_BIU_WDT_CR_PWL_SET(value) ((((1 << 2) - 1) & (value)) << 26)
#define IFXMIPS_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16)
#define IFXMIPS_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
#define IFXMIPS_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
/*------------ LED */
#define DANUBE_LED_BASE_ADDR (KSEG1 + 0x1E100BB0)
#define DANUBE_LED_CON0 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0000))
#define DANUBE_LED_CON1 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0004))
#define DANUBE_LED_CPU0 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0008))
#define DANUBE_LED_CPU1 ((u32*)(DANUBE_LED_BASE_ADDR + 0x000C))
#define DANUBE_LED_AR ((u32*)(DANUBE_LED_BASE_ADDR + 0x0010))
#define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0)
#define IFXMIPS_LED_CON0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0000))
#define IFXMIPS_LED_CON1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0004))
#define IFXMIPS_LED_CPU0 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0008))
#define IFXMIPS_LED_CPU1 ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x000C))
#define IFXMIPS_LED_AR ((u32*)(IFXMIPS_LED_BASE_ADDR + 0x0010))
#define LED_CON0_SWU (1 << 31)
#define LED_CON0_AD1 (1 << 25)
#define LED_CON0_AD0 (1 << 24)
#define DANUBE_LED_2HZ (0)
#define DANUBE_LED_4HZ (1 << 23)
#define DANUBE_LED_8HZ (2 << 23)
#define DANUBE_LED_10HZ (3 << 23)
#define DANUBE_LED_MASK (0xf << 23)
#define IFXMIPS_LED_2HZ (0)
#define IFXMIPS_LED_4HZ (1 << 23)
#define IFXMIPS_LED_8HZ (2 << 23)
#define IFXMIPS_LED_10HZ (3 << 23)
#define IFXMIPS_LED_MASK (0xf << 23)
#define DANUBE_LED_UPD_SRC_FPI (1 << 31)
#define DANUBE_LED_UPD_MASK (3 << 30)
#define DANUBE_LED_ADSL_SRC (3 << 24)
#define IFXMIPS_LED_UPD_SRC_FPI (1 << 31)
#define IFXMIPS_LED_UPD_MASK (3 << 30)
#define IFXMIPS_LED_ADSL_SRC (3 << 24)
#define DANUBE_LED_GROUP0 (1 << 0)
#define DANUBE_LED_GROUP1 (1 << 1)
#define DANUBE_LED_GROUP2 (1 << 2)
#define IFXMIPS_LED_GROUP0 (1 << 0)
#define IFXMIPS_LED_GROUP1 (1 << 1)
#define IFXMIPS_LED_GROUP2 (1 << 2)
#define DANUBE_LED_RISING 0
#define DANUBE_LED_FALLING (1 << 26)
#define DANUBE_LED_EDGE_MASK (1 << 26)
#define IFXMIPS_LED_RISING 0
#define IFXMIPS_LED_FALLING (1 << 26)
#define IFXMIPS_LED_EDGE_MASK (1 << 26)
/*------------ GPIO */
#define DANUBE_GPIO_BASE_ADDR (0xBE100B00)
#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
#define DANUBE_GPIO_P0_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0010))
#define DANUBE_GPIO_P1_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0040))
#define DANUBE_GPIO_P0_IN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0014))
#define DANUBE_GPIO_P1_IN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0044))
#define DANUBE_GPIO_P0_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0018))
#define DANUBE_GPIO_P1_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0048))
#define DANUBE_GPIO_P0_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x001C))
#define DANUBE_GPIO_P1_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x004C))
#define DANUBE_GPIO_P0_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0020))
#define DANUBE_GPIO_P1_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0050))
#define DANUBE_GPIO_P0_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0024))
#define DANUBE_GPIO_P1_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0054))
#define DANUBE_GPIO_P0_STOFF ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0028))
#define DANUBE_GPIO_P1_STOFF ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0058))
#define DANUBE_GPIO_P0_PUDSEL ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x002C))
#define DANUBE_GPIO_P1_PUDSEL ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x005C))
#define DANUBE_GPIO_P0_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0030))
#define DANUBE_GPIO_P1_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0060))
#define IFXMIPS_GPIO_P0_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
#define IFXMIPS_GPIO_P1_OUT ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
#define IFXMIPS_GPIO_P0_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
#define IFXMIPS_GPIO_P1_IN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
#define IFXMIPS_GPIO_P0_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
#define IFXMIPS_GPIO_P1_DIR ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
#define IFXMIPS_GPIO_P0_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
#define IFXMIPS_GPIO_P1_OD ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
#define IFXMIPS_GPIO_P0_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
#define IFXMIPS_GPIO_P1_STOFF ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
#define IFXMIPS_GPIO_P0_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
#define IFXMIPS_GPIO_P1_PUDSEL ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
#define IFXMIPS_GPIO_P0_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
#define IFXMIPS_GPIO_P1_PUDEN ((u32*)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
/*------------ SSC */
#define DANUBE_SSC1_BASE_ADDR (KSEG1 + 0x1e100800)
#define IFXMIPS_SSC1_BASE_ADDR (KSEG1 + 0x1e100800)

16
target/linux/ifxmips/files/include/asm-mips/danube/danube_dma.h
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@@ -17,15 +17,15 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_DMA_H__
#define _DANUBE_DMA_H__
#ifndef _IFXMIPS_DMA_H__
#define _IFXMIPS_DMA_H__
#define RCV_INT 1
#define TX_BUF_FULL_INT 2
#define TRANSMIT_CPT_INT 4
#define DANUBE_DMA_CH_ON 1
#define DANUBE_DMA_CH_OFF 0
#define DANUBE_DMA_CH_DEFAULT_WEIGHT 100
#define IFXMIPS_DMA_CH_ON 1
#define IFXMIPS_DMA_CH_OFF 0
#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT 100
enum attr_t{
TX = 0,
@@ -53,8 +53,8 @@ enum attr_t{
#define DMA_DROP_MASK (1<<31)
#define DANUBE_DMA_RX -1
#define DANUBE_DMA_TX 1
#define IFXMIPS_DMA_RX -1
#define IFXMIPS_DMA_TX 1
typedef struct dma_chan_map {
char dev_name[15];
@@ -151,7 +151,7 @@ typedef struct dma_channel_info{
/*on or off of this channel*/
int control;
/**optional information for the upper layer devices*/
#if defined(CONFIG_DANUBE_ETHERNET_D2) || defined(CONFIG_DANUBE_PPA)
#if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA)
void* opt[64];
#else
void* opt[25];

4
target/linux/ifxmips/files/include/asm-mips/danube/danube_gpio.h
View File

@@ -16,8 +16,8 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_GPIO_H__
#define _DANUBE_GPIO_H__
#ifndef _IFXMIPS_GPIO_H__
#define _IFXMIPS_GPIO_H__
extern int danube_port_reserve_pin (unsigned int port, unsigned int pin);
extern int danube_port_free_pin (unsigned int port, unsigned int pin);

24
target/linux/ifxmips/files/include/asm-mips/danube/danube_ioctl.h
View File

@@ -16,8 +16,8 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_IOCTL_H__
#define _DANUBE_IOCTL_H__
#ifndef _IFXMIPS_IOCTL_H__
#define _IFXMIPS_IOCTL_H__
/*------------ LED */
@@ -28,15 +28,15 @@ struct danube_port_ioctl_parm
int value;
};
#define DANUBE_PORT_IOC_MAGIC 0xbf
#define DANUBE_PORT_IOCOD _IOW(DANUBE_PORT_IOC_MAGIC,0,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCPUDSEL _IOW(DANUBE_PORT_IOC_MAGIC,1,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCPUDEN _IOW(DANUBE_PORT_IOC_MAGIC,2,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCSTOFF _IOW(DANUBE_PORT_IOC_MAGIC,3,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCDIR _IOW(DANUBE_PORT_IOC_MAGIC,4,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCOUTPUT _IOW(DANUBE_PORT_IOC_MAGIC,5,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCINPUT _IOWR(DANUBE_PORT_IOC_MAGIC,6,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCALTSEL0 _IOW(DANUBE_PORT_IOC_MAGIC,7,struct danube_port_ioctl_parm)
#define DANUBE_PORT_IOCALTSEL1 _IOW(DANUBE_PORT_IOC_MAGIC,8,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOC_MAGIC 0xbf
#define IFXMIPS_PORT_IOCOD _IOW(IFXMIPS_PORT_IOC_MAGIC,0,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCPUDSEL _IOW(IFXMIPS_PORT_IOC_MAGIC,1,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCPUDEN _IOW(IFXMIPS_PORT_IOC_MAGIC,2,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCSTOFF _IOW(IFXMIPS_PORT_IOC_MAGIC,3,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCDIR _IOW(IFXMIPS_PORT_IOC_MAGIC,4,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCOUTPUT _IOW(IFXMIPS_PORT_IOC_MAGIC,5,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCINPUT _IOWR(IFXMIPS_PORT_IOC_MAGIC,6,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCALTSEL0 _IOW(IFXMIPS_PORT_IOC_MAGIC,7,struct danube_port_ioctl_parm)
#define IFXMIPS_PORT_IOCALTSEL1 _IOW(IFXMIPS_PORT_IOC_MAGIC,8,struct danube_port_ioctl_parm)
#endif

58
target/linux/ifxmips/files/include/asm-mips/danube/danube_irq.h
View File

@@ -17,8 +17,8 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_IRQ__
#define _DANUBE_IRQ__
#ifndef _IFXMIPS_IRQ__
#define _IFXMIPS_IRQ__
#define INT_NUM_IRQ0 8
#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
@@ -28,38 +28,38 @@
#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
#define DANUBEASC1_TIR (INT_NUM_IM3_IRL0 + 7)
#define DANUBEASC1_RIR (INT_NUM_IM3_IRL0 + 9)
#define DANUBEASC1_EIR (INT_NUM_IM3_IRL0 + 10)
#define IFXMIPSASC1_TIR (INT_NUM_IM3_IRL0 + 7)
#define IFXMIPSASC1_RIR (INT_NUM_IM3_IRL0 + 9)
#define IFXMIPSASC1_EIR (INT_NUM_IM3_IRL0 + 10)
#define DANUBE_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
#define DANUBE_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
#define DANUBE_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
#define IFXMIPS_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
#define IFXMIPS_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
#define IFXMIPS_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
#define DANUBE_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
#define IFXMIPS_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
#define MIPS_CPU_TIMER_IRQ 7
#define DANUBE_DMA_CH0_INT (INT_NUM_IM2_IRL0)
#define DANUBE_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
#define DANUBE_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
#define DANUBE_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
#define DANUBE_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
#define DANUBE_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
#define DANUBE_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
#define DANUBE_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
#define DANUBE_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
#define DANUBE_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
#define DANUBE_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
#define DANUBE_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
#define DANUBE_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
#define DANUBE_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
#define DANUBE_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
#define DANUBE_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
#define DANUBE_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
#define DANUBE_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
#define DANUBE_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
#define DANUBE_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
#define IFXMIPS_DMA_CH0_INT (INT_NUM_IM2_IRL0)
#define IFXMIPS_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
#define IFXMIPS_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
#define IFXMIPS_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
#define IFXMIPS_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
#define IFXMIPS_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
#define IFXMIPS_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
#define IFXMIPS_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
#define IFXMIPS_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
#define IFXMIPS_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
#define IFXMIPS_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
#define IFXMIPS_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
#define IFXMIPS_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
#define IFXMIPS_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
#define IFXMIPS_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
#define IFXMIPS_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
#define IFXMIPS_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
#define IFXMIPS_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
#define IFXMIPS_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
#define IFXMIPS_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
extern void mask_and_ack_danube_irq (unsigned int irq_nr);

8
target/linux/ifxmips/files/include/asm-mips/danube/danube_mii0.h
View File

@@ -1,5 +1,5 @@
#ifndef DANUBE_SW_H
#define DANUBE_SW_H
#ifndef IFXMIPS_SW_H
#define IFXMIPS_SW_H
@@ -138,7 +138,7 @@
#define PHY1_ADDR 1
#define P1M 0
#define DANUBE_SW_REG32(reg_num) *((volatile u32*)(reg_num))
#define IFXMIPS_SW_REG32(reg_num) *((volatile u32*)(reg_num))
#define OK 0;
@@ -251,4 +251,4 @@ struct switch_priv {
enum duplex current_duplex;
};
#endif //DANUBE_SW_H
#endif //IFXMIPS_SW_H

2342
target/linux/ifxmips/files/include/asm-mips/danube/danube_orig.h
View File

File diff suppressed because it is too large Load Diff

14
target/linux/ifxmips/files/include/asm-mips/danube/danube_pmu.h
View File

@@ -16,14 +16,14 @@
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
*
*/
#ifndef _DANUBE_PMU_H__
#define _DANUBE_PMU_H__
#ifndef _IFXMIPS_PMU_H__
#define _IFXMIPS_PMU_H__
#define DANUBE_PMU_PWDCR_DMA 0x20
#define DANUBE_PMU_PWDCR_LED 0x800
#define DANUBE_PMU_PWDCR_GPT 0x1000
#define DANUBE_PMU_PWDCR_PPE 0x2000
#define DANUBE_PMU_PWDCR_FPI 0x4000
#define IFXMIPS_PMU_PWDCR_DMA 0x20
#define IFXMIPS_PMU_PWDCR_LED 0x800
#define IFXMIPS_PMU_PWDCR_GPT 0x1000
#define IFXMIPS_PMU_PWDCR_PPE 0x2000
#define IFXMIPS_PMU_PWDCR_FPI 0x4000
void danube_pmu_enable (unsigned int module);
void danube_pmu_disable (unsigned int module);

36
target/linux/ifxmips/files/include/asm-mips/danube/danube_serial.h
View File

@@ -1,7 +1,7 @@
/* incaAscSio.h - (DANUBE) ASC UART tty driver header */
/* incaAscSio.h - (IFXMIPS) ASC UART tty driver header */
#ifndef __DANUBE_ASC_H
#define __DANUBE_ASC_H
#ifndef __IFXMIPS_ASC_H
#define __IFXMIPS_ASC_H
/******************************************************************************
**
@@ -41,29 +41,29 @@
/* ASC input select (0 or 1) */
#define CONSOLE_TTY 0
#define DANUBEASC_TXFIFO_FL 1
#define DANUBEASC_RXFIFO_FL 1
#define DANUBEASC_TXFIFO_FULL 16
#define IFXMIPSASC_TXFIFO_FL 1
#define IFXMIPSASC_RXFIFO_FL 1
#define IFXMIPSASC_TXFIFO_FULL 16
/* interrupt lines masks for the ASC device interrupts*/
/* change these macroses if it's necessary */
#define DANUBEASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
#define IFXMIPSASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
#define DANUBEASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
#define DANUBEASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
#define DANUBEASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
#define DANUBEASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
#define DANUBEASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
#define DANUBEASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
#define DANUBEASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
#define IFXMIPSASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
#define IFXMIPSASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
#define IFXMIPSASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
#define IFXMIPSASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
#define IFXMIPSASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
#define IFXMIPSASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
#define IFXMIPSASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
/* interrupt controller access macros */
#define ASC_INTERRUPTS_ENABLE(X) \
*((volatile unsigned int*) DANUBE_ICU_IM0_IER) |= X;
*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) |= X;
#define ASC_INTERRUPTS_DISABLE(X) \
*((volatile unsigned int*) DANUBE_ICU_IM0_IER) &= ~X;
*((volatile unsigned int*) IFXMIPS_ICU_IM0_IER) &= ~X;
#define ASC_INTERRUPTS_CLEAR(X) \
*((volatile unsigned int*) DANUBE_ICU_IM0_ISR) = X;
*((volatile unsigned int*) IFXMIPS_ICU_IM0_ISR) = X;
/* CLC register's bits and bitfields */
#define ASCCLC_DISR 0x00000001
@@ -191,4 +191,4 @@
#define ASCFSTAT_TXFFLMASK 0x3F00
#define ASCFSTAT_TXFFLOFF 8
#endif /* __DANUBE_ASC_H */
#endif /* __IFXMIPS_ASC_H */

42
target/linux/ifxmips/files/include/asm-mips/danube/danube_wdt.h
View File

@@ -18,31 +18,31 @@
*
*/
#ifndef DANUBE_WDT_H
#define DANUBE_WDT_H
#ifndef IFXMIPS_WDT_H
#define IFXMIPS_WDT_H
/* Danube wdt ioctl control */
#define DANUBE_WDT_IOC_MAGIC 0xc0
#define DANUBE_WDT_IOC_START _IOW(DANUBE_WDT_IOC_MAGIC, 0, int)
#define DANUBE_WDT_IOC_STOP _IO(DANUBE_WDT_IOC_MAGIC, 1)
#define DANUBE_WDT_IOC_PING _IO(DANUBE_WDT_IOC_MAGIC, 2)
#define DANUBE_WDT_IOC_SET_PWL _IOW(DANUBE_WDT_IOC_MAGIC, 3, int)
#define DANUBE_WDT_IOC_SET_DSEN _IOW(DANUBE_WDT_IOC_MAGIC, 4, int)
#define DANUBE_WDT_IOC_SET_LPEN _IOW(DANUBE_WDT_IOC_MAGIC, 5, int)
#define DANUBE_WDT_IOC_GET_STATUS _IOR(DANUBE_WDT_IOC_MAGIC, 6, int)
#define DANUBE_WDT_IOC_SET_CLKDIV _IOW(DANUBE_WDT_IOC_MAGIC, 7, int)
#define IFXMIPS_WDT_IOC_MAGIC 0xc0
#define IFXMIPS_WDT_IOC_START _IOW(IFXMIPS_WDT_IOC_MAGIC, 0, int)
#define IFXMIPS_WDT_IOC_STOP _IO(IFXMIPS_WDT_IOC_MAGIC, 1)
#define IFXMIPS_WDT_IOC_PING _IO(IFXMIPS_WDT_IOC_MAGIC, 2)
#define IFXMIPS_WDT_IOC_SET_PWL _IOW(IFXMIPS_WDT_IOC_MAGIC, 3, int)
#define IFXMIPS_WDT_IOC_SET_DSEN _IOW(IFXMIPS_WDT_IOC_MAGIC, 4, int)
#define IFXMIPS_WDT_IOC_SET_LPEN _IOW(IFXMIPS_WDT_IOC_MAGIC, 5, int)
#define IFXMIPS_WDT_IOC_GET_STATUS _IOR(IFXMIPS_WDT_IOC_MAGIC, 6, int)
#define IFXMIPS_WDT_IOC_SET_CLKDIV _IOW(IFXMIPS_WDT_IOC_MAGIC, 7, int)
/* password 1 and 2 */
#define DANUBE_WDT_PW1 0x000000BE
#define DANUBE_WDT_PW2 0x000000DC
#define IFXMIPS_WDT_PW1 0x000000BE
#define IFXMIPS_WDT_PW2 0x000000DC
#define DANUBE_WDT_CLKDIV0_VAL 1
#define DANUBE_WDT_CLKDIV1_VAL 64
#define DANUBE_WDT_CLKDIV2_VAL 4096
#define DANUBE_WDT_CLKDIV3_VAL 262144
#define DANUBE_WDT_CLKDIV0 0
#define DANUBE_WDT_CLKDIV1 1
#define DANUBE_WDT_CLKDIV2 2
#define DANUBE_WDT_CLKDIV3 3
#define IFXMIPS_WDT_CLKDIV0_VAL 1
#define IFXMIPS_WDT_CLKDIV1_VAL 64
#define IFXMIPS_WDT_CLKDIV2_VAL 4096
#define IFXMIPS_WDT_CLKDIV3_VAL 262144
#define IFXMIPS_WDT_CLKDIV0 0
#define IFXMIPS_WDT_CLKDIV1 1
#define IFXMIPS_WDT_CLKDIV2 2
#define IFXMIPS_WDT_CLKDIV3 3
#endif

4
target/linux/ifxmips/files/include/asm-mips/mach-danube/irq.h
View File

@@ -1,5 +1,5 @@
#ifndef __DANUBE_IRQ_H
#define __DANUBE_IRQ_H
#ifndef __IFXMIPS_IRQ_H
#define __IFXMIPS_IRQ_H
#define NR_IRQS 256
#include_next <irq.h>