provide an early ioremap cookie of the system configuration register
SVN-Revision: 32489
This commit is contained in:
		| @@ -16,6 +16,8 @@ | |||||||
|  |  | ||||||
| #include <mach/mcs814x.h> | #include <mach/mcs814x.h> | ||||||
|  |  | ||||||
|  | #include "common.h" | ||||||
|  |  | ||||||
| #define KHZ	1000 | #define KHZ	1000 | ||||||
| #define MHZ	(KHZ * KHZ) | #define MHZ	(KHZ * KHZ) | ||||||
|  |  | ||||||
| @@ -32,7 +34,7 @@ struct clk { | |||||||
| 	unsigned long divider;		/* clock divider */ | 	unsigned long divider;		/* clock divider */ | ||||||
| 	u32 usecount;			/* reference count */ | 	u32 usecount;			/* reference count */ | ||||||
| 	struct clk_ops *ops;		/* clock operation */ | 	struct clk_ops *ops;		/* clock operation */ | ||||||
| 	void __iomem *enable_reg;	/* clock enable register */ | 	u32 enable_reg;			/* clock enable register */ | ||||||
| 	u32 enable_mask;		/* clock enable mask */ | 	u32 enable_mask;		/* clock enable mask */ | ||||||
| }; | }; | ||||||
|  |  | ||||||
| @@ -52,13 +54,13 @@ static int clk_local_onoff_enable(struct clk *clk, int enable) | |||||||
| 	if (!clk->enable_reg) | 	if (!clk->enable_reg) | ||||||
| 		return 0; | 		return 0; | ||||||
|  |  | ||||||
| 	tmp = __raw_readl(clk->enable_reg); | 	tmp = __raw_readl(mcs814x_sysdbg_base + clk->enable_reg); | ||||||
| 	if (!enable) | 	if (!enable) | ||||||
| 		tmp &= ~clk->enable_mask; | 		tmp &= ~clk->enable_mask; | ||||||
| 	else | 	else | ||||||
| 		tmp |= clk->enable_mask; | 		tmp |= clk->enable_mask; | ||||||
|  |  | ||||||
| 	__raw_writel(tmp, clk->enable_reg); | 	__raw_writel(tmp, mcs814x_sysdbg_base + clk->enable_reg); | ||||||
|  |  | ||||||
| 	return 0; | 	return 0; | ||||||
| } | } | ||||||
| @@ -117,19 +119,19 @@ static struct clk clk_wdt = { | |||||||
|  |  | ||||||
| static struct clk clk_emac = { | static struct clk clk_emac = { | ||||||
| 	.ops		= &default_clk_ops, | 	.ops		= &default_clk_ops, | ||||||
| 	.enable_reg	= (void __iomem *)(_CONFADDR_SYSDBG + SYSDBG_SYSCTL), | 	.enable_reg	= SYSDBG_SYSCTL, | ||||||
| 	.enable_mask	= SYSCTL_EMAC, | 	.enable_mask	= SYSCTL_EMAC, | ||||||
| }; | }; | ||||||
|  |  | ||||||
| static struct clk clk_ephy = { | static struct clk clk_ephy = { | ||||||
| 	.ops		= &default_clk_ops, | 	.ops		= &default_clk_ops, | ||||||
| 	.enable_reg	= (void __iomem *)(_CONFADDR_SYSDBG + SYSDBG_PLL_CTL), | 	.enable_reg	= SYSDBG_PLL_CTL, | ||||||
| 	.enable_mask	= ~(1 << 0), | 	.enable_mask	= ~SYSCTL_EPHY,	/* active low */ | ||||||
| }; | }; | ||||||
|  |  | ||||||
| static struct clk clk_cipher = { | static struct clk clk_cipher = { | ||||||
| 	.ops		= &default_clk_ops, | 	.ops		= &default_clk_ops, | ||||||
| 	.enable_reg	= (void __iomem *)(_CONFADDR_SYSDBG + SYSDBG_SYSCTL), | 	.enable_reg	= SYSDBG_SYSCTL, | ||||||
| 	.enable_mask	= SYSCTL_CIPHER, | 	.enable_mask	= SYSCTL_CIPHER, | ||||||
| }; | }; | ||||||
|  |  | ||||||
| @@ -252,7 +254,7 @@ void __init mcs814x_clk_init(void) | |||||||
| 	clkdev_add_table(mcs814x_chip_clks, ARRAY_SIZE(mcs814x_chip_clks)); | 	clkdev_add_table(mcs814x_chip_clks, ARRAY_SIZE(mcs814x_chip_clks)); | ||||||
|  |  | ||||||
| 	/* read the bootstrap registers to know the exact clocking scheme */ | 	/* read the bootstrap registers to know the exact clocking scheme */ | ||||||
| 	bs1 = __raw_readl(_CONFADDR_SYSDBG + SYSDBG_BS1); | 	bs1 = __raw_readl(mcs814x_sysdbg_base + SYSDBG_BS1); | ||||||
| 	cpu_freq = (bs1 >> CPU_FREQ_SHIFT) & CPU_FREQ_MASK; | 	cpu_freq = (bs1 >> CPU_FREQ_SHIFT) & CPU_FREQ_MASK; | ||||||
|  |  | ||||||
| 	pr_info("CPU frequency: %lu (kHz)\n", cpu_freq_table[cpu_freq]); | 	pr_info("CPU frequency: %lu (kHz)\n", cpu_freq_table[cpu_freq]); | ||||||
|   | |||||||
| @@ -23,6 +23,8 @@ | |||||||
| #include <asm/pgtable.h> | #include <asm/pgtable.h> | ||||||
| #include <asm/mach/map.h> | #include <asm/mach/map.h> | ||||||
|  |  | ||||||
|  | void __iomem *mcs814x_sysdbg_base; | ||||||
|  |  | ||||||
| static struct map_desc mcs814x_io_desc[] __initdata = { | static struct map_desc mcs814x_io_desc[] __initdata = { | ||||||
| 	{ | 	{ | ||||||
| 		.virtual	= MCS814X_IO_BASE, | 		.virtual	= MCS814X_IO_BASE, | ||||||
| @@ -65,34 +67,34 @@ static void mcs814x_eth_hardware_filter_set(u8 value) | |||||||
| { | { | ||||||
| 	u32 reg; | 	u32 reg; | ||||||
|  |  | ||||||
| 	reg = __raw_readl(_CONFADDR_DBGLED); | 	reg = __raw_readl(MCS814X_VIRT_BASE + MCS814X_DBGLED); | ||||||
| 	if (value) | 	if (value) | ||||||
| 		reg |= 0x80; | 		reg |= 0x80; | ||||||
| 	else | 	else | ||||||
| 		reg &= ~0x80; | 		reg &= ~0x80; | ||||||
| 	__raw_writel(reg, _CONFADDR_DBGLED); | 	__raw_writel(reg, MCS814X_VIRT_BASE + MCS814X_DBGLED); | ||||||
| } | } | ||||||
|  |  | ||||||
| static void mcs814x_eth_led_cfg_set(u8 cfg) | static void mcs814x_eth_led_cfg_set(u8 cfg) | ||||||
| { | { | ||||||
| 	u32 reg; | 	u32 reg; | ||||||
|  |  | ||||||
| 	reg = __raw_readl(_CONFADDR_SYSDBG + SYSDBG_BS2); | 	reg = __raw_readl(mcs814x_sysdbg_base + SYSDBG_BS2); | ||||||
| 	reg &= ~LED_CFG_MASK; | 	reg &= ~LED_CFG_MASK; | ||||||
| 	reg |= cfg; | 	reg |= cfg; | ||||||
| 	__raw_writel(reg, _CONFADDR_SYSDBG + SYSDBG_BS2); | 	__raw_writel(reg, mcs814x_sysdbg_base + SYSDBG_BS2); | ||||||
| } | } | ||||||
|  |  | ||||||
| static void mcs814x_eth_buffer_shifting_set(u8 value) | static void mcs814x_eth_buffer_shifting_set(u8 value) | ||||||
| { | { | ||||||
| 	u8 reg; | 	u8 reg; | ||||||
|  |  | ||||||
| 	reg = __raw_readb(_CONFADDR_SYSDBG + SYSDBG_SYSCTL_MAC); | 	reg = __raw_readb(mcs814x_sysdbg_base + SYSDBG_SYSCTL_MAC); | ||||||
| 	if (value) | 	if (value) | ||||||
| 		reg |= BUF_SHIFT_BIT; | 		reg |= BUF_SHIFT_BIT; | ||||||
| 	else | 	else | ||||||
| 		reg &= ~BUF_SHIFT_BIT; | 		reg &= ~BUF_SHIFT_BIT; | ||||||
| 	__raw_writeb(reg, _CONFADDR_SYSDBG + SYSDBG_SYSCTL_MAC); | 	__raw_writeb(reg, mcs814x_sysdbg_base + SYSDBG_SYSCTL_MAC); | ||||||
| } | } | ||||||
|  |  | ||||||
| static struct of_device_id mcs814x_eth_ids[] __initdata = { | static struct of_device_id mcs814x_eth_ids[] __initdata = { | ||||||
| @@ -130,7 +132,7 @@ void __init mcs814x_init_machine(void) | |||||||
| 	u32 bs2, cpu_mode; | 	u32 bs2, cpu_mode; | ||||||
| 	int gpio; | 	int gpio; | ||||||
|  |  | ||||||
| 	bs2 = __raw_readl(_CONFADDR_SYSDBG + SYSDBG_BS2); | 	bs2 = __raw_readl(mcs814x_sysdbg_base + SYSDBG_BS2); | ||||||
| 	cpu_mode = (bs2 >> CPU_MODE_SHIFT) & CPU_MODE_MASK; | 	cpu_mode = (bs2 >> CPU_MODE_SHIFT) & CPU_MODE_MASK; | ||||||
|  |  | ||||||
| 	pr_info("CPU mode: %s\n", cpu_modes[cpu_mode].name); | 	pr_info("CPU mode: %s\n", cpu_modes[cpu_mode].name); | ||||||
| @@ -148,9 +150,14 @@ void __init mcs814x_init_machine(void) | |||||||
| void __init mcs814x_map_io(void) | void __init mcs814x_map_io(void) | ||||||
| { | { | ||||||
| 	iotable_init(mcs814x_io_desc, ARRAY_SIZE(mcs814x_io_desc)); | 	iotable_init(mcs814x_io_desc, ARRAY_SIZE(mcs814x_io_desc)); | ||||||
|  |  | ||||||
|  | 	mcs814x_sysdbg_base = ioremap(MCS814X_IO_START + MCS814X_SYSDBG, | ||||||
|  | 					MCS814X_SYSDBG_SIZE); | ||||||
|  | 	if (!mcs814x_sysdbg_base) | ||||||
|  | 		panic("unable to remap sysdbg base"); | ||||||
| } | } | ||||||
|  |  | ||||||
| void mcs814x_restart(char mode, const char *cmd) | void mcs814x_restart(char mode, const char *cmd) | ||||||
| { | { | ||||||
| 	__raw_writel(~(1 << 31), _CONFADDR_SYSDBG); | 	__raw_writel(~(1 << 31), mcs814x_sysdbg_base); | ||||||
| } | } | ||||||
|   | |||||||
| @@ -10,5 +10,6 @@ void mcs814x_init_machine(void); | |||||||
| void mcs814x_handle_irq(struct pt_regs *regs); | void mcs814x_handle_irq(struct pt_regs *regs); | ||||||
| void mcs814x_restart(char mode, const char *cmd); | void mcs814x_restart(char mode, const char *cmd); | ||||||
| extern struct sys_timer mcs814x_timer; | extern struct sys_timer mcs814x_timer; | ||||||
|  | extern void __iomem *mcs814x_sysdbg_base; | ||||||
|  |  | ||||||
| #endif /* __ARCH_MCS814X_COMMON_H */ | #endif /* __ARCH_MCS814X_COMMON_H */ | ||||||
|   | |||||||
| @@ -1,10 +1,10 @@ | |||||||
| #include <mach/mcs814x.h> | #include <mach/mcs814x.h> | ||||||
|  |  | ||||||
|                 .macro  addruart, rp, rv, tmp |                 .macro  addruart, rp, rv, tmp | ||||||
| 		ldr	\rp, =_PHYS_CONFADDR | 		ldr	\rp, =MCS814X_PHYS_BASE | ||||||
| 		ldr	\rv, =_VIRT_CONFADDR | 		ldr	\rv, =MCS814X_VIRT_BASE | ||||||
| 		orr	\rp, \rp, #_CONFOFFSET_UART | 		orr	\rp, \rp, #MCS814X_UART | ||||||
| 		orr	\rv, \rv, #_CONFOFFSET_UART | 		orr	\rv, \rv, #MCS814X_UART | ||||||
|                 .endm |                 .endm | ||||||
|  |  | ||||||
| #define UART_SHIFT	2 | #define UART_SHIFT	2 | ||||||
|   | |||||||
| @@ -20,15 +20,13 @@ | |||||||
| #define MCS814X_IRQ_MASK	0x20 | #define MCS814X_IRQ_MASK	0x20 | ||||||
| #define MCS814X_IRQ_STS0	0x40 | #define MCS814X_IRQ_STS0	0x40 | ||||||
|  |  | ||||||
| #define _PHYS_CONFADDR		0x40000000 | #define MCS814X_PHYS_BASE	0x40000000 | ||||||
| #define _VIRT_CONFADDR		MCS814X_IO_BASE | #define MCS814X_VIRT_BASE	MCS814X_IO_BASE | ||||||
|  |  | ||||||
| #define _CONFOFFSET_UART    0x000DC000 | #define MCS814X_UART    	0x000DC000 | ||||||
| #define _CONFOFFSET_DBGLED  0x000EC000 | #define MCS814X_DBGLED  	0x000EC000 | ||||||
| #define _CONFOFFSET_SYSDBG  0x000F8000 | #define MCS814X_SYSDBG  	0x000F8000 | ||||||
|  | #define MCS814X_SYSDBG_SIZE	0x50 | ||||||
| #define _CONFADDR_DBGLED  (_VIRT_CONFADDR + _CONFOFFSET_DBGLED) |  | ||||||
| #define _CONFADDR_SYSDBG  (_VIRT_CONFADDR + _CONFOFFSET_SYSDBG) |  | ||||||
|  |  | ||||||
| /* System configuration and bootstrap registers */ | /* System configuration and bootstrap registers */ | ||||||
| #define SYSDBG_BS1		0x00 | #define SYSDBG_BS1		0x00 | ||||||
| @@ -46,6 +44,7 @@ | |||||||
|  |  | ||||||
| #define SYSDBG_SYSCTL		0x08 | #define SYSDBG_SYSCTL		0x08 | ||||||
| #define  SYSCTL_EMAC		(1 << 0) | #define  SYSCTL_EMAC		(1 << 0) | ||||||
|  | #define  SYSCTL_EPHY		(1 << 1) /* active low */ | ||||||
| #define  SYSCTL_CIPHER		(1 << 16) | #define  SYSCTL_CIPHER		(1 << 16) | ||||||
|  |  | ||||||
| #define SYSDBG_PLL_CTL		0x3C | #define SYSDBG_PLL_CTL		0x3C | ||||||
|   | |||||||
| @@ -32,7 +32,7 @@ static inline void flush(void) | |||||||
| static inline void arch_decomp_setup(void) | static inline void arch_decomp_setup(void) | ||||||
| { | { | ||||||
| 	if (soc_is_mcs8140()) | 	if (soc_is_mcs8140()) | ||||||
| 		uart_base = (void __iomem *)(_PHYS_CONFADDR + _CONFOFFSET_UART); | 		uart_base = (void __iomem *)(MCS814X_PHYS_BASE +MCS814X_UART); | ||||||
| } | } | ||||||
|  |  | ||||||
| #define arch_decomp_wdog() | #define arch_decomp_wdog() | ||||||
|   | |||||||
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	 Florian Fainelli
					Florian Fainelli