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ipq806x: fix pcie tx termination offset

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According to GPL tarballs and QSDK related branch tx termination
offset for ipq8064 SoC version >= 2.0 should be equal to 0 and
not 7.

https://github.com/paul-chambers/netgear-r7800/blob/master/git_home/linux.git/sourcecode/arch/arm/mach-msm/board-ipq806x.c#L1682-L1685

Fix this.

Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
[slh: rebase for kernel v4.14 as well]
Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>

(cherry picked from commit fbedc2213c)
This commit is contained in:
Pavel Kubelun
2018-01-18 13:51:25 +03:00
committed by John Crispin
parent a64a36308c
commit 8458febc01
2 changed files with 24 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
target/linux/ipq806x/files-4.14/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
View File

@@ -14,5 +14,17 @@
tx_deamp_3_5db = <32>; tx_deamp_3_5db = <32>;
mpll = <0xa0>; mpll = <0xa0>;
}; };
pcie0: pci@1b500000 {
phy-tx0-term-offset = <0>;
};
pcie1: pci@1b700000 {
phy-tx0-term-offset = <0>;
};
pcie2: pci@1b900000 {
phy-tx0-term-offset = <0>;
};
}; };
}; };

12
target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
View File

@@ -14,5 +14,17 @@
tx_deamp_3_5db = <32>; tx_deamp_3_5db = <32>;
mpll = <0xa0>; mpll = <0xa0>;
}; };
pcie0: pci@1b500000 {
phy-tx0-term-offset = <0>;
};
pcie1: pci@1b700000 {
phy-tx0-term-offset = <0>;
};
pcie2: pci@1b900000 {
phy-tx0-term-offset = <0>;
};
}; };
}; };