adds dsl support, thank you infineon/lantiq
SVN-Revision: 18259
This commit is contained in:
John Crispin
3
package/ifxmips-dsl-api/src/Makefile
Normal file
3
package/ifxmips-dsl-api/src/Makefile
Normal file
@@ -0,0 +1,3 @@
|
||||
obj-m = ifxmips_mei.o ifxmips_atm.o
|
||||
|
||||
ifxmips_atm-objs := ifxmips_atm_core.o ifxmips_atm_danube.o
|
||||
172
package/ifxmips-dsl-api/src/ifx_atm.h
Normal file
172
package/ifxmips-dsl-api/src/ifx_atm.h
Normal file
@@ -0,0 +1,172 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifx_atm.h
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM
|
||||
**
|
||||
** DATE : 17 Jun 2009
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : Global ATM driver header file
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 07 JUL 2009 Xu Liang Init Version
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef IFX_ATM_H
|
||||
#define IFX_ATM_H
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
\defgroup IFX_ATM UEIP Project - ATM driver module
|
||||
\brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
|
||||
*/
|
||||
|
||||
/*!
|
||||
\defgroup IFX_ATM_IOCTL IOCTL Commands
|
||||
\ingroup IFX_ATM
|
||||
\brief IOCTL Commands used by user application.
|
||||
*/
|
||||
|
||||
/*!
|
||||
\defgroup IFX_ATM_STRUCT Structures
|
||||
\ingroup IFX_ATM
|
||||
\brief Structures used by user application.
|
||||
*/
|
||||
|
||||
/*!
|
||||
\file ifx_atm.h
|
||||
\ingroup IFX_ATM
|
||||
\brief ATM driver header file
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Definition
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
\addtogroup IFX_ATM_STRUCT
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/*
|
||||
* ATM MIB
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
__u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
|
||||
__u32 ifInErrors; /*!< counter of error ingress cells */
|
||||
__u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
|
||||
__u32 ifOutErrors; /*!< counter of error egress cells */
|
||||
} atm_cell_ifEntry_t;
|
||||
|
||||
typedef struct {
|
||||
__u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
|
||||
__u32 ifInUcastPkts; /*!< counter of ingress packets */
|
||||
__u32 ifOutUcastPkts; /*!< counter of egress packets */
|
||||
__u32 ifInErrors; /*!< counter of error ingress packets */
|
||||
__u32 ifInDiscards; /*!< counter of dropped ingress packets */
|
||||
__u32 ifOutErros; /*!< counter of error egress packets */
|
||||
__u32 ifOutDiscards; /*!< counter of dropped egress packets */
|
||||
} atm_aal5_ifEntry_t;
|
||||
|
||||
typedef struct {
|
||||
__u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
|
||||
__u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
|
||||
__u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
|
||||
} atm_aal5_vcc_t;
|
||||
|
||||
typedef struct {
|
||||
int vpi; /*!< VPI of the VCC to get MIB counters */
|
||||
int vci; /*!< VCI of the VCC to get MIB counters */
|
||||
atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
|
||||
} atm_aal5_vcc_x_t;
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* IOCTL
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
\addtogroup IFX_ATM_IOCTL
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/*
|
||||
* ioctl Command
|
||||
*/
|
||||
/*!
|
||||
\brief ATM IOCTL Magic Number
|
||||
*/
|
||||
#define PPE_ATM_IOC_MAGIC 'o'
|
||||
/*!
|
||||
\brief ATM IOCTL Command - Get Cell Level MIB Counters
|
||||
|
||||
This command is obsolete. User can get cell level MIB from DSL API.
|
||||
This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
|
||||
*/
|
||||
#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
|
||||
/*!
|
||||
\brief ATM IOCTL Command - Get AAL5 Level MIB Counters
|
||||
|
||||
Get AAL5 packet counters.
|
||||
This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
|
||||
*/
|
||||
#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
|
||||
/*!
|
||||
\brief ATM IOCTL Command - Get Per PVC MIB Counters
|
||||
|
||||
Get AAL5 packet counters for each PVC.
|
||||
This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
|
||||
*/
|
||||
#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
|
||||
/*!
|
||||
\brief Total Number of ATM IOCTL Commands
|
||||
*/
|
||||
#define PPE_ATM_IOC_MAXNR 3
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* API
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
#ifdef __KERNEL__
|
||||
struct port_cell_info {
|
||||
unsigned int port_num;
|
||||
unsigned int tx_link_rate[2];
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif // IFX_ATM_H
|
||||
|
||||
172
package/ifxmips-dsl-api/src/ifxmips_atm.h
Normal file
172
package/ifxmips-dsl-api/src/ifxmips_atm.h
Normal file
@@ -0,0 +1,172 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifx_atm.h
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM
|
||||
**
|
||||
** DATE : 17 Jun 2009
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : Global ATM driver header file
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 07 JUL 2009 Xu Liang Init Version
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef IFX_ATM_H
|
||||
#define IFX_ATM_H
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
\defgroup IFX_ATM UEIP Project - ATM driver module
|
||||
\brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
|
||||
*/
|
||||
|
||||
/*!
|
||||
\defgroup IFX_ATM_IOCTL IOCTL Commands
|
||||
\ingroup IFX_ATM
|
||||
\brief IOCTL Commands used by user application.
|
||||
*/
|
||||
|
||||
/*!
|
||||
\defgroup IFX_ATM_STRUCT Structures
|
||||
\ingroup IFX_ATM
|
||||
\brief Structures used by user application.
|
||||
*/
|
||||
|
||||
/*!
|
||||
\file ifx_atm.h
|
||||
\ingroup IFX_ATM
|
||||
\brief ATM driver header file
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Definition
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
\addtogroup IFX_ATM_STRUCT
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/*
|
||||
* ATM MIB
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
__u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
|
||||
__u32 ifInErrors; /*!< counter of error ingress cells */
|
||||
__u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
|
||||
__u32 ifOutErrors; /*!< counter of error egress cells */
|
||||
} atm_cell_ifEntry_t;
|
||||
|
||||
typedef struct {
|
||||
__u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
|
||||
__u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
|
||||
__u32 ifInUcastPkts; /*!< counter of ingress packets */
|
||||
__u32 ifOutUcastPkts; /*!< counter of egress packets */
|
||||
__u32 ifInErrors; /*!< counter of error ingress packets */
|
||||
__u32 ifInDiscards; /*!< counter of dropped ingress packets */
|
||||
__u32 ifOutErros; /*!< counter of error egress packets */
|
||||
__u32 ifOutDiscards; /*!< counter of dropped egress packets */
|
||||
} atm_aal5_ifEntry_t;
|
||||
|
||||
typedef struct {
|
||||
__u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
|
||||
__u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
|
||||
__u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
|
||||
} atm_aal5_vcc_t;
|
||||
|
||||
typedef struct {
|
||||
int vpi; /*!< VPI of the VCC to get MIB counters */
|
||||
int vci; /*!< VCI of the VCC to get MIB counters */
|
||||
atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
|
||||
} atm_aal5_vcc_x_t;
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* IOCTL
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
\addtogroup IFX_ATM_IOCTL
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/*
|
||||
* ioctl Command
|
||||
*/
|
||||
/*!
|
||||
\brief ATM IOCTL Magic Number
|
||||
*/
|
||||
#define PPE_ATM_IOC_MAGIC 'o'
|
||||
/*!
|
||||
\brief ATM IOCTL Command - Get Cell Level MIB Counters
|
||||
|
||||
This command is obsolete. User can get cell level MIB from DSL API.
|
||||
This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
|
||||
*/
|
||||
#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
|
||||
/*!
|
||||
\brief ATM IOCTL Command - Get AAL5 Level MIB Counters
|
||||
|
||||
Get AAL5 packet counters.
|
||||
This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
|
||||
*/
|
||||
#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
|
||||
/*!
|
||||
\brief ATM IOCTL Command - Get Per PVC MIB Counters
|
||||
|
||||
Get AAL5 packet counters for each PVC.
|
||||
This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
|
||||
*/
|
||||
#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
|
||||
/*!
|
||||
\brief Total Number of ATM IOCTL Commands
|
||||
*/
|
||||
#define PPE_ATM_IOC_MAXNR 3
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* API
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
#ifdef __KERNEL__
|
||||
struct port_cell_info {
|
||||
unsigned int port_num;
|
||||
unsigned int tx_link_rate[2];
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif // IFX_ATM_H
|
||||
|
||||
2507
package/ifxmips-dsl-api/src/ifxmips_atm_core.c
Normal file
2507
package/ifxmips-dsl-api/src/ifxmips_atm_core.c
Normal file
File diff suppressed because it is too large
Load Diff
249
package/ifxmips-dsl-api/src/ifxmips_atm_core.h
Normal file
249
package/ifxmips-dsl-api/src/ifxmips_atm_core.h
Normal file
@@ -0,0 +1,249 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_atm_core.h
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM
|
||||
**
|
||||
** DATE : 7 Jul 2009
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : ATM driver header file (core functions)
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 17 JUN 2009 Xu Liang Init Version
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef IFXMIPS_ATM_CORE_H
|
||||
#define IFXMIPS_ATM_CORE_H
|
||||
|
||||
|
||||
|
||||
#include <asm/ifx/ifx_atm.h>
|
||||
#include "ifxmips_atm_ppe_common.h"
|
||||
#include "ifxmips_atm_fw_regs_common.h"
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Definition
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* Compile Options
|
||||
*/
|
||||
|
||||
#define ENABLE_DEBUG 1
|
||||
|
||||
#define ENABLE_ASSERT 1
|
||||
|
||||
#define INLINE
|
||||
|
||||
#define DEBUG_DUMP_SKB 1
|
||||
|
||||
#define DEBUG_QOS 1
|
||||
|
||||
#define ENABLE_DBG_PROC 1
|
||||
|
||||
#define ENABLE_FW_PROC 1
|
||||
|
||||
#ifdef CONFIG_IFX_ATM_TASKLET
|
||||
#define ENABLE_TASKLET 1
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Debug/Assert/Error Message
|
||||
*/
|
||||
|
||||
#define DBG_ENABLE_MASK_ERR (1 << 0)
|
||||
#define DBG_ENABLE_MASK_DEBUG_PRINT (1 << 1)
|
||||
#define DBG_ENABLE_MASK_ASSERT (1 << 2)
|
||||
#define DBG_ENABLE_MASK_DUMP_SKB_RX (1 << 8)
|
||||
#define DBG_ENABLE_MASK_DUMP_SKB_TX (1 << 9)
|
||||
#define DBG_ENABLE_MASK_DUMP_QOS (1 << 10)
|
||||
#define DBG_ENABLE_MASK_DUMP_INIT (1 << 11)
|
||||
#define DBG_ENABLE_MASK_ALL (DBG_ENABLE_MASK_ERR | DBG_ENABLE_MASK_DEBUG_PRINT | DBG_ENABLE_MASK_ASSERT | DBG_ENABLE_MASK_DUMP_SKB_RX | DBG_ENABLE_MASK_DUMP_SKB_TX | DBG_ENABLE_MASK_DUMP_QOS | DBG_ENABLE_MASK_DUMP_INIT)
|
||||
|
||||
#define err(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ERR) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
|
||||
|
||||
#if defined(ENABLE_DEBUG) && ENABLE_DEBUG
|
||||
#undef dbg
|
||||
#define dbg(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT) ) printk(KERN_WARNING __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
|
||||
#else
|
||||
#if !defined(dbg)
|
||||
#define dbg(format, arg...)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(ENABLE_ASSERT) && ENABLE_ASSERT
|
||||
#define ASSERT(cond, format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ASSERT) && !(cond) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 )
|
||||
#else
|
||||
#define ASSERT(cond, format, arg...)
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Constants
|
||||
*/
|
||||
#define DEFAULT_TX_LINK_RATE 3200 // in cells
|
||||
|
||||
/*
|
||||
* ATM Port, QSB Queue, DMA RX/TX Channel Parameters
|
||||
*/
|
||||
#define ATM_PORT_NUMBER 2
|
||||
#define MAX_QUEUE_NUMBER 16
|
||||
#define OAM_RX_QUEUE 15
|
||||
#define QSB_RESERVE_TX_QUEUE 0
|
||||
#define FIRST_QSB_QID 1
|
||||
#define MAX_PVC_NUMBER (MAX_QUEUE_NUMBER - FIRST_QSB_QID)
|
||||
#define MAX_RX_DMA_CHANNEL_NUMBER 8
|
||||
#define MAX_TX_DMA_CHANNEL_NUMBER 16
|
||||
#define DATA_BUFFER_ALIGNMENT EMA_ALIGNMENT
|
||||
#define DESC_ALIGNMENT 8
|
||||
#define DEFAULT_RX_HUNT_BITTH 4
|
||||
|
||||
/*
|
||||
* RX DMA Channel Allocation
|
||||
*/
|
||||
#define RX_DMA_CH_OAM 0
|
||||
#define RX_DMA_CH_AAL 1
|
||||
#define RX_DMA_CH_TOTAL 2
|
||||
#define RX_DMA_CH_OAM_DESC_LEN 32
|
||||
#define RX_DMA_CH_OAM_BUF_SIZE (CELL_SIZE & ~15)
|
||||
#define RX_DMA_CH_AAL_BUF_SIZE (2048 - 48)
|
||||
|
||||
/*
|
||||
* OAM Constants
|
||||
*/
|
||||
#define OAM_HTU_ENTRY_NUMBER 3
|
||||
#define OAM_F4_SEG_HTU_ENTRY 0
|
||||
#define OAM_F4_TOT_HTU_ENTRY 1
|
||||
#define OAM_F5_HTU_ENTRY 2
|
||||
#define OAM_F4_CELL_ID 0
|
||||
#define OAM_F5_CELL_ID 15
|
||||
//#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
|
||||
// #undef OAM_HTU_ENTRY_NUMBER
|
||||
// #define OAM_HTU_ENTRY_NUMBER 4
|
||||
// #define OAM_ARQ_HTU_ENTRY 3
|
||||
//#endif
|
||||
|
||||
/*
|
||||
* RX Frame Definitions
|
||||
*/
|
||||
#define MAX_RX_PACKET_ALIGN_BYTES 3
|
||||
#define MAX_RX_PACKET_PADDING_BYTES 3
|
||||
#define RX_INBAND_TRAILER_LENGTH 8
|
||||
#define MAX_RX_FRAME_EXTRA_BYTES (RX_INBAND_TRAILER_LENGTH + MAX_RX_PACKET_ALIGN_BYTES + MAX_RX_PACKET_PADDING_BYTES)
|
||||
|
||||
/*
|
||||
* TX Frame Definitions
|
||||
*/
|
||||
#define MAX_TX_HEADER_ALIGN_BYTES 12
|
||||
#define MAX_TX_PACKET_ALIGN_BYTES 3
|
||||
#define MAX_TX_PACKET_PADDING_BYTES 3
|
||||
#define TX_INBAND_HEADER_LENGTH 8
|
||||
#define MAX_TX_FRAME_EXTRA_BYTES (TX_INBAND_HEADER_LENGTH + MAX_TX_HEADER_ALIGN_BYTES + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES)
|
||||
|
||||
/*
|
||||
* Cell Constant
|
||||
*/
|
||||
#define CELL_SIZE ATM_AAL0_SDU
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Data Type
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
unsigned int h;
|
||||
unsigned int l;
|
||||
} ppe_u64_t;
|
||||
|
||||
struct port {
|
||||
unsigned int tx_max_cell_rate;
|
||||
unsigned int tx_current_cell_rate;
|
||||
|
||||
struct atm_dev *dev;
|
||||
};
|
||||
|
||||
struct connection {
|
||||
struct atm_vcc *vcc;
|
||||
|
||||
volatile struct tx_descriptor
|
||||
*tx_desc;
|
||||
unsigned int tx_desc_pos;
|
||||
struct sk_buff **tx_skb;
|
||||
|
||||
unsigned int aal5_vcc_crc_err; /* number of packets with CRC error */
|
||||
unsigned int aal5_vcc_oversize_sdu; /* number of packets with oversize error */
|
||||
|
||||
unsigned int port;
|
||||
};
|
||||
|
||||
struct atm_priv_data {
|
||||
unsigned long conn_table;
|
||||
struct connection conn[MAX_PVC_NUMBER];
|
||||
|
||||
volatile struct rx_descriptor
|
||||
*aal_desc;
|
||||
unsigned int aal_desc_pos;
|
||||
|
||||
volatile struct rx_descriptor
|
||||
*oam_desc;
|
||||
unsigned char *oam_buf;
|
||||
unsigned int oam_desc_pos;
|
||||
|
||||
struct port port[ATM_PORT_NUMBER];
|
||||
|
||||
unsigned int wrx_pdu; /* successfully received AAL5 packet */
|
||||
unsigned int wrx_drop_pdu; /* AAL5 packet dropped by driver on RX */
|
||||
unsigned int wtx_pdu; /* successfully tranmitted AAL5 packet */
|
||||
unsigned int wtx_err_pdu; /* error AAL5 packet */
|
||||
unsigned int wtx_drop_pdu; /* AAL5 packet dropped by driver on TX */
|
||||
|
||||
ppe_u64_t wrx_total_byte;
|
||||
ppe_u64_t wtx_total_byte;
|
||||
unsigned int prev_wrx_total_byte;
|
||||
unsigned int prev_wtx_total_byte;
|
||||
|
||||
void *aal_desc_base;
|
||||
void *oam_desc_base;
|
||||
void *oam_buf_base;
|
||||
void *tx_desc_base;
|
||||
void *tx_skb_base;
|
||||
};
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Declaration
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
extern unsigned int ifx_atm_dbg_enable;
|
||||
|
||||
extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor);
|
||||
|
||||
extern void ifx_atm_init_chip(void);
|
||||
extern void ifx_atm_uninit_chip(void);
|
||||
|
||||
extern int ifx_pp32_start(int pp32);
|
||||
extern void ifx_pp32_stop(int pp32);
|
||||
|
||||
|
||||
|
||||
#endif // IFXMIPS_ATM_CORE_H
|
||||
272
package/ifxmips-dsl-api/src/ifxmips_atm_danube.c
Normal file
272
package/ifxmips-dsl-api/src/ifxmips_atm_danube.c
Normal file
@@ -0,0 +1,272 @@
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_atm_danube.c
|
||||
** PROJECT : UEIP
|
||||
** MODULES : ATM
|
||||
**
|
||||
** DATE : 7 Jul 2009
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : ATM driver common source file (core functions)
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 07 JUL 2009 Xu Liang Init Version
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Head File
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* Common Head File
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/version.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/ioctl.h>
|
||||
#include <asm/delay.h>
|
||||
|
||||
/*
|
||||
* Chip Specific Head File
|
||||
*/
|
||||
#include <asm/ifx/ifx_types.h>
|
||||
#include <asm/ifx/ifx_regs.h>
|
||||
#include <asm/ifx/common_routines.h>
|
||||
#include <asm/ifx/ifx_pmu.h>
|
||||
#include "ifxmips_atm_core.h"
|
||||
#include "ifxmips_atm_fw_danube.h"
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Definition
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* EMA Settings
|
||||
*/
|
||||
#define EMA_CMD_BUF_LEN 0x0040
|
||||
#define EMA_CMD_BASE_ADDR (0x00001580 << 2)
|
||||
#define EMA_DATA_BUF_LEN 0x0100
|
||||
#define EMA_DATA_BASE_ADDR (0x00001900 << 2)
|
||||
#define EMA_WRITE_BURST 0x2
|
||||
#define EMA_READ_BURST 0x2
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Declaration
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
/*
|
||||
* Hardware Init/Uninit Functions
|
||||
*/
|
||||
static inline void init_pmu(void);
|
||||
static inline void uninit_pmu(void);
|
||||
static inline void init_ema(void);
|
||||
static inline void init_mailbox(void);
|
||||
static inline void init_atm_tc(void);
|
||||
static inline void clear_share_buffer(void);
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Local Variable
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Local Function
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
static inline void init_pmu(void)
|
||||
{
|
||||
//*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
|
||||
PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
|
||||
}
|
||||
|
||||
static inline void uninit_pmu(void)
|
||||
{
|
||||
PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
|
||||
}
|
||||
|
||||
static inline void init_ema(void)
|
||||
{
|
||||
IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
|
||||
IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
|
||||
IFX_REG_W32(0x000000FF, EMA_IER);
|
||||
IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
|
||||
}
|
||||
|
||||
static inline void init_mailbox(void)
|
||||
{
|
||||
IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
|
||||
IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
|
||||
IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
|
||||
IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
|
||||
}
|
||||
|
||||
static inline void init_atm_tc(void)
|
||||
{
|
||||
// for ReTX expansion in future
|
||||
//*FFSM_CFG0 = SET_BITS(*FFSM_CFG0, 5, 0, 6); // pnum = 6
|
||||
//*FFSM_CFG1 = SET_BITS(*FFSM_CFG1, 5, 0, 6); // pnum = 6
|
||||
}
|
||||
|
||||
static inline void clear_share_buffer(void)
|
||||
{
|
||||
volatile u32 *p = SB_RAM0_ADDR(0);
|
||||
unsigned int i;
|
||||
|
||||
for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
|
||||
IFX_REG_W32(0, p++);
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Download PPE firmware binary code.
|
||||
* Input:
|
||||
* src --- u32 *, binary code buffer
|
||||
* dword_len --- unsigned int, binary code length in DWORD (32-bit)
|
||||
* Output:
|
||||
* int --- IFX_SUCCESS: Success
|
||||
* else: Error Code
|
||||
*/
|
||||
static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
|
||||
{
|
||||
volatile u32 *dest;
|
||||
|
||||
if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
|
||||
|| data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
|
||||
return IFX_ERROR;
|
||||
|
||||
if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
|
||||
IFX_REG_W32(0x00, CDM_CFG);
|
||||
else
|
||||
IFX_REG_W32(0x02, CDM_CFG);
|
||||
|
||||
/* copy code */
|
||||
dest = CDM_CODE_MEMORY(0, 0);
|
||||
while ( code_dword_len-- > 0 )
|
||||
IFX_REG_W32(*code_src++, dest++);
|
||||
|
||||
/* copy data */
|
||||
dest = CDM_DATA_MEMORY(0, 0);
|
||||
while ( data_dword_len-- > 0 )
|
||||
IFX_REG_W32(*data_src++, dest++);
|
||||
|
||||
return IFX_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ####################################
|
||||
* Global Function
|
||||
* ####################################
|
||||
*/
|
||||
|
||||
extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
|
||||
{
|
||||
ASSERT(major != NULL, "pointer is NULL");
|
||||
ASSERT(minor != NULL, "pointer is NULL");
|
||||
|
||||
*major = ATM_FW_VER_MAJOR;
|
||||
*minor = ATM_FW_VER_MINOR;
|
||||
}
|
||||
|
||||
void ifx_atm_init_chip(void)
|
||||
{
|
||||
init_pmu();
|
||||
|
||||
init_ema();
|
||||
|
||||
init_mailbox();
|
||||
|
||||
init_atm_tc();
|
||||
|
||||
clear_share_buffer();
|
||||
}
|
||||
|
||||
void ifx_atm_uninit_chip(void)
|
||||
{
|
||||
uninit_pmu();
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Initialize and start up PP32.
|
||||
* Input:
|
||||
* none
|
||||
* Output:
|
||||
* int --- IFX_SUCCESS: Success
|
||||
* else: Error Code
|
||||
*/
|
||||
int ifx_pp32_start(int pp32)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* download firmware */
|
||||
ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
|
||||
if ( ret != IFX_SUCCESS )
|
||||
return ret;
|
||||
|
||||
/* run PP32 */
|
||||
IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
|
||||
|
||||
/* idle for a while to let PP32 init itself */
|
||||
udelay(10);
|
||||
|
||||
return IFX_SUCCESS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
* Halt PP32.
|
||||
* Input:
|
||||
* none
|
||||
* Output:
|
||||
* none
|
||||
*/
|
||||
void ifx_pp32_stop(int pp32)
|
||||
{
|
||||
/* halt PP32 */
|
||||
IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
|
||||
}
|
||||
429
package/ifxmips-dsl-api/src/ifxmips_atm_fw_danube.h
Normal file
429
package/ifxmips-dsl-api/src/ifxmips_atm_fw_danube.h
Normal file
@@ -0,0 +1,429 @@
|
||||
#ifndef IFXMIPS_ATM_FW_DANUBE_H
|
||||
#define IFXMIPS_ATM_FW_DANUBE_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
**
|
||||
** FILE NAME : ifxmips_atm_fw_danube.h
|
||||
** PROJECT : Danube
|
||||
** MODULES : ATM (ADSL)
|
||||
**
|
||||
** DATE : 1 AUG 2005
|
||||
** AUTHOR : Xu Liang
|
||||
** DESCRIPTION : ATM Driver (PP32 Firmware)
|
||||
** COPYRIGHT : Copyright (c) 2006
|
||||
** Infineon Technologies AG
|
||||
** Am Campeon 1-12, 85579 Neubiberg, Germany
|
||||
**
|
||||
** This program is free software; you can redistribute it and/or modify
|
||||
** it under the terms of the GNU General Public License as published by
|
||||
** the Free Software Foundation; either version 2 of the License, or
|
||||
** (at your option) any later version.
|
||||
**
|
||||
** HISTORY
|
||||
** $Date $Author $Comment
|
||||
** 4 AUG 2005 Xu Liang Initiate Version
|
||||
** 23 OCT 2006 Xu Liang Add GPL header.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#define ATM_FW_VER_MAJOR 0
|
||||
#define ATM_FW_VER_MINOR 1
|
||||
|
||||
|
||||
static unsigned int firmware_binary_code[] = {
|
||||
0x800004A0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFC8, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xC1000002, 0xD90C0000, 0xC2000002, 0xDA080001, 0x80004710, 0xC2000000, 0xDA080001, 0x80003D98,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x80003D50, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x80004F18, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x80003C50, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xC0400000, 0xC0004840, 0xC8840000, 0x800043D0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xC0400002, 0xC0004840, 0xC8840000, 0x80004350, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xC3C00004, 0xDBC80001, 0xC10C0002, 0xD90C0000, 0x8000FEC8, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xC10E0002, 0xD90C0000, 0xC0004808, 0xC8400000, 0x80004380, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x900004D9, 0x00000000, 0x00000000, 0x00000000, 0x90CC0481,
|
||||
0x00000000, 0x00000000, 0x00000000, 0xC3C00000, 0xDBC80001, 0xC1400008, 0xC1900000, 0x71948000,
|
||||
0x15000100, 0xC140000A, 0xC1900002, 0x71948000, 0x15000100, 0xC140000C, 0xC1900004, 0x71948000,
|
||||
0x15000100, 0xC1400004, 0xC1900006, 0x71948000, 0x15000100, 0xC1400006, 0xC1900008, 0x71948000,
|
||||
0x15000100, 0xC140000E, 0xC190000A, 0x71948000, 0x15000100, 0xC1400000, 0xC190000C, 0x71948000,
|
||||
0x15000100, 0xC1400002, 0xC190000E, 0x71948000, 0x15000100, 0xC0400000, 0xC11C0000, 0xC000082C,
|
||||
0xCD040E08, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0400002, 0xC11C0000, 0xC000082C, 0xCD040E08,
|
||||
0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0000824, 0x00000000, 0xCBC00001, 0xCB800001, 0xCB400001,
|
||||
0xCB000000, 0xC0004878, 0x5BFC4000, 0xCFC00001, 0x5BB84000, 0xCF800001, 0x5B744000, 0xCF400001,
|
||||
0x5B304000, 0xCF000000, 0xC0000A10, 0x00000000, 0xCBC00001, 0xCB800000, 0xC0004874, 0x5BFC4000,
|
||||
0xCFC00001, 0x5BB84000, 0xCF800000, 0xC30001FE, 0xC000140A, 0xCF000000, 0xC3000000, 0x7F018000,
|
||||
0xC000042E, 0xCF000000, 0xC000040E, 0xCF000000, 0xC3C1FFFE, 0xC000490E, 0xCFC00080, 0xC000492C,
|
||||
0xCFC00080, 0xC0004924, 0xCFC00040, 0xC0004912, 0xCFC00040, 0xC0004966, 0xCFC00040, 0xC0004968,
|
||||
0xCFC00080, 0xC000496A, 0xCFC00080, 0xC3C00000, 0xC2800020, 0xC3000000, 0x7F018000, 0x6FF88000,
|
||||
0x6FD44000, 0x4395C000, 0x5BB84A00, 0x5838000A, 0xCF000000, 0x5BFC0002, 0xB7E8FFA8, 0x00000000,
|
||||
0xC3C00000, 0xC2800010, 0x6FF86000, 0x47F9C000, 0x5BB84C80, 0xC3400000, 0x58380004, 0xCB420080,
|
||||
0x00000000, 0x58380008, 0xCF400080, 0x5BFC0002, 0xB7E8FF90, 0x00000000, 0xC3C00000, 0xC2800020,
|
||||
0xC348001E, 0xC3000000, 0x7F018000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20,
|
||||
0x58380008, 0xCF400420, 0x5838000A, 0xCF000000, 0x5BFC0002, 0xB7E8FF90, 0x00000000, 0x00000000,
|
||||
0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x80000518, 0x00000000, 0x80002118, 0x00000000,
|
||||
0x8000FFC8, 0xC0004958, 0xC8400000, 0x00000000, 0xC3C00002, 0x7BC42000, 0xCC400000, 0xC0004848,
|
||||
0xCB840000, 0xC000495C, 0xCAC40000, 0xC0004844, 0xC8840000, 0x46F90000, 0x8400FF6A, 0xC000487C,
|
||||
0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC0001624, 0xCB040000, 0xA63C005A,
|
||||
0x00000000, 0x00000000, 0xA71EFF02, 0x00000000, 0xC0000824, 0xCA840000, 0x6CA08000, 0x6CA42000,
|
||||
0x46610000, 0x42290000, 0xC35E0002, 0xC6340068, 0xC0001624, 0xCF440080, 0xC2000000, 0xC161FFFE,
|
||||
0x5955FFFE, 0x15400000, 0x00000000, 0xC0004844, 0xC8840000, 0xC000082C, 0xCA040040, 0x00000000,
|
||||
0x00000000, 0x58880002, 0xB608FFF8, 0x00000000, 0xC0800000, 0xC0004844, 0xCC840040, 0x5AEC0002,
|
||||
0xC000495C, 0xCEC40000, 0x5E6C0006, 0x84000048, 0xC0004848, 0xCB840000, 0xC0000838, 0xC2500002,
|
||||
0xCE440808, 0x5FB80002, 0xC0004848, 0xCF840000, 0x5EEC0002, 0xC000495C, 0xCEC40000, 0x00000000,
|
||||
0xC121FFFE, 0x5911FE14, 0x15000000, 0x8000FD80, 0xC000495A, 0xC8400000, 0x00000000, 0xC3C00002,
|
||||
0x7BC42000, 0xCC400000, 0xC0004960, 0xCAC40000, 0x00000000, 0x00000000, 0x5EEC0000, 0x840000F2,
|
||||
0x00000000, 0xB6FC0030, 0xC0001600, 0xCA040000, 0x00000000, 0x00000000, 0xA61E00B2, 0x6FE90000,
|
||||
0xC0000A28, 0xCE840808, 0xC2C00000, 0xC2800004, 0xB6E80080, 0xC0001604, 0xCA840000, 0xC0004960,
|
||||
0xCEC40000, 0xA69EFCA2, 0x00000000, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00002, 0xC0001600,
|
||||
0xCA040000, 0x00000000, 0x00000000, 0xA61E000A, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00000,
|
||||
0xC0001604, 0xCA840000, 0xC0004960, 0xCEC40000, 0xA69EFC0A, 0xC2400000, 0xC0000A14, 0xCA440030,
|
||||
0x00000000, 0x00000000, 0x46E52000, 0xA4400000, 0xC2800000, 0xDFEB0031, 0x8000FFF8, 0xDFEA0031,
|
||||
0xB668FB82, 0x00000000, 0xC00048A0, 0xCB040000, 0xC0000A10, 0xCA840000, 0x6F208000, 0x6F242000,
|
||||
0x46610000, 0x42A10000, 0xC2400000, 0xC0000A14, 0xCA440030, 0xC35E0002, 0xC6340068, 0xC0001604,
|
||||
0xCF440080, 0x5B300002, 0xB670FFF8, 0x5AEC0002, 0xC3000000, 0xC00048A0, 0xCF040000, 0xC0004960,
|
||||
0xCEC40000, 0x8000FAC0, 0xC0004918, 0xD2800000, 0xC2000000, 0xDF600040, 0x5E600080, 0x8400025A,
|
||||
0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000480A, 0xCA000000, 0xC0004912,
|
||||
0xCA400000, 0xC0004924, 0xCA800000, 0xC0004966, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
|
||||
0x15000000, 0x76610000, 0x76A10000, 0x76E10000, 0x840001B2, 0xC0004918, 0xCA400000, 0xC28001FE,
|
||||
0x76A10000, 0x5A640002, 0x6A254010, 0x5EE80000, 0x84000002, 0x6AA54000, 0x8000FFF8, 0xC6280000,
|
||||
0x62818008, 0xC0004918, 0xCF000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004966,
|
||||
0xCA400000, 0xC2000002, 0x6A310000, 0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE,
|
||||
0x5911FE14, 0x15000000, 0x6F346000, 0x4735A000, 0x5B744C80, 0xC2800000, 0x58340006, 0xCA800080,
|
||||
0xC2C00000, 0x58340000, 0xCAC000E0, 0xC2400000, 0x5834000A, 0xCA420080, 0x6EA82000, 0x42E9E000,
|
||||
0x6F2CA000, 0x42E56000, 0x5AEC1400, 0xC3990040, 0xC7381C20, 0xC6F80068, 0x99005930, 0xDB980000,
|
||||
0xDBD80001, 0x00000000, 0xDEA00000, 0x47210000, 0x8400FD68, 0xC0004958, 0xC8400000, 0x00000000,
|
||||
0xC3C00002, 0x7BC42000, 0xCC400000, 0xC0004848, 0xCB840000, 0xC0004844, 0xC8840000, 0x5FB80000,
|
||||
0x8400F7DA, 0xC0001A1C, 0xCA000000, 0xC2400002, 0x6A452000, 0x76610000, 0x8400F7AA, 0xC000487C,
|
||||
0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC4240000, 0x00000000, 0xA63C17BA,
|
||||
0x00000000, 0xC0004878, 0xC8040000, 0x6C908000, 0x44908000, 0x44908000, 0x40100000, 0xCA000000,
|
||||
0xC4240000, 0x00000000, 0xC0004934, 0xCE000000, 0xC2800002, 0xC4681C10, 0xC62821D8, 0xC2600010,
|
||||
0x5A650040, 0xC0004800, 0xCB400000, 0xC2200400, 0x5A200000, 0xC7601048, 0xC0001220, 0xCE800000,
|
||||
0xC0001200, 0xCE400000, 0xC0001202, 0xCE000000, 0xC0001240, 0xCB400000, 0x00000000, 0x00000000,
|
||||
0xA754FFC0, 0xC2000000, 0xC7600048, 0xA7520022, 0x00000000, 0x00000000, 0x990060A8, 0xC0004822,
|
||||
0xC9400000, 0xC1800002, 0x80001668, 0x58204080, 0xC2000000, 0xCA000020, 0xC2400000, 0xCA414008,
|
||||
0xC2800000, 0xCA812008, 0xC2C00000, 0xCAC20020, 0xC0004938, 0xCE000000, 0xC0004920, 0xCE400000,
|
||||
0xC0004916, 0xCE800000, 0xC0004922, 0xCEC00000, 0xA6400520, 0x00000000, 0xC0004938, 0xCBC00000,
|
||||
0x00000000, 0xC3800000, 0x6FF48000, 0x6FD44000, 0x4355A000, 0x5B744A00, 0x58340000, 0xCB802018,
|
||||
0x00000000, 0xC2000000, 0x6FB46000, 0x47B5A000, 0x5B744C80, 0x5834000C, 0xCA000028, 0xC000491A,
|
||||
0xCF800000, 0x5E200000, 0x84000452, 0xC2000000, 0xDF610050, 0x5E6001E8, 0x8800FFD0, 0xC2000002,
|
||||
0xC2400466, 0xC2A00000, 0x5AA80000, 0xC0001006, 0xCE000000, 0xC0001008, 0xCE400000, 0xC000100A,
|
||||
0xCE800000, 0x99005370, 0xC1A0FFFE, 0xC0000824, 0xC9840068, 0xC0004934, 0xCA400000, 0xC2000000,
|
||||
0xC2800002, 0x990053B0, 0xDA980000, 0xC6140000, 0xC6580000, 0xC161FFFE, 0x5955FFFE, 0x15400000,
|
||||
0x00000000, 0x99005498, 0xC000491A, 0xC9400000, 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE14,
|
||||
0x15000000, 0xC0004922, 0xCA001120, 0xC3C00000, 0xC3800000, 0xC0004930, 0xCE001120, 0xC0004932,
|
||||
0xCBC000E0, 0xC2800000, 0xC000491E, 0xCFC00000, 0xC0004862, 0xCA800068, 0xC3A0001A, 0x5BB94000,
|
||||
0xC6B80068, 0xC000491C, 0xCF800000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0x00000000,
|
||||
0x00000000, 0x00000000, 0xA8E2FFC8, 0xC2000000, 0xC1220002, 0xD90C0000, 0xDF600040, 0x5E600080,
|
||||
0x8400FFDA, 0xC000491C, 0xCA000000, 0xC000491E, 0xCA400000, 0x00000000, 0x00000000, 0x99005930,
|
||||
0xDA180000, 0xDA580001, 0x00000000, 0xC2000000, 0xDF610050, 0x5E6001FE, 0x8800FFD0, 0xC0004916,
|
||||
0xCA800000, 0xC2C00000, 0xDFEC0050, 0xC2400000, 0x46E52000, 0x84000032, 0x5EA80000, 0x84000022,
|
||||
0xC2600002, 0x990060A8, 0xC000482E, 0xC9400000, 0xC1800002, 0x80000018, 0xC2600000, 0x990060A8,
|
||||
0xC000482C, 0xC9400000, 0xC1800002, 0xC2000068, 0xC6240080, 0xC0004930, 0xCE400088, 0xC000491A,
|
||||
0xC9800000, 0xC0004862, 0xC9400000, 0x6D9C6000, 0x459CE000, 0x59DC4C80, 0x99005790, 0xD9580000,
|
||||
0xD9980001, 0xD9D40000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC2000000, 0xDF600040,
|
||||
0x5E600080, 0x8400FFD2, 0x00000000, 0xC000491C, 0xCA000000, 0xC000491E, 0xCA400000, 0x00000000,
|
||||
0x00000000, 0x99005930, 0xDA180000, 0xDA580001, 0x00000000, 0x800010D0, 0x00000000, 0x990060A8,
|
||||
0xC000482A, 0xC9400000, 0xC1800002, 0x800010A0, 0xC0004938, 0xCBC00000, 0x00000000, 0x00000000,
|
||||
0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0x58380008, 0xCA000000, 0x00000000, 0x00000000,
|
||||
0xA6000362, 0x00000000, 0xC0004938, 0xCBC00000, 0xC3000000, 0x00000000, 0x6FF88000, 0x6FD44000,
|
||||
0x4395C000, 0x5BB84A00, 0x58380000, 0xCB002018, 0xC2000000, 0x58380008, 0xCA020080, 0x5838000C,
|
||||
0xCAC00000, 0x5838000E, 0xCA400000, 0xC000491A, 0xCF000000, 0xC0004930, 0xCEC00000, 0xC000493C,
|
||||
0xCE000000, 0xC0004932, 0xCE400000, 0x5E200000, 0x84000108, 0xC2800000, 0xA6FE009A, 0x6F206000,
|
||||
0x47210000, 0x5A204C80, 0x5820000C, 0xCA800028, 0x00000000, 0x00000000, 0x5EA80000, 0x840001DA,
|
||||
0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0x99005498, 0xC000491A, 0xC9400000,
|
||||
0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0xC0004930, 0xCAC00000, 0xC0004932,
|
||||
0xCA400000, 0xC7EC1120, 0xC0004930, 0xCEC00000, 0x5838000C, 0xCEC00000, 0x58000002, 0xCE400000,
|
||||
0xC0004934, 0xCA000000, 0xC2400002, 0x6E642000, 0x6E642000, 0x76252000, 0x84000012, 0xC2400002,
|
||||
0x6E684000, 0x58380008, 0xCE800208, 0xA6000000, 0x6E682000, 0x58380008, 0xCE800108, 0xC2400002,
|
||||
0x6E642000, 0x76252000, 0x840000D2, 0x58380008, 0xCA000000, 0xC2800000, 0xC2400000, 0xA60200A0,
|
||||
0xDBA80000, 0x6F386000, 0x4739C000, 0x5BB84C80, 0x58380004, 0xCA400080, 0x58380002, 0xCA800080,
|
||||
0x00000000, 0xDEB80000, 0x46694000, 0x88000048, 0x00000000, 0xC0004824, 0xCA000000, 0xC2400002,
|
||||
0x6E640000, 0x5A200002, 0xCE000000, 0x58380008, 0xCE400008, 0x80000000, 0x00000000, 0x80000030,
|
||||
0xC0004934, 0xCA000000, 0x00000000, 0x00000000, 0xA6020C4A, 0x00000000, 0x00000000, 0x80000C80,
|
||||
0xC2800000, 0xC2000200, 0xC240001A, 0xDF690050, 0x46A14000, 0x46694000, 0x8800FFBA, 0xC2000006,
|
||||
0xC2600982, 0x5A643B6E, 0x5838000A, 0xCA800000, 0xC0001006, 0xCE000000, 0xC0001008, 0xCE400000,
|
||||
0xC000100A, 0xCE800000, 0x99005370, 0xC1A0FFFE, 0xC0000824, 0xC9840068, 0xC2000000, 0xC0004930,
|
||||
0xCA02E010, 0x58380026, 0xCA400000, 0x00000000, 0xC2800000, 0x990053B0, 0xDA980000, 0xC6140000,
|
||||
0xC6580000, 0xC0004934, 0xCA000000, 0x00000000, 0x00000000, 0xA6020002, 0x00000000, 0x00000000,
|
||||
0x80000300, 0xC0004938, 0xCBC00000, 0xC0004878, 0xC8040000, 0x6C908000, 0x44908000, 0x44908000,
|
||||
0x40100000, 0xCA000000, 0xC4240000, 0x00000000, 0x58240018, 0xCA000000, 0x6FF88000, 0x6FD44000,
|
||||
0x4395C000, 0x5BB84A00, 0xC3000000, 0xC3400002, 0xC2C00000, 0xC62C0080, 0xC6270040, 0xC0004940,
|
||||
0xCE400040, 0xC6260040, 0xC0004942, 0xCE400040, 0xC000493C, 0xCA000000, 0x5EEC0000, 0x84000172,
|
||||
0x5A6C0010, 0x46614000, 0x88000178, 0x5A600052, 0x466D4000, 0x88000160, 0x58380006, 0xCA800000,
|
||||
0xC0004940, 0xCA000000, 0xC2400000, 0xC6A70040, 0x7E412000, 0x76252000, 0xC2000000, 0xC6A10040,
|
||||
0x46610000, 0x84000120, 0xC0004942, 0xCA000000, 0xC2400000, 0xC6A60040, 0x7E412000, 0x76252000,
|
||||
0xC2000000, 0xC6A00040, 0x58380002, 0xCA800000, 0x46610000, 0x840000D0, 0xC2400000, 0xC6A60080,
|
||||
0x46E50000, 0x880000C2, 0xC2400000, 0xC6A40080, 0x58380008, 0xCA800000, 0x466D0000, 0x880000A2,
|
||||
0x00000000, 0xA682FFF8, 0x00000000, 0xC7700B08, 0xA6840078, 0x00000000, 0xC7700A08, 0x80000068,
|
||||
0xC7700208, 0xC000493C, 0xCAC00000, 0x80000048, 0xC7700308, 0xC000493C, 0xCAC00000, 0x80000028,
|
||||
0xC7700908, 0x80000018, 0xC7700808, 0x80000008, 0xC7700708, 0x8000FFF8, 0xC7700508, 0xC0004944,
|
||||
0xCF000000, 0xC000493E, 0xCEC00000, 0xC0004938, 0xCA400000, 0xC000493C, 0xCB800000, 0xC000493E,
|
||||
0xCB400000, 0xC3000000, 0x6E608000, 0x6E544000, 0x42150000, 0x5A204A00, 0x5AA00008, 0x58200004,
|
||||
0xCB000080, 0xC0004934, 0xCA000000, 0xC2400000, 0xC0004930, 0xCA42E010, 0xC3C00018, 0xA6020078,
|
||||
0x00000000, 0x43656000, 0x46F90000, 0x88000038, 0x47AD6000, 0x6EE04010, 0x5BE00004, 0xC2000000,
|
||||
0xC6E00010, 0x5E200000, 0x8400002A, 0x5BFC0002, 0x80000018, 0xC3C00004, 0x5A2C0008, 0x46390000,
|
||||
0x8800FFFA, 0x5FB80008, 0x6FE04000, 0x42390000, 0x46312000, 0x88000050, 0xC2400000, 0xC0004930,
|
||||
0xCA42E010, 0xC2060002, 0xC6800000, 0xCE000308, 0x6FE04000, 0x4631C000, 0x5F700010, 0x4675A000,
|
||||
0xC2000000, 0xC6340010, 0xC25A000A, 0xC000491A, 0xCA401C20, 0xC2800000, 0xC0004932, 0xCA8000E0,
|
||||
0xC0004862, 0xCA400068, 0x6FA04010, 0x42290000, 0xC000491E, 0xCE000000, 0xC7E41050, 0xC000491C,
|
||||
0xCE400000, 0x6FE04000, 0x43A1C000, 0xC000493C, 0xCF800000, 0xC000493E, 0xCF400000, 0xC000493A,
|
||||
0xCFC00000, 0x8000FFF0, 0x00000000, 0x00000000, 0x00000000, 0xC2000000, 0xDCE00000, 0xA622FFB8,
|
||||
0xC1220002, 0xD90C0000, 0xC0004938, 0xCBC00000, 0xC0004944, 0xCB400000, 0xC0004862, 0xCB000000,
|
||||
0xC0004934, 0xCA000000, 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0xA6020248, 0xC2400000,
|
||||
0x58380008, 0xCA406008, 0xDFE80000, 0xC2218E08, 0x5A21BAF6, 0x46294000, 0x8400000A, 0xC2080002,
|
||||
0x7235A000, 0x80000040, 0x5E640000, 0x8400000A, 0xC20C0002, 0x7235A000, 0x80000018, 0xC2000000,
|
||||
0xC760E718, 0xC7604220, 0x5E200000, 0x8400025A, 0xC2200002, 0xC0004930, 0xCE001008, 0x990060A8,
|
||||
0xC0004828, 0xC9400000, 0xC1800002, 0x58380000, 0xCA000000, 0x00000000, 0x00000000, 0xA6000112,
|
||||
0xC0004940, 0xCA800000, 0xC0004942, 0xCA400000, 0xC7600080, 0xC6A01840, 0xC6601040, 0xC000493A,
|
||||
0xCA400000, 0xC0004934, 0xCA800000, 0xC0007200, 0x40300000, 0x40240000, 0x5C000004, 0x5EC07400,
|
||||
0x8800FFFA, 0x5C000200, 0xCE000000, 0x58000002, 0x5EC07400, 0x8800FFFA, 0x5C000200, 0xCE800000,
|
||||
0xC000493E, 0xCA000000, 0xC2400000, 0x5838000C, 0xCE400000, 0x990060A8, 0xC0004830, 0xC9400000,
|
||||
0xC6180000, 0xC0004930, 0xC6100080, 0xCD000080, 0x80000090, 0xC2400002, 0x58380008, 0xCE400008,
|
||||
0xC0004944, 0xCF400000, 0x80000260, 0xC000493C, 0xCA400000, 0xDFE80000, 0x5A300018, 0xC0007200,
|
||||
0x40200000, 0xCA000000, 0x58380008, 0xC6501080, 0xCD001080, 0x5838000A, 0xCE800000, 0x58380026,
|
||||
0xCE000000, 0xC0004944, 0xCF400000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0x80000020,
|
||||
0x00000000, 0x990060A8, 0xC0004826, 0xC9400000, 0xC1800002, 0x8000FDC0, 0xC2000000, 0xC2400200,
|
||||
0xDF600040, 0xB624FFCA, 0xC000491C, 0xCA400000, 0xC000491E, 0xCA800000, 0x99005930, 0xDA580000,
|
||||
0xDA980001, 0x00000000, 0xC0004934, 0xCA000000, 0x00000000, 0xC2800000, 0xA6020140, 0xC2400004,
|
||||
0xC2000200, 0xDF690050, 0x46A14000, 0x46694000, 0x8800FFC2, 0x00000000, 0xC000491A, 0xC9800000,
|
||||
0xC0004862, 0xC9400000, 0x6D9C6000, 0x459CE000, 0x59DC4C80, 0x99005790, 0xD9580000, 0xD9980001,
|
||||
0xD9D40000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC2000000, 0xC2400200, 0xDF600040,
|
||||
0xB624FFCA, 0xC000491C, 0xCA400000, 0xC000491E, 0xCA800000, 0x99005930, 0xDA580000, 0xDA980001,
|
||||
0x00000000, 0x58380008, 0xCA400000, 0xC2000000, 0xCE000020, 0xC2A1FFFE, 0x5AA9FFFE, 0xCE001080,
|
||||
0x5838000A, 0xCE800000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0000838, 0xC2500002,
|
||||
0xCE440808, 0xC0004848, 0xCB840000, 0xC2000000, 0xC000082C, 0xCA040030, 0x5FB80002, 0xC0004848,
|
||||
0xCF840000, 0x58880002, 0xB608FFF8, 0x00000000, 0xC0800000, 0xC0004844, 0xCC840000, 0x00000000,
|
||||
0xC121FFFE, 0x5911FE14, 0x15000000, 0x8000DEC0, 0xC2000000, 0xDF600040, 0x5E200080, 0x84000252,
|
||||
0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000480C, 0xCA000000, 0xC0004910,
|
||||
0xCA400000, 0xC000492C, 0xCA800000, 0xC0004968, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
|
||||
0x15000000, 0x76610000, 0x76A10000, 0x762D6000, 0x840001AA, 0xC0004926, 0xCA400000, 0xC201FFFE,
|
||||
0x762D6000, 0x5A640002, 0x6AE50010, 0x5F200000, 0x84000002, 0x6A250000, 0x8000FFF8, 0xC6E00000,
|
||||
0x62014008, 0xC0004926, 0xCE800000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004968,
|
||||
0xCA400000, 0xC2000002, 0x6A290000, 0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE,
|
||||
0x5911FE14, 0x15000000, 0x6EB4A000, 0x6E944000, 0x4575A000, 0x46B5A000, 0x5B744E20, 0x58340002,
|
||||
0xC2000000, 0xCA0000E0, 0x5834002E, 0xC2400000, 0xCA400080, 0x6EB0A000, 0x6EBC4000, 0x47F18000,
|
||||
0x46B18000, 0x5B300E4E, 0x5B300004, 0x6E642000, 0x4225E000, 0xC39A8024, 0xC7380068, 0xC6B81C20,
|
||||
0x99005930, 0xDB980000, 0xDBD80001, 0x00000000, 0xC2000000, 0xDF600040, 0x5E200080, 0x8400028A,
|
||||
0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA000000, 0xC000492A,
|
||||
0xCA400000, 0xC000496A, 0xCB000000, 0xC0004956, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14,
|
||||
0x15000000, 0x76318000, 0x76718000, 0x840001EA, 0xC201FFFE, 0x76318000, 0x5AEC0002, 0x6B2D0010,
|
||||
0x5EA00000, 0x84000002, 0x6A2D0000, 0x8000FFF8, 0xC7200000, 0x62016008, 0xC0004956, 0xCEC00000,
|
||||
0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000496A, 0xCA400000, 0xC2000002, 0x6A2D0000,
|
||||
0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x6EF4A000,
|
||||
0x6ED44000, 0x4575A000, 0x46F5A000, 0x5B744E20, 0x5834000E, 0xC2000000, 0xCA0000E0, 0x58340008,
|
||||
0xC2400000, 0xCA420080, 0x5834000C, 0xC2800000, 0xCA832018, 0x6E644010, 0x42250000, 0x4229E000,
|
||||
0xC39A8008, 0x58340008, 0xCB809020, 0x58340008, 0xC2800000, 0xCA810018, 0x6EE0A000, 0x6EE44000,
|
||||
0x46610000, 0x46E10000, 0x5A200008, 0x5A200E28, 0x42290000, 0xC6380068, 0xC6F81C20, 0x99005930,
|
||||
0xDB980000, 0xDBD80001, 0x00000000, 0xC000495A, 0xC8400000, 0x00000000, 0xC3C00002, 0x7BC42000,
|
||||
0xCC400000, 0xC0001A1C, 0xCA000000, 0xC2400008, 0x6A452000, 0x76610000, 0x8400D91A, 0xC0000A28,
|
||||
0xC3800000, 0xCB840030, 0xC0000A14, 0xC3400000, 0xCB440030, 0xC0004880, 0xCB040000, 0xB7B4D8CA,
|
||||
0x58041802, 0xCAC00000, 0xA7000018, 0x00000000, 0x00000000, 0xA6C8D898, 0xC2800000, 0xC6E80020,
|
||||
0x80000030, 0xC2800000, 0xC7282020, 0xC000490E, 0xCA400000, 0x6BE9E000, 0x00000000, 0x77E52000,
|
||||
0x8400D848, 0x6EA0A000, 0x6E944000, 0x45610000, 0x46A10000, 0x5A204E20, 0x5820000C, 0xCA000000,
|
||||
0xC0004946, 0xCE800000, 0xA6220348, 0x00000000, 0xC2200060, 0xC0004948, 0xCE000010, 0xCE001040,
|
||||
0xC240000A, 0xC000494A, 0xCE400000, 0xC2B60002, 0xC0004964, 0xCE801B08, 0x99005C00, 0xC00048A0,
|
||||
0xC8840000, 0x00000000, 0xC0004946, 0xCBC00000, 0x00000000, 0x00000000, 0x6FF8A000, 0x6FD44000,
|
||||
0x4579C000, 0x47F9C000, 0x5BB84E20, 0x990059C0, 0xDBD80000, 0xDB980001, 0x00000000, 0x99005708,
|
||||
0xC000491C, 0xC1400000, 0xC9420050, 0xC000491C, 0x99005BB8, 0xC9400001, 0xC9800000, 0x00000000,
|
||||
0x99005930, 0xD9580000, 0xD9980001, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000,
|
||||
0x990055F8, 0xDBD80000, 0xDB980001, 0xC7D80000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
|
||||
0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x58380010, 0xCA000000, 0xC0004874,
|
||||
0xC8040000, 0x6C908000, 0x44908000, 0x44908000, 0x40100000, 0xCA400000, 0xC4340000, 0x00000000,
|
||||
0xC7400000, 0xCE000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000,
|
||||
0xC2800002, 0x6ABD4000, 0x72A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
|
||||
0x990060A8, 0xC0004836, 0xC9400000, 0xC1800002, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFC8,
|
||||
0x00000000, 0xC1220002, 0xD90C0000, 0xC2000000, 0xC0000A14, 0xCA040030, 0xC0000A28, 0xC2500002,
|
||||
0xCE440808, 0x58880002, 0xB608FFF8, 0xC00048A0, 0xC0800000, 0xCC840000, 0x8000D498, 0xC0004946,
|
||||
0xCBC00000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000, 0xC2800002,
|
||||
0x6ABD4000, 0x72A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x6FF8A000,
|
||||
0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x58380008, 0xCA000000, 0x5838000C, 0xCA400000,
|
||||
0xC3400000, 0xC6340008, 0xC000494E, 0xCF400000, 0xC2800000, 0xC62A0080, 0xC3000000, 0xC6308020,
|
||||
0x6F304000, 0x43298000, 0xC000493C, 0xCF000000, 0xC2C00000, 0xC66C0080, 0xC0004950, 0xCEC00000,
|
||||
0xC2800000, 0xC66AE028, 0xC0004954, 0xCE800000, 0x5F740000, 0x84000188, 0x5E300028, 0x462D2000,
|
||||
0x84000152, 0x462D2000, 0x8800011A, 0x5E300018, 0x462D2000, 0x88000012, 0x462D2000, 0x8400002A,
|
||||
0x00000000, 0x800000A8, 0x00000000, 0x99005D40, 0xDBD80000, 0xDB980001, 0xC7800000, 0xC3400002,
|
||||
0xC000494E, 0xCF400000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000,
|
||||
0xC2800002, 0x6ABD4000, 0x7E814000, 0x76A52000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14,
|
||||
0x15000000, 0xC2200060, 0xC0004948, 0xCE001040, 0xC2000000, 0xC000494C, 0xCE000000, 0x80000068,
|
||||
0x00000000, 0x99005D40, 0xDBD80000, 0xDB980001, 0xC7800000, 0x99005F40, 0xDBD80000, 0xDB980001,
|
||||
0xC7800000, 0xC2200058, 0xC0004948, 0xCE001040, 0xC2000002, 0xC000494C, 0xCE000000, 0xC2000006,
|
||||
0xC0001006, 0xCE000000, 0x5838000A, 0xCA400000, 0xC2200982, 0x5A203B6E, 0xC0001008, 0xCE000000,
|
||||
0xC000100A, 0xCE400000, 0xC0004954, 0xCA800000, 0xC200000C, 0xC000494A, 0xCE000000, 0xC0004948,
|
||||
0xCE800010, 0xC2B60000, 0xC0004964, 0xCE800000, 0x99005C00, 0xC00048A0, 0xC8840000, 0x00000000,
|
||||
0xC0004946, 0xCBC00000, 0xC000494C, 0xCA000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000,
|
||||
0x5BB84E20, 0x5E200000, 0x840000E2, 0x00000000, 0x990059C0, 0xDBD80000, 0xDB980001, 0x00000000,
|
||||
0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC000491C, 0x99005BB8, 0xC9400001, 0xC9800000,
|
||||
0x00000000, 0x99005930, 0xD9580000, 0xD9980001, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000,
|
||||
0x00000000, 0x990055F8, 0xDBD80000, 0xDB980001, 0xC7D80000, 0x00000000, 0xC121FFFE, 0x5911FE14,
|
||||
0x15000000, 0xC000493C, 0xCA800000, 0xC000494E, 0xCAC00000, 0xC3000018, 0xC3400006, 0x5E200000,
|
||||
0x84000012, 0xC2800000, 0xC2C00000, 0xC300001E, 0xC3400000, 0xC6AC1080, 0xC72C0420, 0xC76C0818,
|
||||
0x58380010, 0xCA800000, 0x58380008, 0xCEC00000, 0xC6280108, 0xC0004874, 0xC8040000, 0x6C908000,
|
||||
0x44908000, 0x44908000, 0x40100000, 0xCB000000, 0xC4340000, 0x00000000, 0xC7400000, 0xCE800000,
|
||||
0xC0004952, 0xCE800000, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFC8, 0x00000000, 0xC000494C,
|
||||
0xCA000000, 0xC0004950, 0xCAC00000, 0x5E200000, 0x84000052, 0xDFE80000, 0x7E814000, 0x5834001A,
|
||||
0xCE800000, 0x990060A8, 0xC0004834, 0xC9400000, 0xC1800002, 0x990060A8, 0xC0004838, 0xC9400000,
|
||||
0xC6D80000, 0xC1220002, 0xD90C0000, 0x5E200000, 0x84000028, 0x5838002C, 0xCB000000, 0xDFE80000,
|
||||
0x00000000, 0x58380014, 0xCF000000, 0x80000000, 0xC2A1FFFE, 0x5AA9FFFE, 0x5838000A, 0xCE800000,
|
||||
0xC3000000, 0xC0000A14, 0xCB040030, 0xC2D00002, 0xC0000A28, 0xCEC40808, 0xC000494E, 0xCA800000,
|
||||
0x58880002, 0xB4B0FFF8, 0xC00048A0, 0xC0800000, 0xCC840000, 0x5EA80000, 0x8400013A, 0x5E200000,
|
||||
0x84000128, 0xC000493C, 0xCA800000, 0x00000000, 0x00000000, 0x5AA80060, 0xCE800000, 0x99005D40,
|
||||
0xDBD80000, 0xDB980001, 0xC7800000, 0x99005F40, 0xDBD80000, 0xDB980001, 0xC7800000, 0xC0004952,
|
||||
0xCAC00000, 0x58380000, 0xCA800000, 0xC30C0002, 0xC7F00020, 0xA6800078, 0x00000000, 0x00000000,
|
||||
0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0001800, 0xCA000000, 0x00000000, 0x00000000,
|
||||
0xA60CFFCA, 0xC6F00508, 0xC6B0C408, 0xCF000000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,
|
||||
0x8000CB48, 0xDCBC0001, 0x5FFC0000, 0x8400003A, 0xC3800002, 0xDB880001, 0x5FFC0004, 0x8400C4B2,
|
||||
0xC3800000, 0xDB880001, 0xC3CE0002, 0xC0000800, 0xCFC00708, 0xC3E1FFFE, 0x597DFFFE, 0x593DFE14,
|
||||
0x94000001, 0x00000000, 0x00000000, 0x00000000, 0xC000487C, 0xC8040000, 0x00000000, 0x00000000,
|
||||
0x40080000, 0xCBC00000, 0xC4380000, 0x00000000, 0xC000480E, 0xCA000000, 0xC0004858, 0xCB440000,
|
||||
0x00000000, 0x00000000, 0x46350000, 0x88000098, 0x00000000, 0xA7C00028, 0xC0004854, 0xC1000002,
|
||||
0xCD040000, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x800000C0, 0x00000000, 0xA7D20118, 0x00000000,
|
||||
0xC7E14048, 0xC2400000, 0xC6246030, 0xC200006A, 0x46610000, 0xC6240038, 0xC0000810, 0xCE440038,
|
||||
0x8000FF58, 0xC2000000, 0xC0000808, 0xCA040018, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x5A200002,
|
||||
0x5E600010, 0x8400FFF8, 0xC2000000, 0xC0000808, 0xCE040018, 0xC3400000, 0x80000010, 0xC1200002,
|
||||
0xC0000818, 0xCD041008, 0x5B740002, 0xC0004858, 0xCF440000, 0x99005348, 0xC0004848, 0xC9440000,
|
||||
0xC1800000, 0xC11C0002, 0xC000082C, 0xCD040E08, 0x800005C8, 0x5B740002, 0xC0004858, 0xCF440000,
|
||||
0xC7800000, 0xC13C0002, 0xCD001E08, 0xC0004848, 0xC9440000, 0xC1800000, 0xC000082C, 0xC9840030,
|
||||
0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB4980540, 0x00000000, 0xC0800000, 0x80000530,
|
||||
0xC000487C, 0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCBC00000, 0xC4280000, 0x00000000,
|
||||
0xA7C00110, 0xC000484C, 0xCA040000, 0xC2400000, 0xC0001AEC, 0xCA440020, 0x5A200002, 0xC000484C,
|
||||
0xCE040000, 0xB624006A, 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC0004848, 0xC9440000, 0xC1800000,
|
||||
0xC000082C, 0xC9840030, 0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB4980430, 0x00000000,
|
||||
0xC0800000, 0x80000420, 0xC0004854, 0xC1000004, 0xCD040000, 0xC0000820, 0xC2000002, 0xCE040000,
|
||||
0xC2000000, 0xC000484C, 0xCE040000, 0xC0004858, 0xCE040000, 0x8000FF10, 0xC0004854, 0xC1000000,
|
||||
0xCD040000, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x99005348, 0xC0004848, 0xC9440000, 0xC1800000,
|
||||
0xC1200000, 0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC2000000, 0xC000484C,
|
||||
0xCE040000, 0x80000320, 0xC0001AC0, 0xCB840000, 0xC000487C, 0xC8040000, 0x00000000, 0x00000000,
|
||||
0x40080000, 0xCBC00000, 0xC4280000, 0x00000000, 0xA780022A, 0x00000000, 0x00000000, 0xA7C001EA,
|
||||
0x00000000, 0xC0001B00, 0xC2060006, 0xCE040310, 0xA7E801A2, 0x00000000, 0xC0004850, 0xCA040000,
|
||||
0xC2400000, 0xC0001AEC, 0xCA448020, 0x5A200002, 0xC0004850, 0xCE040000, 0xB624008A, 0x00000000,
|
||||
0xC6800000, 0xC13C0002, 0xCD001E08, 0xC0001ACC, 0xC2000002, 0xCE040008, 0xC0004848, 0xC9440000,
|
||||
0xC1800000, 0xC000082C, 0xC9840030, 0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB49801A8,
|
||||
0x00000000, 0xC0800000, 0x80000198, 0xC0004854, 0xC1000000, 0xCD040000, 0xC11C0000, 0xC000082C,
|
||||
0xCD040E08, 0x99005348, 0xC0004848, 0xC9440000, 0xC1800000, 0xC2000000, 0xC0000820, 0xCE040000,
|
||||
0xC1200000, 0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0004850, 0xCE040000,
|
||||
0xC2000002, 0xC0001ACC, 0xCE040010, 0x800000D0, 0xC2000002, 0xC0004850, 0xCE040000, 0x8000FE70,
|
||||
0xC2000000, 0xC0004850, 0xCE040000, 0xA7E60012, 0x00000000, 0xC2000002, 0xC0001B00, 0xCE040008,
|
||||
0x8000FE58, 0x00000000, 0xA7860032, 0x00000000, 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC2020002,
|
||||
0xC7E2A548, 0xC0001B00, 0xCE040000, 0x8000FE00, 0xC2040002, 0xC0001B00, 0xCE040208, 0x8000FDE0,
|
||||
0xC2C80002, 0x6AC56000, 0xDACC0000, 0xC0004854, 0xCB440000, 0xC0004848, 0xCB840000, 0xC0000838,
|
||||
0xC3C00000, 0xCBC40030, 0x5EF40004, 0x8400000A, 0xC3000000, 0xC0001ACC, 0xCF040108, 0x47BD8000,
|
||||
0x84000012, 0x47BD8000, 0x88000018, 0xC1006E8C, 0x8000B908, 0xC0004840, 0xCC840000, 0x8000F6B8,
|
||||
0xC0001AC0, 0xCAC40000, 0xC0004854, 0xCB440000, 0xA6C0FBD2, 0x00000000, 0x5EF40000, 0x8400F712,
|
||||
0x5EF40002, 0x8400F9A2, 0x5EF40004, 0x8400FBA2, 0xC1006CE8, 0x8000B880, 0x00000000, 0xC0800000,
|
||||
0xDF4B0040, 0xC0004900, 0xCB800000, 0xC2000000, 0xC000490A, 0xA78000B0, 0xCBC00000, 0xC1000000,
|
||||
0xD9000001, 0xC1000002, 0xD90C0000, 0x6FF46000, 0x47F5A000, 0x5B744C80, 0xC2400000, 0x58340004,
|
||||
0xCA400080, 0xC0004900, 0xCE000008, 0x5A640002, 0x58340004, 0xC6500080, 0xCD000080, 0xC0004914,
|
||||
0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0xC0000408, 0xCE000000, 0xA78200B8,
|
||||
0xC0004908, 0xCBC00000, 0xC1000000, 0xD9000001, 0xC1000002, 0xD90C0000, 0x6FF4A000, 0x6FD44000,
|
||||
0x4575A000, 0x47F5A000, 0x5B744E20, 0xC2800000, 0x58340006, 0xCA800080, 0xC2000000, 0xC0004900,
|
||||
0xCE000108, 0x5EA80002, 0x58340006, 0xC6900080, 0xCD000080, 0x5A7C0020, 0xC2000002, 0x6A250000,
|
||||
0xC0000408, 0xCE000000, 0xDCA80001, 0x5EA80000, 0x8400B6F0, 0x00000000, 0xA4800210, 0x00000000,
|
||||
0xC3C00000, 0xC000140E, 0xCBC00020, 0xC3400000, 0xC2400000, 0x6FF86000, 0x47F9C000, 0x5BB84C80,
|
||||
0x58380008, 0xCB400080, 0x58380006, 0xCA400080, 0x5F740002, 0x58380008, 0xC7500080, 0xCD000080,
|
||||
0xC2000000, 0x58380004, 0xCA020080, 0xC3000000, 0x5838000C, 0xCB000028, 0x5A640002, 0x46250000,
|
||||
0x8400FFF8, 0xC2400000, 0x58380006, 0xC6500080, 0xCD000080, 0xC2000000, 0x5838000A, 0xCA020080,
|
||||
0x5B300002, 0x5838000C, 0xC7100028, 0xCD000028, 0xC2420020, 0x5A200004, 0x46612000, 0x8400FFF8,
|
||||
0xC2000000, 0x5838000A, 0xC6101080, 0xCD001080, 0xC0004966, 0xCA400000, 0xC2000002, 0x6A3D0000,
|
||||
0x72252000, 0xCE400000, 0x5F740000, 0x84000028, 0xC0004912, 0xCA000000, 0xC2C00002, 0x6AFD6000,
|
||||
0x7EC16000, 0x76E10000, 0xCE000000, 0x5F300020, 0x84000028, 0xC0004924, 0xCA000000, 0xC2C00002,
|
||||
0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4820050, 0xC2400000, 0xC000140E, 0xCA408020,
|
||||
0xC2000002, 0xC0004900, 0xCE000008, 0xC000490A, 0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080,
|
||||
0xC1000004, 0xD9000001, 0xA4840288, 0x00000000, 0xC3C00000, 0xC000140E, 0xCBC10020, 0xC2800000,
|
||||
0xC2000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x5838002E, 0xCA800080,
|
||||
0x58380006, 0xCA020080, 0xC3400000, 0x5838002E, 0xCB420080, 0x5AA80002, 0x46290000, 0x8400FFF8,
|
||||
0xC2800000, 0x5838002E, 0xC6900080, 0xCD000080, 0x5F740002, 0x5838002E, 0xC7501080, 0xCD001080,
|
||||
0xC0004968, 0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0xC000492A, 0xCA800000,
|
||||
0x5E740000, 0x84000028, 0xC0004910, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000,
|
||||
0xCE000000, 0x6ABD4010, 0xA68000D2, 0x00000000, 0xC0004910, 0xCA000000, 0xC2C00002, 0x6AFD6000,
|
||||
0x7EC16000, 0x76E10000, 0xCE000000, 0x58380032, 0xCA000000, 0x58000002, 0xCA400000, 0x5838000C,
|
||||
0x00000000, 0xCE000001, 0xCE400000, 0xC000492A, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000,
|
||||
0xCE000000, 0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000, 0xCE000000, 0x80000028,
|
||||
0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4880100,
|
||||
0xC2C00000, 0xC000140E, 0xCAC20020, 0xC000490E, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x7E010000,
|
||||
0x76252000, 0xCE400000, 0xC000496A, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000,
|
||||
0x6EF0A000, 0x6ED44000, 0x45718000, 0x46F18000, 0x5B304E20, 0x58300000, 0xCA000000, 0x00000000,
|
||||
0xC2400002, 0x76252000, 0x84000032, 0xC24C0002, 0xC6E40020, 0xC624C408, 0x58300010, 0xCA400508,
|
||||
0x00000000, 0xC0001800, 0xCE400000, 0xA4860050, 0xC2400000, 0xC000140E, 0xCA418020, 0xC2020002,
|
||||
0xC0004900, 0xCE000108, 0xC0004908, 0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080, 0xC1000004,
|
||||
0xD9000001, 0xC0001408, 0xCC800000, 0xC10E0002, 0xD90C0000, 0x8000EDA8, 0xDFBC0001, 0xC000496E,
|
||||
0x99006050, 0xC9400000, 0xC7D80000, 0x00000000, 0xC5700000, 0x5EF00020, 0x88000130, 0x6F346000,
|
||||
0x4735A000, 0x5B744C80, 0x58340008, 0xC2400000, 0xCA400080, 0x00000000, 0xC2000000, 0x5A640002,
|
||||
0xCE400080, 0x58340004, 0xCA000080, 0x00000000, 0x00000000, 0x5E200002, 0xCE000080, 0xC0004912,
|
||||
0xCA800000, 0xC2400002, 0x6A712000, 0x72694000, 0xCE800000, 0x5E200000, 0x8400003A, 0xC000480A,
|
||||
0xCA000000, 0xC0000408, 0xCA800000, 0x76610000, 0x00000000, 0x72294000, 0xCE800000, 0x80000020,
|
||||
0xC0004914, 0xCA000000, 0x7E412000, 0x00000000, 0x76610000, 0xCE000000, 0x800000B8, 0x6EF4A000,
|
||||
0x6ED44000, 0x4575A000, 0x46F5A000, 0x5B744E20, 0x5834002E, 0xC2400000, 0xCA420080, 0x00000000,
|
||||
0xC2000000, 0x5A640002, 0xC6501080, 0xCD001080, 0x58340006, 0xCA000080, 0x00000000, 0x00000000,
|
||||
0x5A200002, 0xCE000080, 0xC0004910, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000,
|
||||
0xC2000002, 0x6A310000, 0xC000042A, 0xCE000000, 0xC1040002, 0xD90C0000, 0x00000000, 0x8000EB18,
|
||||
0x00000000, 0xC4980930, 0x9D000000, 0xC5580030, 0xC0000838, 0xCD840000, 0xC1440200, 0xC1C03200,
|
||||
0xC55C1078, 0xC000100E, 0x9D000000, 0xCD800000, 0xC000100C, 0xCDC00000, 0xC0004862, 0xC9C00000,
|
||||
0x00000000, 0x00000000, 0xD9D80001, 0xC0007200, 0x401C0000, 0x5DC07400, 0x8800FFFA, 0x5C000200,
|
||||
0xCD800000, 0xC1F0000A, 0x71D4A000, 0xDD980000, 0xDD9C0001, 0x41D8E000, 0xC5D40268, 0xC0001010,
|
||||
0xCD400000, 0x6C9C8000, 0x449CE000, 0x449CE000, 0x59DC0004, 0xC1601260, 0xC5D40268, 0x9D000000,
|
||||
0xC0001012, 0xCD400000, 0x00000000, 0x00000000, 0xD9580000, 0x6D586000, 0x4558C000, 0x59984C80,
|
||||
0xD9980001, 0x5818000A, 0xC1800000, 0xC9800080, 0xC0005400, 0x6D5CA000, 0x401C0000, 0x40180000,
|
||||
0xC9400000, 0x58000002, 0x00000000, 0xC9C00000, 0xC0004930, 0xCD400000, 0xC0004932, 0xCDC00000,
|
||||
0x59980004, 0xC1C20020, 0xB59CFFF8, 0x00000000, 0xC1800000, 0xDD9C0001, 0x581C000A, 0xCD800080,
|
||||
0x581C000C, 0xC1800000, 0xC9800028, 0xC1C00002, 0xDD940000, 0x69D4E000, 0x5D980002, 0xCD800028,
|
||||
0xC0004924, 0xC9800000, 0x00000000, 0x9D000000, 0x00000000, 0x71D8C000, 0xCD800000, 0xC000492A,
|
||||
0xC9400000, 0xC1C00002, 0x69D8E000, 0x7DC0C000, 0x7594A000, 0xCD400000, 0xC000492C, 0xC9400000,
|
||||
0xDD800001, 0x58000032, 0x75D4A000, 0x84000078, 0xC9400001, 0xC9800000, 0xDD800001, 0x5800000C,
|
||||
0x00000000, 0xCD400001, 0xCD800000, 0xC000492C, 0xC9400000, 0xC000492A, 0xC9800000, 0x71D4A000,
|
||||
0xC000492C, 0xCD400000, 0x71D8C000, 0xC000492A, 0xCD800000, 0x9D000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0xC0004862, 0xC9800000, 0x00000000, 0xC1C00200, 0x4194C000, 0x45D8E000, 0x8800FFFA,
|
||||
0xC5D80000, 0xC0004862, 0xCD800000, 0xC0001406, 0xC9800000, 0xC1C00002, 0x9D000000, 0xC5D80A08,
|
||||
0xC5581050, 0xCD800000, 0xC0004930, 0xC9800000, 0xC0004932, 0xC9C00000, 0xC140000E, 0xC5581C20,
|
||||
0xDD940000, 0xC0007200, 0x40140000, 0x5D407400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0x58000002,
|
||||
0x5D407400, 0x8800FFFA, 0x5C000200, 0xCDC00000, 0xDD540000, 0xC1C00000, 0x58140006, 0xC9C20080,
|
||||
0xC1800000, 0x58140000, 0xC98000E0, 0x6DDC2000, 0xC000491E, 0x41D8E000, 0xCDC00000, 0xDD980000,
|
||||
0xC1C00022, 0xC5D80D78, 0xDD940001, 0xC5581C20, 0xC000491C, 0xCD800000, 0xDD540000, 0xC1C00000,
|
||||
0x58140006, 0xC9C20080, 0xC1800000, 0x58140004, 0xC9820080, 0x00000000, 0x59DC0002, 0x459CC000,
|
||||
0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140006, 0xC5D81080, 0xCD801080, 0xC0004860, 0xC9400000,
|
||||
0xC1800100, 0xC1D00002, 0x58146B00, 0xD5800000, 0x58000002, 0xD5800001, 0x59540004, 0xB558FFF8,
|
||||
0xC0004860, 0xC1400000, 0xCD400000, 0xDD980001, 0x9D000000, 0xDD940000, 0xC0001404, 0xCDC00808,
|
||||
0xC1C00000, 0xC1800200, 0x5D980004, 0xDF5D0050, 0x45D8A000, 0x8800FFDA, 0xDD800001, 0x5800000C,
|
||||
0x00000000, 0xC9400001, 0xC9800000, 0xC1C00002, 0xC5D43F08, 0xC5D81E08, 0xC0004862, 0xC9C00000,
|
||||
0x00000000, 0x00000000, 0x581C7200, 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD400000, 0x58000002,
|
||||
0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0xC0004862, 0xC9C00000, 0x00000000, 0xC15004C0,
|
||||
0xC5D40068, 0xDD9C0000, 0xC5D41C20, 0xC1C00000, 0xDD800001, 0x58000030, 0xC9C00080, 0xDD800001,
|
||||
0x58000002, 0xC9800000, 0x6DDC2000, 0xC000491C, 0x41D8E000, 0xCD400001, 0xCDC00000, 0xDD940001,
|
||||
0xC1C00000, 0x58140030, 0xC9C00080, 0xC1800000, 0x58140006, 0xC9820080, 0x00000000, 0x59DC0002,
|
||||
0x459CC000, 0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140030, 0xC5D80080, 0xCD800080, 0xC1C00000,
|
||||
0xDF5C0040, 0x5DDC0080, 0x8400FFD2, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0xC160FFFE, 0xC0000A10, 0xC9440068, 0xC1A0FFFE, 0x59980E28, 0xC000100C, 0xCD400000, 0xC000100E,
|
||||
0xCD800000, 0xC0004964, 0xC9800000, 0x00000000, 0xC170000A, 0x7194A000, 0x6C988000, 0x4498C000,
|
||||
0x4498C000, 0x59980004, 0xC5940278, 0xC0001010, 0xCD400000, 0xC0004946, 0xC9400000, 0x00000000,
|
||||
0x00000000, 0x6D58A000, 0x6D5C4000, 0x45D8C000, 0x4558C000, 0xC000494A, 0xC9400000, 0xC0004948,
|
||||
0xC9C00000, 0x4194C000, 0xC1400012, 0xC55C1820, 0x9D000000, 0xC59C0270, 0xC0001012, 0xCDC00000,
|
||||
0xC1400000, 0x58000012, 0xC9410040, 0xC0004950, 0xC9C00000, 0xC5580000, 0xC5940840, 0xC5581080,
|
||||
0xD9940000, 0xC000493C, 0xC9400000, 0xC0004954, 0xC9800000, 0x59DC00A8, 0x455CE000, 0x41D8E000,
|
||||
0x5D5C0030, 0x8800FFF8, 0xC1C00030, 0xC1800000, 0xC5D84030, 0xC1400000, 0xC5D40010, 0x5DD40002,
|
||||
0x8400005A, 0x5DD40004, 0x84000082, 0x5DD40006, 0x840000AA, 0x5DD80026, 0x840000D2, 0xDD540000,
|
||||
0xDD800001, 0x58000008, 0x40180000, 0xCD400000, 0x59980002, 0x8000FFA8, 0xDD540000, 0xDD800001,
|
||||
0x58000008, 0x40180000, 0xCD4000C0, 0x59980002, 0x8000FF70, 0xDD540000, 0xDD800001, 0x58000008,
|
||||
0x40180000, 0xCD400080, 0x59980002, 0x8000FF38, 0xDD540000, 0xDD800001, 0x58000008, 0x40180000,
|
||||
0xCD400040, 0x59980002, 0x8000FF00, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x58000012, 0xC9400000, 0xC0004954, 0xC9C00000, 0xC0004950, 0xC9400080, 0xDD800001, 0x58000028,
|
||||
0x5D9C0000, 0x8400003A, 0x5D9C0002, 0x8400003A, 0x5D9C0004, 0x84000052, 0xC55B0040, 0xC55C08C0,
|
||||
0xCD800041, 0xCDC008C0, 0x80000048, 0xCD400000, 0x80000038, 0xC55900C0, 0xC55C1840, 0xCD8000C1,
|
||||
0xCDC01840, 0x80000010, 0xC55A0080, 0xC55C1080, 0xCD800081, 0xCDC01080, 0x9D000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x59540002, 0x6994E018, 0x61C0C008, 0x4194A000, 0x5D940040, 0x8800FFFA,
|
||||
0xC5940000, 0x9D000000, 0xCD400000, 0x00000000, 0x00000000, 0x9D000000, 0x4158A000, 0xCD400000,
|
||||
0x00000000,
|
||||
};
|
||||
|
||||
static unsigned int firmware_binary_data[] = {
|
||||
};
|
||||
|
||||
|
||||
#endif // IFXMIPS_ATM_FW_DANUBE_H
|
||||
364
package/ifxmips-dsl-api/src/ifxmips_atm_fw_regs_common.h
Normal file
364
package/ifxmips-dsl-api/src/ifxmips_atm_fw_regs_common.h
Normal file
@@ -0,0 +1,364 @@
|
||||
#ifndef IFXMIPS_ATM_FW_REGS_COMMON_H
|
||||
#define IFXMIPS_ATM_FW_REGS_COMMON_H
|
||||
|
||||
|
||||
|
||||
#if defined(CONFIG_DANUBE)
|
||||
#include "ifxmips_atm_fw_regs_danube.h"
|
||||
#elif defined(CONFIG_AMAZON_SE)
|
||||
#include "ifxmips_atm_fw_regs_amazon_se.h"
|
||||
#elif defined(CONFIG_AR9)
|
||||
#include "ifxmips_atm_fw_regs_ar9.h"
|
||||
#elif defined(CONFIG_VR9)
|
||||
#include "ifxmips_atm_fw_regs_vr9.h"
|
||||
#else
|
||||
#error Platform is not specified!
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* PPE ATM Cell Header
|
||||
*/
|
||||
#if defined(__BIG_ENDIAN)
|
||||
struct uni_cell_header {
|
||||
unsigned int gfc :4;
|
||||
unsigned int vpi :8;
|
||||
unsigned int vci :16;
|
||||
unsigned int pti :3;
|
||||
unsigned int clp :1;
|
||||
};
|
||||
#else
|
||||
struct uni_cell_header {
|
||||
unsigned int clp :1;
|
||||
unsigned int pti :3;
|
||||
unsigned int vci :16;
|
||||
unsigned int vpi :8;
|
||||
unsigned int gfc :4;
|
||||
};
|
||||
#endif // defined(__BIG_ENDIAN)
|
||||
|
||||
/*
|
||||
* Inband Header and Trailer
|
||||
*/
|
||||
#if defined(__BIG_ENDIAN)
|
||||
struct rx_inband_trailer {
|
||||
/* 0 - 3h */
|
||||
unsigned int uu :8;
|
||||
unsigned int cpi :8;
|
||||
unsigned int stw_res1:4;
|
||||
unsigned int stw_clp :1;
|
||||
unsigned int stw_ec :1;
|
||||
unsigned int stw_uu :1;
|
||||
unsigned int stw_cpi :1;
|
||||
unsigned int stw_ovz :1;
|
||||
unsigned int stw_mfl :1;
|
||||
unsigned int stw_usz :1;
|
||||
unsigned int stw_crc :1;
|
||||
unsigned int stw_il :1;
|
||||
unsigned int stw_ra :1;
|
||||
unsigned int stw_res2:2;
|
||||
/* 4 - 7h */
|
||||
unsigned int gfc :4;
|
||||
unsigned int vpi :8;
|
||||
unsigned int vci :16;
|
||||
unsigned int pti :3;
|
||||
unsigned int clp :1;
|
||||
};
|
||||
|
||||
struct tx_inband_header {
|
||||
/* 0 - 3h */
|
||||
unsigned int gfc :4;
|
||||
unsigned int vpi :8;
|
||||
unsigned int vci :16;
|
||||
unsigned int pti :3;
|
||||
unsigned int clp :1;
|
||||
/* 4 - 7h */
|
||||
unsigned int uu :8;
|
||||
unsigned int cpi :8;
|
||||
unsigned int pad :8;
|
||||
unsigned int res1 :8;
|
||||
};
|
||||
#else
|
||||
struct rx_inband_trailer {
|
||||
/* 0 - 3h */
|
||||
unsigned int stw_res2:2;
|
||||
unsigned int stw_ra :1;
|
||||
unsigned int stw_il :1;
|
||||
unsigned int stw_crc :1;
|
||||
unsigned int stw_usz :1;
|
||||
unsigned int stw_mfl :1;
|
||||
unsigned int stw_ovz :1;
|
||||
unsigned int stw_cpi :1;
|
||||
unsigned int stw_uu :1;
|
||||
unsigned int stw_ec :1;
|
||||
unsigned int stw_clp :1;
|
||||
unsigned int stw_res1:4;
|
||||
unsigned int cpi :8;
|
||||
unsigned int uu :8;
|
||||
/* 4 - 7h */
|
||||
unsigned int clp :1;
|
||||
unsigned int pti :3;
|
||||
unsigned int vci :16;
|
||||
unsigned int vpi :8;
|
||||
unsigned int gfc :4;
|
||||
};
|
||||
|
||||
struct tx_inband_header {
|
||||
/* 0 - 3h */
|
||||
unsigned int clp :1;
|
||||
unsigned int pti :3;
|
||||
unsigned int vci :16;
|
||||
unsigned int vpi :8;
|
||||
unsigned int gfc :4;
|
||||
/* 4 - 7h */
|
||||
unsigned int res1 :8;
|
||||
unsigned int pad :8;
|
||||
unsigned int cpi :8;
|
||||
unsigned int uu :8;
|
||||
};
|
||||
#endif // defined(__BIG_ENDIAN)
|
||||
|
||||
/*
|
||||
* MIB Table Maintained by Firmware
|
||||
*/
|
||||
struct wan_mib_table {
|
||||
u32 res1;
|
||||
u32 wrx_drophtu_cell;
|
||||
u32 wrx_dropdes_pdu;
|
||||
u32 wrx_correct_pdu;
|
||||
u32 wrx_err_pdu;
|
||||
u32 wrx_dropdes_cell;
|
||||
u32 wrx_correct_cell;
|
||||
u32 wrx_err_cell;
|
||||
u32 wrx_total_byte;
|
||||
u32 res2;
|
||||
u32 wtx_total_pdu;
|
||||
u32 wtx_total_cell;
|
||||
u32 wtx_total_byte;
|
||||
};
|
||||
|
||||
/*
|
||||
* Host-PPE Communication Data Structure
|
||||
*/
|
||||
|
||||
#if defined(__BIG_ENDIAN)
|
||||
struct wrx_queue_config {
|
||||
/* 0h */
|
||||
unsigned int res2 :27;
|
||||
unsigned int dmach :4;
|
||||
unsigned int errdp :1;
|
||||
/* 1h */
|
||||
unsigned int oversize :16;
|
||||
unsigned int undersize :16;
|
||||
/* 2h */
|
||||
unsigned int res1 :16;
|
||||
unsigned int mfs :16;
|
||||
/* 3h */
|
||||
unsigned int uumask :8;
|
||||
unsigned int cpimask :8;
|
||||
unsigned int uuexp :8;
|
||||
unsigned int cpiexp :8;
|
||||
};
|
||||
|
||||
struct wtx_port_config {
|
||||
unsigned int res1 :27;
|
||||
unsigned int qid :4;
|
||||
unsigned int qsben :1;
|
||||
};
|
||||
|
||||
struct wtx_queue_config {
|
||||
unsigned int res1 :25;
|
||||
unsigned int sbid :1;
|
||||
unsigned int res2 :3;
|
||||
unsigned int type :2;
|
||||
unsigned int qsben :1;
|
||||
};
|
||||
|
||||
struct wrx_dma_channel_config {
|
||||
/* 0h */
|
||||
unsigned int res1 :1;
|
||||
unsigned int mode :2;
|
||||
unsigned int rlcfg :1;
|
||||
unsigned int desba :28;
|
||||
/* 1h */
|
||||
unsigned int chrl :16;
|
||||
unsigned int clp1th :16;
|
||||
/* 2h */
|
||||
unsigned int deslen :16;
|
||||
unsigned int vlddes :16;
|
||||
};
|
||||
|
||||
struct wtx_dma_channel_config {
|
||||
/* 0h */
|
||||
unsigned int res2 :1;
|
||||
unsigned int mode :2;
|
||||
unsigned int res3 :1;
|
||||
unsigned int desba :28;
|
||||
/* 1h */
|
||||
unsigned int res1 :32;
|
||||
/* 2h */
|
||||
unsigned int deslen :16;
|
||||
unsigned int vlddes :16;
|
||||
};
|
||||
|
||||
struct htu_entry {
|
||||
unsigned int res1 :1;
|
||||
unsigned int clp :1;
|
||||
unsigned int pid :2;
|
||||
unsigned int vpi :8;
|
||||
unsigned int vci :16;
|
||||
unsigned int pti :3;
|
||||
unsigned int vld :1;
|
||||
};
|
||||
|
||||
struct htu_mask {
|
||||
unsigned int set :1;
|
||||
unsigned int clp :1;
|
||||
unsigned int pid_mask :2;
|
||||
unsigned int vpi_mask :8;
|
||||
unsigned int vci_mask :16;
|
||||
unsigned int pti_mask :3;
|
||||
unsigned int clear :1;
|
||||
};
|
||||
|
||||
struct htu_result {
|
||||
unsigned int res1 :12;
|
||||
unsigned int cellid :4;
|
||||
unsigned int res2 :5;
|
||||
unsigned int type :1;
|
||||
unsigned int ven :1;
|
||||
unsigned int res3 :5;
|
||||
unsigned int qid :4;
|
||||
};
|
||||
|
||||
struct rx_descriptor {
|
||||
/* 0 - 3h */
|
||||
unsigned int own :1;
|
||||
unsigned int c :1;
|
||||
unsigned int sop :1;
|
||||
unsigned int eop :1;
|
||||
unsigned int res1 :3;
|
||||
unsigned int byteoff :2;
|
||||
unsigned int res2 :2;
|
||||
unsigned int id :4;
|
||||
unsigned int err :1;
|
||||
unsigned int datalen :16;
|
||||
/* 4 - 7h */
|
||||
unsigned int res3 :4;
|
||||
unsigned int dataptr :28;
|
||||
};
|
||||
|
||||
struct tx_descriptor {
|
||||
/* 0 - 3h */
|
||||
unsigned int own :1;
|
||||
unsigned int c :1;
|
||||
unsigned int sop :1;
|
||||
unsigned int eop :1;
|
||||
unsigned int byteoff :5;
|
||||
unsigned int res1 :5;
|
||||
unsigned int iscell :1;
|
||||
unsigned int clp :1;
|
||||
unsigned int datalen :16;
|
||||
/* 4 - 7h */
|
||||
unsigned int res2 :4;
|
||||
unsigned int dataptr :28;
|
||||
};
|
||||
#else
|
||||
struct wrx_queue_config {
|
||||
/* 0h */
|
||||
unsigned int errdp :1;
|
||||
unsigned int dmach :4;
|
||||
unsigned int res2 :27;
|
||||
/* 1h */
|
||||
unsigned int undersize :16;
|
||||
unsigned int oversize :16;
|
||||
/* 2h */
|
||||
unsigned int mfs :16;
|
||||
unsigned int res1 :16;
|
||||
/* 3h */
|
||||
unsigned int cpiexp :8;
|
||||
unsigned int uuexp :8;
|
||||
unsigned int cpimask :8;
|
||||
unsigned int uumask :8;
|
||||
};
|
||||
|
||||
struct wtx_port_config {
|
||||
unsigned int qsben :1;
|
||||
unsigned int qid :4;
|
||||
unsigned int res1 :27;
|
||||
};
|
||||
|
||||
struct wtx_queue_config {
|
||||
unsigned int qsben :1;
|
||||
unsigned int type :2;
|
||||
unsigned int res2 :3;
|
||||
unsigned int sbid :1;
|
||||
unsigned int res1 :25;
|
||||
};
|
||||
|
||||
struct wrx_dma_channel_config
|
||||
{
|
||||
/* 0h */
|
||||
unsigned int desba :28;
|
||||
unsigned int rlcfg :1;
|
||||
unsigned int mode :2;
|
||||
unsigned int res1 :1;
|
||||
/* 1h */
|
||||
unsigned int clp1th :16;
|
||||
unsigned int chrl :16;
|
||||
/* 2h */
|
||||
unsigned int vlddes :16;
|
||||
unsigned int deslen :16;
|
||||
};
|
||||
|
||||
struct wtx_dma_channel_config {
|
||||
/* 0h */
|
||||
unsigned int desba :28;
|
||||
unsigned int res3 :1;
|
||||
unsigned int mode :2;
|
||||
unsigned int res2 :1;
|
||||
/* 1h */
|
||||
unsigned int res1 :32;
|
||||
/* 2h */
|
||||
unsigned int vlddes :16;
|
||||
unsigned int deslen :16;
|
||||
};
|
||||
|
||||
struct rx_descriptor {
|
||||
/* 4 - 7h */
|
||||
unsigned int dataptr :28;
|
||||
unsigned int res3 :4;
|
||||
/* 0 - 3h */
|
||||
unsigned int datalen :16;
|
||||
unsigned int err :1;
|
||||
unsigned int id :4;
|
||||
unsigned int res2 :2;
|
||||
unsigned int byteoff :2;
|
||||
unsigned int res1 :3;
|
||||
unsigned int eop :1;
|
||||
unsigned int sop :1;
|
||||
unsigned int c :1;
|
||||
unsigned int own :1;
|
||||
};
|
||||
|
||||
struct tx_descriptor {
|
||||
/* 4 - 7h */
|
||||
unsigned int dataptr :28;
|
||||
unsigned int res2 :4;
|
||||
/* 0 - 3h */
|
||||
unsigned int datalen :16;
|
||||
unsigned int clp :1;
|
||||
unsigned int iscell :1;
|
||||
unsigned int res1 :5;
|
||||
unsigned int byteoff :5;
|
||||
unsigned int eop :1;
|
||||
unsigned int sop :1;
|
||||
unsigned int c :1;
|
||||
unsigned int own :1;
|
||||
};
|
||||
#endif // defined(__BIG_ENDIAN)
|
||||
|
||||
|
||||
|
||||
#endif // IFXMIPS_ATM_FW_REGS_COMMON_H
|
||||
30
package/ifxmips-dsl-api/src/ifxmips_atm_fw_regs_danube.h
Normal file
30
package/ifxmips-dsl-api/src/ifxmips_atm_fw_regs_danube.h
Normal file
@@ -0,0 +1,30 @@
|
||||
#ifndef IFXMIPS_ATM_FW_REGS_DANUBE_H
|
||||
#define IFXMIPS_ATM_FW_REGS_DANUBE_H
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Host-PPE Communication Data Address Mapping
|
||||
*/
|
||||
#define FW_VER_ID SB_BUFFER(0x2001)
|
||||
#define CFG_WRX_HTUTS SB_BUFFER(0x2400) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */
|
||||
#define CFG_WRX_QNUM SB_BUFFER(0x2401) /* WAN RX Queue Number */
|
||||
#define CFG_WRX_DCHNUM SB_BUFFER(0x2402) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */
|
||||
#define CFG_WTX_DCHNUM SB_BUFFER(0x2403) /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */
|
||||
#define CFG_WRDES_DELAY SB_BUFFER(0x2404) /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */
|
||||
#define WRX_DMACH_ON SB_BUFFER(0x2405) /* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */
|
||||
#define WTX_DMACH_ON SB_BUFFER(0x2406) /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */
|
||||
#define WRX_HUNT_BITTH SB_BUFFER(0x2407) /* WAN RX HUNT Threshold, must be between 2 to 8. */
|
||||
#define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config*) SB_BUFFER(0x2500 + (i) * 20))
|
||||
#define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config*) SB_BUFFER(0x2640 + (i) * 7))
|
||||
#define WTX_PORT_CONFIG(i) ((struct wtx_port_config*) SB_BUFFER(0x2440 + (i)))
|
||||
#define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config*) SB_BUFFER(0x2710 + (i) * 27))
|
||||
#define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config*) SB_BUFFER(0x2711 + (i) * 27))
|
||||
#define WAN_MIB_TABLE ((struct wan_mib_table*) SB_BUFFER(0x2410))
|
||||
#define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2000 + (i)))
|
||||
#define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2020 + (i)))
|
||||
#define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2040 + (i)))
|
||||
|
||||
|
||||
|
||||
#endif // IFXMIPS_ATM_FW_REGS_DANUBE_H
|
||||
231
package/ifxmips-dsl-api/src/ifxmips_atm_ppe_common.h
Normal file
231
package/ifxmips-dsl-api/src/ifxmips_atm_ppe_common.h
Normal file
@@ -0,0 +1,231 @@
|
||||
#ifndef IFXMIPS_ATM_PPE_COMMON_H
|
||||
#define IFXMIPS_ATM_PPE_COMMON_H
|
||||
|
||||
|
||||
|
||||
#if defined(CONFIG_DANUBE)
|
||||
#include "ifxmips_atm_ppe_danube.h"
|
||||
#elif defined(CONFIG_AMAZON_SE)
|
||||
#include "ifxmips_atm_ppe_amazon_se.h"
|
||||
#elif defined(CONFIG_AR9)
|
||||
#include "ifxmips_atm_ppe_ar9.h"
|
||||
#elif defined(CONFIG_VR9)
|
||||
#include "ifxmips_atm_ppe_vr9.h"
|
||||
#else
|
||||
#error Platform is not specified!
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Code/Data Memory (CDM) Interface Configuration Register
|
||||
*/
|
||||
#define CDM_CFG PPE_REG_ADDR(0x0100)
|
||||
|
||||
#define CDM_CFG_RAM1 GET_BITS(*CDM_CFG, 3, 2)
|
||||
#define CDM_CFG_RAM0 (*CDM_CFG & (1 << 1))
|
||||
|
||||
#define CDM_CFG_RAM1_SET(value) SET_BITS(0, 3, 2, value)
|
||||
#define CDM_CFG_RAM0_SET(value) ((value) ? (1 << 1) : 0)
|
||||
|
||||
/*
|
||||
* QSB Internal Cell Delay Variation Register
|
||||
*/
|
||||
#define QSB_ICDV QSB_CONF_REG_ADDR(0x0007)
|
||||
|
||||
#define QSB_ICDV_TAU GET_BITS(*QSB_ICDV, 5, 0)
|
||||
|
||||
#define QSB_ICDV_TAU_SET(value) SET_BITS(0, 5, 0, value)
|
||||
|
||||
/*
|
||||
* QSB Scheduler Burst Limit Register
|
||||
*/
|
||||
#define QSB_SBL QSB_CONF_REG_ADDR(0x0009)
|
||||
|
||||
#define QSB_SBL_SBL GET_BITS(*QSB_SBL, 3, 0)
|
||||
|
||||
#define QSB_SBL_SBL_SET(value) SET_BITS(0, 3, 0, value)
|
||||
|
||||
/*
|
||||
* QSB Configuration Register
|
||||
*/
|
||||
#define QSB_CFG QSB_CONF_REG_ADDR(0x000A)
|
||||
|
||||
#define QSB_CFG_TSTEPC GET_BITS(*QSB_CFG, 1, 0)
|
||||
|
||||
#define QSB_CFG_TSTEPC_SET(value) SET_BITS(0, 1, 0, value)
|
||||
|
||||
/*
|
||||
* QSB RAM Transfer Table Register
|
||||
*/
|
||||
#define QSB_RTM QSB_CONF_REG_ADDR(0x000B)
|
||||
|
||||
#define QSB_RTM_DM (*QSB_RTM)
|
||||
|
||||
#define QSB_RTM_DM_SET(value) ((value) & 0xFFFFFFFF)
|
||||
|
||||
/*
|
||||
* QSB RAM Transfer Data Register
|
||||
*/
|
||||
#define QSB_RTD QSB_CONF_REG_ADDR(0x000C)
|
||||
|
||||
#define QSB_RTD_TTV (*QSB_RTD)
|
||||
|
||||
#define QSB_RTD_TTV_SET(value) ((value) & 0xFFFFFFFF)
|
||||
|
||||
/*
|
||||
* QSB RAM Access Register
|
||||
*/
|
||||
#define QSB_RAMAC QSB_CONF_REG_ADDR(0x000D)
|
||||
|
||||
#define QSB_RAMAC_RW (*QSB_RAMAC & (1 << 31))
|
||||
#define QSB_RAMAC_TSEL GET_BITS(*QSB_RAMAC, 27, 24)
|
||||
#define QSB_RAMAC_LH (*QSB_RAMAC & (1 << 16))
|
||||
#define QSB_RAMAC_TESEL GET_BITS(*QSB_RAMAC, 9, 0)
|
||||
|
||||
#define QSB_RAMAC_RW_SET(value) ((value) ? (1 << 31) : 0)
|
||||
#define QSB_RAMAC_TSEL_SET(value) SET_BITS(0, 27, 24, value)
|
||||
#define QSB_RAMAC_LH_SET(value) ((value) ? (1 << 16) : 0)
|
||||
#define QSB_RAMAC_TESEL_SET(value) SET_BITS(0, 9, 0, value)
|
||||
|
||||
/*
|
||||
* QSB Queue Scheduling and Shaping Definitions
|
||||
*/
|
||||
#define QSB_WFQ_NONUBR_MAX 0x3f00
|
||||
#define QSB_WFQ_UBR_BYPASS 0x3fff
|
||||
#define QSB_TP_TS_MAX 65472
|
||||
#define QSB_TAUS_MAX 64512
|
||||
#define QSB_GCR_MIN 18
|
||||
|
||||
/*
|
||||
* QSB Constant
|
||||
*/
|
||||
#define QSB_RAMAC_RW_READ 0
|
||||
#define QSB_RAMAC_RW_WRITE 1
|
||||
|
||||
#define QSB_RAMAC_TSEL_QPT 0x01
|
||||
#define QSB_RAMAC_TSEL_SCT 0x02
|
||||
#define QSB_RAMAC_TSEL_SPT 0x03
|
||||
#define QSB_RAMAC_TSEL_VBR 0x08
|
||||
|
||||
#define QSB_RAMAC_LH_LOW 0
|
||||
#define QSB_RAMAC_LH_HIGH 1
|
||||
|
||||
#define QSB_QPT_SET_MASK 0x0
|
||||
#define QSB_QVPT_SET_MASK 0x0
|
||||
#define QSB_SET_SCT_MASK 0x0
|
||||
#define QSB_SET_SPT_MASK 0x0
|
||||
#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF
|
||||
|
||||
#define QSB_SPT_SBV_VALID (1 << 31)
|
||||
#define QSB_SPT_PN_SET(value) (((value) & 0x01) ? (1 << 16) : 0)
|
||||
#define QSB_SPT_INTRATE_SET(value) SET_BITS(0, 13, 0, value)
|
||||
|
||||
/*
|
||||
* QSB Queue Parameter Table Entry and Queue VBR Parameter Table Entry
|
||||
*/
|
||||
#if defined(__BIG_ENDIAN)
|
||||
union qsb_queue_parameter_table {
|
||||
struct {
|
||||
unsigned int res1 :1;
|
||||
unsigned int vbr :1;
|
||||
unsigned int wfqf :14;
|
||||
unsigned int tp :16;
|
||||
} bit;
|
||||
u32 dword;
|
||||
};
|
||||
|
||||
union qsb_queue_vbr_parameter_table {
|
||||
struct {
|
||||
unsigned int taus :16;
|
||||
unsigned int ts :16;
|
||||
} bit;
|
||||
u32 dword;
|
||||
};
|
||||
#else
|
||||
union qsb_queue_parameter_table {
|
||||
struct {
|
||||
unsigned int tp :16;
|
||||
unsigned int wfqf :14;
|
||||
unsigned int vbr :1;
|
||||
unsigned int res1 :1;
|
||||
} bit;
|
||||
u32 dword;
|
||||
};
|
||||
|
||||
union qsb_queue_vbr_parameter_table {
|
||||
struct {
|
||||
unsigned int ts :16;
|
||||
unsigned int taus :16;
|
||||
} bit;
|
||||
u32 dword;
|
||||
};
|
||||
#endif // defined(__BIG_ENDIAN)
|
||||
|
||||
/*
|
||||
* Mailbox IGU0 Registers
|
||||
*/
|
||||
#define MBOX_IGU0_ISRS PPE_REG_ADDR(0x0200)
|
||||
#define MBOX_IGU0_ISRC PPE_REG_ADDR(0x0201)
|
||||
#define MBOX_IGU0_ISR PPE_REG_ADDR(0x0202)
|
||||
#define MBOX_IGU0_IER PPE_REG_ADDR(0x0203)
|
||||
|
||||
#define MBOX_IGU0_ISRS_SET(n) (1 << (n))
|
||||
#define MBOX_IGU0_ISRC_CLEAR(n) (1 << (n))
|
||||
#define MBOX_IGU0_ISR_ISR(n) (*MBOX_IGU0_ISR & (1 << (n)))
|
||||
#define MBOX_IGU0_IER_EN(n) (*MBOX_IGU0_IER & (1 << (n)))
|
||||
#define MBOX_IGU0_IER_EN_SET(n) (1 << (n))
|
||||
|
||||
/*
|
||||
* Mailbox IGU1 Registers
|
||||
*/
|
||||
#define MBOX_IGU1_ISRS PPE_REG_ADDR(0x0204)
|
||||
#define MBOX_IGU1_ISRC PPE_REG_ADDR(0x0205)
|
||||
#define MBOX_IGU1_ISR PPE_REG_ADDR(0x0206)
|
||||
#define MBOX_IGU1_IER PPE_REG_ADDR(0x0207)
|
||||
|
||||
#define MBOX_IGU1_ISRS_SET(n) (1 << (n))
|
||||
#define MBOX_IGU1_ISRC_CLEAR(n) (1 << (n))
|
||||
#define MBOX_IGU1_ISR_ISR(n) (*MBOX_IGU1_ISR & (1 << (n)))
|
||||
#define MBOX_IGU1_IER_EN(n) (*MBOX_IGU1_IER & (1 << (n)))
|
||||
#define MBOX_IGU1_IER_EN_SET(n) (1 << (n))
|
||||
|
||||
/*
|
||||
* Mailbox IGU3 Registers
|
||||
*/
|
||||
#define MBOX_IGU3_ISRS PPE_REG_ADDR(0x0214)
|
||||
#define MBOX_IGU3_ISRC PPE_REG_ADDR(0x0215)
|
||||
#define MBOX_IGU3_ISR PPE_REG_ADDR(0x0216)
|
||||
#define MBOX_IGU3_IER PPE_REG_ADDR(0x0217)
|
||||
|
||||
#define MBOX_IGU3_ISRS_SET(n) (1 << (n))
|
||||
#define MBOX_IGU3_ISRC_CLEAR(n) (1 << (n))
|
||||
#define MBOX_IGU3_ISR_ISR(n) (*MBOX_IGU3_ISR & (1 << (n)))
|
||||
#define MBOX_IGU3_IER_EN(n) (*MBOX_IGU3_IER & (1 << (n)))
|
||||
#define MBOX_IGU3_IER_EN_SET(n) (1 << (n))
|
||||
|
||||
/*
|
||||
* RTHA/TTHA Registers
|
||||
*/
|
||||
#define SFSM_STATE0 PPE_REG_ADDR(0x0410)
|
||||
#define SFSM_STATE1 PPE_REG_ADDR(0x0411)
|
||||
#define SFSM_DBA0 PPE_REG_ADDR(0x0412)
|
||||
#define SFSM_DBA1 PPE_REG_ADDR(0x0413)
|
||||
#define SFSM_CBA0 PPE_REG_ADDR(0x0414)
|
||||
#define SFSM_CBA1 PPE_REG_ADDR(0x0415)
|
||||
#define SFSM_CFG0 PPE_REG_ADDR(0x0416)
|
||||
#define SFSM_CFG1 PPE_REG_ADDR(0x0417)
|
||||
#define SFSM_PGCNT0 PPE_REG_ADDR(0x041C)
|
||||
#define SFSM_PGCNT1 PPE_REG_ADDR(0x041D)
|
||||
#define FFSM_DBA0 PPE_REG_ADDR(0x0508)
|
||||
#define FFSM_DBA1 PPE_REG_ADDR(0x0509)
|
||||
#define FFSM_CFG0 PPE_REG_ADDR(0x050A)
|
||||
#define FFSM_CFG1 PPE_REG_ADDR(0x050B)
|
||||
#define FFSM_IDLE_HEAD_BC0 PPE_REG_ADDR(0x050E)
|
||||
#define FFSM_IDLE_HEAD_BC1 PPE_REG_ADDR(0x050F)
|
||||
#define FFSM_PGCNT0 PPE_REG_ADDR(0x0514)
|
||||
#define FFSM_PGCNT1 PPE_REG_ADDR(0x0515)
|
||||
|
||||
|
||||
|
||||
#endif // IFXMIPS_ATM_PPE_COMMON_H
|
||||
100
package/ifxmips-dsl-api/src/ifxmips_atm_ppe_danube.h
Normal file
100
package/ifxmips-dsl-api/src/ifxmips_atm_ppe_danube.h
Normal file
@@ -0,0 +1,100 @@
|
||||
#ifndef IFXMIPS_ATM_PPE_DANUBE_H
|
||||
#define IFXMIPS_ATM_PPE_DANUBE_H
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* FPI Configuration Bus Register and Memory Address Mapping
|
||||
*/
|
||||
#define IFX_PPE (KSEG1 | 0x1E180000)
|
||||
#define PP32_DEBUG_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))
|
||||
#define PPM_INT_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))
|
||||
#define PP32_INTERNAL_RES_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))
|
||||
#define CDM_CODE_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))
|
||||
#define PPE_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))
|
||||
#define CDM_DATA_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))
|
||||
#define PPM_INT_UNIT_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))
|
||||
#define PPM_TIMER0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))
|
||||
#define PPM_TASK_IND_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))
|
||||
#define PPS_BRK_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))
|
||||
#define PPM_TIMER1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))
|
||||
#define SB_RAM0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2)))
|
||||
#define SB_RAM1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8400) << 2)))
|
||||
#define SB_RAM2_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2)))
|
||||
#define SB_RAM3_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9600) << 2)))
|
||||
#define QSB_CONF_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))
|
||||
|
||||
/*
|
||||
* DWORD-Length of Memory Blocks
|
||||
*/
|
||||
#define PP32_DEBUG_REG_DWLEN 0x0030
|
||||
#define PPM_INT_REG_DWLEN 0x0010
|
||||
#define PP32_INTERNAL_RES_DWLEN 0x00C0
|
||||
#define CDM_CODE_MEMORYn_DWLEN(n) ((n) == 0 ? 0x1000 : 0x0800)
|
||||
#define PPE_REG_DWLEN 0x1000
|
||||
#define CDM_DATA_MEMORY_DWLEN CDM_CODE_MEMORYn_DWLEN(1)
|
||||
#define PPM_INT_UNIT_DWLEN 0x0100
|
||||
#define PPM_TIMER0_DWLEN 0x0100
|
||||
#define PPM_TASK_IND_REG_DWLEN 0x0100
|
||||
#define PPS_BRK_DWLEN 0x0100
|
||||
#define PPM_TIMER1_DWLEN 0x0100
|
||||
#define SB_RAM0_DWLEN 0x0400
|
||||
#define SB_RAM1_DWLEN 0x0800
|
||||
#define SB_RAM2_DWLEN 0x0A00
|
||||
#define SB_RAM3_DWLEN 0x0400
|
||||
#define QSB_CONF_REG_DWLEN 0x0100
|
||||
|
||||
/*
|
||||
* PP32 to FPI Address Mapping
|
||||
*/
|
||||
#define SB_BUFFER(__sb_addr) ((volatile unsigned int *)((((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x23FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) : \
|
||||
(((__sb_addr) >= 0x2400) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2400) : \
|
||||
(((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x2C00) : \
|
||||
(((__sb_addr) >= 0x3600) && ((__sb_addr) <= 0x39FF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3600) : \
|
||||
0))
|
||||
|
||||
/*
|
||||
* PP32 Debug Control Register
|
||||
*/
|
||||
#define PP32_DBG_CTRL PP32_DEBUG_REG_ADDR(0, 0x0000)
|
||||
|
||||
#define DBG_CTRL_START_SET(value) ((value) ? (1 << 0) : 0)
|
||||
#define DBG_CTRL_STOP_SET(value) ((value) ? (1 << 1) : 0)
|
||||
#define DBG_CTRL_STEP_SET(value) ((value) ? (1 << 2) : 0)
|
||||
|
||||
#define PP32_HALT_STAT PP32_DEBUG_REG_ADDR(0, 0x0001)
|
||||
|
||||
#define PP32_BRK_SRC PP32_DEBUG_REG_ADDR(0, 0x0002)
|
||||
|
||||
#define PP32_DBG_PC_MIN(i) PP32_DEBUG_REG_ADDR(0, 0x0010 + (i))
|
||||
#define PP32_DBG_PC_MAX(i) PP32_DEBUG_REG_ADDR(0, 0x0014 + (i))
|
||||
#define PP32_DBG_DATA_MIN(i) PP32_DEBUG_REG_ADDR(0, 0x0018 + (i))
|
||||
#define PP32_DBG_DATA_MAX(i) PP32_DEBUG_REG_ADDR(0, 0x001A + (i))
|
||||
#define PP32_DBG_DATA_VAL(i) PP32_DEBUG_REG_ADDR(0, 0x001C + (i))
|
||||
|
||||
#define PP32_DBG_CUR_PC PP32_DEBUG_REG_ADDR(0, 0x0080)
|
||||
|
||||
#define PP32_DBG_TASK_NO PP32_DEBUG_REG_ADDR(0, 0x0081)
|
||||
|
||||
/*
|
||||
* EMA Registers
|
||||
*/
|
||||
#define EMA_CMDCFG PPE_REG_ADDR(0x0A00)
|
||||
#define EMA_DATACFG PPE_REG_ADDR(0x0A01)
|
||||
#define EMA_CMDCNT PPE_REG_ADDR(0x0A02)
|
||||
#define EMA_DATACNT PPE_REG_ADDR(0x0A03)
|
||||
#define EMA_ISR PPE_REG_ADDR(0x0A04)
|
||||
#define EMA_IER PPE_REG_ADDR(0x0A05)
|
||||
#define EMA_CFG PPE_REG_ADDR(0x0A06)
|
||||
#define EMA_SUBID PPE_REG_ADDR(0x0A07)
|
||||
|
||||
#define EMA_ALIGNMENT 4
|
||||
|
||||
/*
|
||||
* Mailbox IGU1 Interrupt
|
||||
*/
|
||||
#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
|
||||
|
||||
|
||||
|
||||
#endif // IFXMIPS_ATM_PPE_DANUBE_H
|
||||
2998
package/ifxmips-dsl-api/src/ifxmips_mei.c
Normal file
2998
package/ifxmips-dsl-api/src/ifxmips_mei.c
Normal file
File diff suppressed because it is too large
Load Diff
700
package/ifxmips-dsl-api/src/ifxmips_mei_interface.h
Normal file
700
package/ifxmips-dsl-api/src/ifxmips_mei_interface.h
Normal file
@@ -0,0 +1,700 @@
|
||||
/******************************************************************************
|
||||
|
||||
Copyright (c) 2009
|
||||
Infineon Technologies AG
|
||||
Am Campeon 1-12; 81726 Munich, Germany
|
||||
|
||||
For licensing information, see the file 'LICENSE' in the root folder of
|
||||
this software module.
|
||||
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef IFXMIPS_MEI_H
|
||||
#define IFXMIPS_MEI_H
|
||||
|
||||
#define CONFIG_DANUBE 1
|
||||
|
||||
#if !defined(CONFIG_DANUBE) && !defined(CONFIG_AMAZON_SE) && !defined(CONFIG_AR9) && !defined(CONFIG_VR9)
|
||||
#error Platform undefined!!!
|
||||
#endif
|
||||
|
||||
#ifdef IFX_MEI_BSP
|
||||
/** This is the character datatype. */
|
||||
typedef char DSL_char_t;
|
||||
/** This is the unsigned 8-bit datatype. */
|
||||
typedef unsigned char DSL_uint8_t;
|
||||
/** This is the signed 8-bit datatype. */
|
||||
typedef signed char DSL_int8_t;
|
||||
/** This is the unsigned 16-bit datatype. */
|
||||
typedef unsigned short DSL_uint16_t;
|
||||
/** This is the signed 16-bit datatype. */
|
||||
typedef signed short DSL_int16_t;
|
||||
/** This is the unsigned 32-bit datatype. */
|
||||
typedef unsigned long DSL_uint32_t;
|
||||
/** This is the signed 32-bit datatype. */
|
||||
typedef signed long DSL_int32_t;
|
||||
/** This is the float datatype. */
|
||||
typedef float DSL_float_t;
|
||||
/** This is the void datatype. */
|
||||
typedef void DSL_void_t;
|
||||
/** integer type, width is depending on processor arch */
|
||||
typedef int DSL_int_t;
|
||||
/** unsigned integer type, width is depending on processor arch */
|
||||
typedef unsigned int DSL_uint_t;
|
||||
typedef struct file DSL_DRV_file_t;
|
||||
typedef struct inode DSL_DRV_inode_t;
|
||||
|
||||
/**
|
||||
* Defines all possible CMV groups
|
||||
* */
|
||||
typedef enum {
|
||||
DSL_CMV_GROUP_CNTL = 1,
|
||||
DSL_CMV_GROUP_STAT = 2,
|
||||
DSL_CMV_GROUP_INFO = 3,
|
||||
DSL_CMV_GROUP_TEST = 4,
|
||||
DSL_CMV_GROUP_OPTN = 5,
|
||||
DSL_CMV_GROUP_RATE = 6,
|
||||
DSL_CMV_GROUP_PLAM = 7,
|
||||
DSL_CMV_GROUP_CNFG = 8
|
||||
} DSL_CmvGroup_t;
|
||||
/**
|
||||
* Defines all opcode types
|
||||
* */
|
||||
typedef enum {
|
||||
H2D_CMV_READ = 0x00,
|
||||
H2D_CMV_WRITE = 0x04,
|
||||
H2D_CMV_INDICATE_REPLY = 0x10,
|
||||
H2D_ERROR_OPCODE_UNKNOWN =0x20,
|
||||
H2D_ERROR_CMV_UNKNOWN =0x30,
|
||||
|
||||
D2H_CMV_READ_REPLY =0x01,
|
||||
D2H_CMV_WRITE_REPLY = 0x05,
|
||||
D2H_CMV_INDICATE = 0x11,
|
||||
D2H_ERROR_OPCODE_UNKNOWN = 0x21,
|
||||
D2H_ERROR_CMV_UNKNOWN = 0x31,
|
||||
D2H_ERROR_CMV_READ_NOT_AVAILABLE = 0x41,
|
||||
D2H_ERROR_CMV_WRITE_ONLY = 0x51,
|
||||
D2H_ERROR_CMV_READ_ONLY = 0x61,
|
||||
|
||||
H2D_DEBUG_READ_DM = 0x02,
|
||||
H2D_DEBUG_READ_PM = 0x06,
|
||||
H2D_DEBUG_WRITE_DM = 0x0a,
|
||||
H2D_DEBUG_WRITE_PM = 0x0e,
|
||||
|
||||
D2H_DEBUG_READ_DM_REPLY = 0x03,
|
||||
D2H_DEBUG_READ_FM_REPLY = 0x07,
|
||||
D2H_DEBUG_WRITE_DM_REPLY = 0x0b,
|
||||
D2H_DEBUG_WRITE_FM_REPLY = 0x0f,
|
||||
D2H_ERROR_ADDR_UNKNOWN = 0x33,
|
||||
|
||||
D2H_AUTONOMOUS_MODEM_READY_MSG = 0xf1
|
||||
} DSL_CmvOpcode_t;
|
||||
|
||||
/* mutex macros */
|
||||
#define MEI_MUTEX_INIT(id,flag) \
|
||||
sema_init(&id,flag)
|
||||
#define MEI_MUTEX_LOCK(id) \
|
||||
down_interruptible(&id)
|
||||
#define MEI_MUTEX_UNLOCK(id) \
|
||||
up(&id)
|
||||
#define MEI_WAIT(ms) \
|
||||
{\
|
||||
set_current_state(TASK_INTERRUPTIBLE);\
|
||||
schedule_timeout(ms);\
|
||||
}
|
||||
#define MEI_INIT_WAKELIST(name,queue) \
|
||||
init_waitqueue_head(&queue)
|
||||
|
||||
/* wait for an event, timeout is measured in ms */
|
||||
#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\
|
||||
interruptible_sleep_on_timeout(&ev,timeout * HZ / 1000)
|
||||
#define MEI_WAKEUP_EVENT(ev)\
|
||||
wake_up_interruptible(&ev)
|
||||
#endif /* IFX_MEI_BSP */
|
||||
|
||||
/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/
|
||||
#define ME_DX_DATA (0x0000)
|
||||
#define ME_VERSION (0x0004)
|
||||
#define ME_ARC_GP_STAT (0x0008)
|
||||
#define ME_DX_STAT (0x000C)
|
||||
#define ME_DX_AD (0x0010)
|
||||
#define ME_DX_MWS (0x0014)
|
||||
#define ME_ME2ARC_INT (0x0018)
|
||||
#define ME_ARC2ME_STAT (0x001C)
|
||||
#define ME_ARC2ME_MASK (0x0020)
|
||||
#define ME_DBG_WR_AD (0x0024)
|
||||
#define ME_DBG_RD_AD (0x0028)
|
||||
#define ME_DBG_DATA (0x002C)
|
||||
#define ME_DBG_DECODE (0x0030)
|
||||
#define ME_CONFIG (0x0034)
|
||||
#define ME_RST_CTRL (0x0038)
|
||||
#define ME_DBG_MASTER (0x003C)
|
||||
#define ME_CLK_CTRL (0x0040)
|
||||
#define ME_BIST_CTRL (0x0044)
|
||||
#define ME_BIST_STAT (0x0048)
|
||||
#define ME_XDATA_BASE_SH (0x004c)
|
||||
#define ME_XDATA_BASE (0x0050)
|
||||
#define ME_XMEM_BAR_BASE (0x0054)
|
||||
#define ME_XMEM_BAR0 (0x0054)
|
||||
#define ME_XMEM_BAR1 (0x0058)
|
||||
#define ME_XMEM_BAR2 (0x005C)
|
||||
#define ME_XMEM_BAR3 (0x0060)
|
||||
#define ME_XMEM_BAR4 (0x0064)
|
||||
#define ME_XMEM_BAR5 (0x0068)
|
||||
#define ME_XMEM_BAR6 (0x006C)
|
||||
#define ME_XMEM_BAR7 (0x0070)
|
||||
#define ME_XMEM_BAR8 (0x0074)
|
||||
#define ME_XMEM_BAR9 (0x0078)
|
||||
#define ME_XMEM_BAR10 (0x007C)
|
||||
#define ME_XMEM_BAR11 (0x0080)
|
||||
#define ME_XMEM_BAR12 (0x0084)
|
||||
#define ME_XMEM_BAR13 (0x0088)
|
||||
#define ME_XMEM_BAR14 (0x008C)
|
||||
#define ME_XMEM_BAR15 (0x0090)
|
||||
#define ME_XMEM_BAR16 (0x0094)
|
||||
|
||||
#define WHILE_DELAY 20000
|
||||
/*
|
||||
** Define where in ME Processor's memory map the Stratify chip lives
|
||||
*/
|
||||
|
||||
#define MAXSWAPSIZE (8 * 1024) //8k *(32bits)
|
||||
|
||||
// Mailboxes
|
||||
#define MSG_LENGTH 16 // x16 bits
|
||||
#define YES_REPLY 1
|
||||
#define NO_REPLY 0
|
||||
|
||||
#define CMV_TIMEOUT 1000 //jiffies
|
||||
|
||||
// Block size per BAR
|
||||
#define SDRAM_SEGMENT_SIZE (64*1024)
|
||||
// Number of Bar registers
|
||||
#define MAX_BAR_REGISTERS (17)
|
||||
|
||||
#define XDATA_REGISTER (15)
|
||||
|
||||
// ARC register addresss
|
||||
#define ARC_STATUS 0x0
|
||||
#define ARC_LP_START 0x2
|
||||
#define ARC_LP_END 0x3
|
||||
#define ARC_DEBUG 0x5
|
||||
#define ARC_INT_MASK 0x10A
|
||||
|
||||
#define IRAM0_BASE (0x00000)
|
||||
#define IRAM1_BASE (0x04000)
|
||||
#if defined(CONFIG_DANUBE)
|
||||
#define BRAM_BASE (0x0A000)
|
||||
#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
|
||||
#define BRAM_BASE (0x08000)
|
||||
#endif
|
||||
#define XRAM_BASE (0x18000)
|
||||
#define YRAM_BASE (0x1A000)
|
||||
#define EXT_MEM_BASE (0x80000)
|
||||
#define ARC_GPIO_CTRL (0xC030)
|
||||
#define ARC_GPIO_DATA (0xC034)
|
||||
|
||||
#define IRAM0_SIZE (16*1024)
|
||||
#define IRAM1_SIZE (16*1024)
|
||||
#define BRAM_SIZE (12*1024)
|
||||
#define XRAM_SIZE (8*1024)
|
||||
#define YRAM_SIZE (8*1024)
|
||||
#define EXT_MEM_SIZE (1536*1024)
|
||||
|
||||
#define ADSL_BASE (0x20000)
|
||||
#define CRI_BASE (ADSL_BASE + 0x11F00)
|
||||
#define CRI_CCR0 (CRI_BASE + 0x00)
|
||||
#define CRI_RST (CRI_BASE + 0x04*4)
|
||||
#define ADSL_DILV_BASE (ADSL_BASE+0x20000)
|
||||
|
||||
//
|
||||
#define IRAM0_ADDR_BIT_MASK 0xFFF
|
||||
#define IRAM1_ADDR_BIT_MASK 0xFFF
|
||||
#define BRAM_ADDR_BIT_MASK 0xFFF
|
||||
#define RX_DILV_ADDR_BIT_MASK 0x1FFF
|
||||
|
||||
/*** Bit definitions ***/
|
||||
#define ARC_AUX_HALT (1 << 25)
|
||||
#define ARC_DEBUG_HALT (1 << 1)
|
||||
#define FALSE 0
|
||||
#define TRUE 1
|
||||
#define BIT0 (1<<0)
|
||||
#define BIT1 (1<<1)
|
||||
#define BIT2 (1<<2)
|
||||
#define BIT3 (1<<3)
|
||||
#define BIT4 (1<<4)
|
||||
#define BIT5 (1<<5)
|
||||
#define BIT6 (1<<6)
|
||||
#define BIT7 (1<<7)
|
||||
#define BIT8 (1<<8)
|
||||
#define BIT9 (1<<9)
|
||||
#define BIT10 (1<<10)
|
||||
#define BIT11 (1<<11)
|
||||
#define BIT12 (1<<12)
|
||||
#define BIT13 (1<<13)
|
||||
#define BIT14 (1<<14)
|
||||
#define BIT15 (1<<15)
|
||||
#define BIT16 (1<<16)
|
||||
#define BIT17 (1<<17)
|
||||
#define BIT18 (1<<18)
|
||||
#define BIT19 (1<<19)
|
||||
#define BIT20 (1<<20)
|
||||
#define BIT21 (1<<21)
|
||||
#define BIT22 (1<<22)
|
||||
#define BIT23 (1<<23)
|
||||
#define BIT24 (1<<24)
|
||||
#define BIT25 (1<<25)
|
||||
#define BIT26 (1<<26)
|
||||
#define BIT27 (1<<27)
|
||||
#define BIT28 (1<<28)
|
||||
#define BIT29 (1<<29)
|
||||
#define BIT30 (1<<30)
|
||||
#define BIT31 (1<<31)
|
||||
|
||||
// CRI_CCR0 Register definitions
|
||||
#define CLK_2M_MODE_ENABLE BIT6
|
||||
#define ACL_CLK_MODE_ENABLE BIT4
|
||||
#define FDF_CLK_MODE_ENABLE BIT2
|
||||
#define STM_CLK_MODE_ENABLE BIT0
|
||||
|
||||
// CRI_RST Register definitions
|
||||
#define FDF_SRST BIT3
|
||||
#define MTE_SRST BIT2
|
||||
#define FCI_SRST BIT1
|
||||
#define AAI_SRST BIT0
|
||||
|
||||
// MEI_TO_ARC_INTERRUPT Register definitions
|
||||
#define MEI_TO_ARC_INT1 BIT3
|
||||
#define MEI_TO_ARC_INT0 BIT2
|
||||
#define MEI_TO_ARC_CS_DONE BIT1 //need to check
|
||||
#define MEI_TO_ARC_MSGAV BIT0
|
||||
|
||||
// ARC_TO_MEI_INTERRUPT Register definitions
|
||||
#define ARC_TO_MEI_INT1 BIT8
|
||||
#define ARC_TO_MEI_INT0 BIT7
|
||||
#define ARC_TO_MEI_CS_REQ BIT6
|
||||
#define ARC_TO_MEI_DBG_DONE BIT5
|
||||
#define ARC_TO_MEI_MSGACK BIT4
|
||||
#define ARC_TO_MEI_NO_ACCESS BIT3
|
||||
#define ARC_TO_MEI_CHECK_AAITX BIT2
|
||||
#define ARC_TO_MEI_CHECK_AAIRX BIT1
|
||||
#define ARC_TO_MEI_MSGAV BIT0
|
||||
|
||||
// ARC_TO_MEI_INTERRUPT_MASK Register definitions
|
||||
#define GP_INT1_EN BIT8
|
||||
#define GP_INT0_EN BIT7
|
||||
#define CS_REQ_EN BIT6
|
||||
#define DBG_DONE_EN BIT5
|
||||
#define MSGACK_EN BIT4
|
||||
#define NO_ACC_EN BIT3
|
||||
#define AAITX_EN BIT2
|
||||
#define AAIRX_EN BIT1
|
||||
#define MSGAV_EN BIT0
|
||||
|
||||
#define MEI_SOFT_RESET BIT0
|
||||
|
||||
#define HOST_MSTR BIT0
|
||||
|
||||
#define JTAG_MASTER_MODE 0x0
|
||||
#define MEI_MASTER_MODE HOST_MSTR
|
||||
|
||||
// MEI_DEBUG_DECODE Register definitions
|
||||
#define MEI_DEBUG_DEC_MASK (0x3)
|
||||
#define MEI_DEBUG_DEC_AUX_MASK (0x0)
|
||||
#define ME_DBG_DECODE_DMP1_MASK (0x1)
|
||||
#define MEI_DEBUG_DEC_DMP2_MASK (0x2)
|
||||
#define MEI_DEBUG_DEC_CORE_MASK (0x3)
|
||||
|
||||
#define AUX_STATUS (0x0)
|
||||
#define AUX_ARC_GPIO_CTRL (0x10C)
|
||||
#define AUX_ARC_GPIO_DATA (0x10D)
|
||||
// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
|
||||
// page swap requests.
|
||||
#if defined(CONFIG_DANUBE)
|
||||
#define OMBOX_BASE 0xDF80
|
||||
#define ARC_TO_MEI_MAILBOX 0xDFA0
|
||||
#define IMBOX_BASE 0xDFC0
|
||||
#define MEI_TO_ARC_MAILBOX 0xDFD0
|
||||
#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
|
||||
#define OMBOX_BASE 0xAF80
|
||||
#define ARC_TO_MEI_MAILBOX 0xAFA0
|
||||
#define IMBOX_BASE 0xAFC0
|
||||
#define MEI_TO_ARC_MAILBOX 0xAFD0
|
||||
#endif
|
||||
|
||||
#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C)
|
||||
#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C)
|
||||
#define OMBOX1 (OMBOX_BASE+0x4)
|
||||
|
||||
// Codeswap request messages are indicated by setting BIT31
|
||||
#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
|
||||
|
||||
// Clear Eoc messages received are indicated by setting BIT17
|
||||
#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000)
|
||||
#define OMB_REBOOT_INTERRUPT_CODE (1 << 18)
|
||||
|
||||
/*
|
||||
** Swap page header
|
||||
*/
|
||||
// Page must be loaded at boot time if size field has BIT31 set
|
||||
#define BOOT_FLAG (BIT31)
|
||||
#define BOOT_FLAG_MASK ~BOOT_FLAG
|
||||
|
||||
#define FREE_RELOAD 1
|
||||
#define FREE_SHOWTIME 2
|
||||
#define FREE_ALL 3
|
||||
|
||||
// marcos
|
||||
#define IFX_MEI_WRITE_REGISTER_L(data,addr) *((volatile u32*)(addr)) = (u32)(data)
|
||||
#define IFX_MEI_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
|
||||
#define SET_BIT(reg, mask) reg |= (mask)
|
||||
#define CLEAR_BIT(reg, mask) reg &= (~mask)
|
||||
#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
|
||||
//#define SET_BITS(reg, mask) SET_BIT(reg, mask)
|
||||
#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
|
||||
|
||||
#define ALIGN_SIZE ( 1L<<10 ) //1K size align
|
||||
#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
|
||||
|
||||
// swap marco
|
||||
#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
|
||||
#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
|
||||
|
||||
|
||||
#ifdef CONFIG_PROC_FS
|
||||
typedef struct reg_entry
|
||||
{
|
||||
int *flag;
|
||||
char name[30]; /* big enough to hold names */
|
||||
char description[100]; /* big enough to hold description */
|
||||
unsigned short low_ino;
|
||||
} reg_entry_t;
|
||||
#endif
|
||||
// Swap page header describes size in 32-bit words, load location, and image offset
|
||||
// for program and/or data segments
|
||||
typedef struct _arc_swp_page_hdr {
|
||||
u32 p_offset; //Offset bytes of progseg from beginning of image
|
||||
u32 p_dest; //Destination addr of progseg on processor
|
||||
u32 p_size; //Size in 32-bitwords of program segment
|
||||
u32 d_offset; //Offset bytes of dataseg from beginning of image
|
||||
u32 d_dest; //Destination addr of dataseg on processor
|
||||
u32 d_size; //Size in 32-bitwords of data segment
|
||||
} ARC_SWP_PAGE_HDR;
|
||||
|
||||
/*
|
||||
** Swap image header
|
||||
*/
|
||||
#define GET_PROG 0 // Flag used for program mem segment
|
||||
#define GET_DATA 1 // Flag used for data mem segment
|
||||
|
||||
// Image header contains size of image, checksum for image, and count of
|
||||
// page headers. Following that are 'count' page headers followed by
|
||||
// the code and/or data segments to be loaded
|
||||
typedef struct _arc_img_hdr {
|
||||
u32 size; // Size of binary image in bytes
|
||||
u32 checksum; // Checksum for image
|
||||
u32 count; // Count of swp pages in image
|
||||
ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
|
||||
} ARC_IMG_HDR;
|
||||
|
||||
typedef struct smmu_mem_info {
|
||||
int type;
|
||||
int boot;
|
||||
unsigned long nCopy;
|
||||
unsigned long size;
|
||||
unsigned char *address;
|
||||
unsigned char *org_address;
|
||||
} smmu_mem_info_t;
|
||||
|
||||
#ifdef __KERNEL__
|
||||
typedef struct ifx_mei_device_private {
|
||||
int modem_ready;
|
||||
int arcmsgav;
|
||||
int cmv_reply;
|
||||
int cmv_waiting;
|
||||
// Mei to ARC CMV count, reply count, ARC Indicator count
|
||||
int modem_ready_cnt;
|
||||
int cmv_count;
|
||||
int reply_count;
|
||||
unsigned long image_size;
|
||||
int nBar;
|
||||
u16 Recent_indicator[MSG_LENGTH];
|
||||
|
||||
u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
|
||||
|
||||
smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];
|
||||
ARC_IMG_HDR *img_hdr;
|
||||
// to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
|
||||
wait_queue_head_t wait_queue_arcmsgav;
|
||||
wait_queue_head_t wait_queue_modemready;
|
||||
struct semaphore mei_cmv_sema;
|
||||
} ifx_mei_device_private_t;
|
||||
#endif
|
||||
typedef struct winhost_message {
|
||||
union {
|
||||
u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
|
||||
u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
|
||||
} msg;
|
||||
} DSL_DEV_WinHost_Message_t;
|
||||
/********************************************************************************************************
|
||||
* DSL CPE API Driver Stack Interface Definitions
|
||||
* *****************************************************************************************************/
|
||||
/** IOCTL codes for bsp driver */
|
||||
#define DSL_IOC_MEI_BSP_MAGIC 's'
|
||||
|
||||
#define DSL_FIO_BSP_DSL_START _IO (DSL_IOC_MEI_BSP_MAGIC, 0)
|
||||
#define DSL_FIO_BSP_RUN _IO (DSL_IOC_MEI_BSP_MAGIC, 1)
|
||||
#define DSL_FIO_BSP_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 2)
|
||||
#define DSL_FIO_BSP_RESET _IO (DSL_IOC_MEI_BSP_MAGIC, 3)
|
||||
#define DSL_FIO_BSP_REBOOT _IO (DSL_IOC_MEI_BSP_MAGIC, 4)
|
||||
#define DSL_FIO_BSP_HALT _IO (DSL_IOC_MEI_BSP_MAGIC, 5)
|
||||
#define DSL_FIO_BSP_BOOTDOWNLOAD _IO (DSL_IOC_MEI_BSP_MAGIC, 6)
|
||||
#define DSL_FIO_BSP_JTAG_ENABLE _IO (DSL_IOC_MEI_BSP_MAGIC, 7)
|
||||
#define DSL_FIO_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 8)
|
||||
#define DSL_FIO_ARC_MUX_TEST _IO (DSL_IOC_MEI_BSP_MAGIC, 9)
|
||||
#define DSL_FIO_BSP_REMOTE _IOW (DSL_IOC_MEI_BSP_MAGIC, 10, u32)
|
||||
#define DSL_FIO_BSP_GET_BASE_ADDRESS _IOR (DSL_IOC_MEI_BSP_MAGIC, 11, u32)
|
||||
#define DSL_FIO_BSP_IS_MODEM_READY _IOR (DSL_IOC_MEI_BSP_MAGIC, 12, u32)
|
||||
#define DSL_FIO_BSP_GET_VERSION _IOR (DSL_IOC_MEI_BSP_MAGIC, 13, DSL_DEV_Version_t)
|
||||
#define DSL_FIO_BSP_CMV_WINHOST _IOWR(DSL_IOC_MEI_BSP_MAGIC, 14, DSL_DEV_WinHost_Message_t)
|
||||
#define DSL_FIO_BSP_CMV_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 15, DSL_DEV_MeiReg_t)
|
||||
#define DSL_FIO_BSP_CMV_WRITE _IOW (DSL_IOC_MEI_BSP_MAGIC, 16, DSL_DEV_MeiReg_t)
|
||||
#define DSL_FIO_BSP_DEBUG_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 17, DSL_DEV_MeiDebug_t)
|
||||
#define DSL_FIO_BSP_DEBUG_WRITE _IOWR(DSL_IOC_MEI_BSP_MAGIC, 18, DSL_DEV_MeiDebug_t)
|
||||
#define DSL_FIO_BSP_GET_CHIP_INFO _IOR (DSL_IOC_MEI_BSP_MAGIC, 19, DSL_DEV_HwVersion_t)
|
||||
|
||||
#define DSL_DEV_MEIDEBUG_BUFFER_SIZES 512
|
||||
|
||||
typedef struct DSL_DEV_MeiDebug
|
||||
{
|
||||
DSL_uint32_t iAddress;
|
||||
DSL_uint32_t iCount;
|
||||
DSL_uint32_t buffer[DSL_DEV_MEIDEBUG_BUFFER_SIZES];
|
||||
} DSL_DEV_MeiDebug_t; /* meidebug */
|
||||
|
||||
/**
|
||||
* Structure is used for debug access only.
|
||||
* Refer to configure option INCLUDE_ADSL_WINHOST_DEBUG */
|
||||
typedef struct struct_meireg
|
||||
{
|
||||
/*
|
||||
* Specifies that address for debug access */
|
||||
unsigned long iAddress;
|
||||
/*
|
||||
* Specifies the pointer to the data that has to be written or returns a
|
||||
* pointer to the data that has been read out*/
|
||||
unsigned long iData;
|
||||
} DSL_DEV_MeiReg_t; /* meireg */
|
||||
|
||||
typedef struct DSL_DEV_Device
|
||||
{
|
||||
DSL_int_t nInUse; /* modem state, update by bsp driver, */
|
||||
DSL_void_t *pPriv;
|
||||
DSL_uint32_t base_address; /* mei base address */
|
||||
DSL_int_t nIrq[2]; /* irq number */
|
||||
#define IFX_DFEIR 0
|
||||
#define IFX_DYING_GASP 1
|
||||
DSL_DEV_MeiDebug_t lop_debugwr; /* dying gasp */
|
||||
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0))
|
||||
struct module *owner;
|
||||
#endif
|
||||
} DSL_DEV_Device_t; /* ifx_adsl_device_t */
|
||||
|
||||
#define DSL_DEV_PRIVATE(dev) ((ifx_mei_device_private_t*)(dev->pPriv))
|
||||
|
||||
typedef struct DSL_DEV_Version /* ifx_adsl_bsp_version */
|
||||
{
|
||||
unsigned long major;
|
||||
unsigned long minor;
|
||||
unsigned long revision;
|
||||
} DSL_DEV_Version_t; /* ifx_adsl_bsp_version_t */
|
||||
|
||||
typedef struct DSL_DEV_ChipInfo
|
||||
{
|
||||
unsigned long major;
|
||||
unsigned long minor;
|
||||
} DSL_DEV_HwVersion_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
DSL_uint8_t dummy;
|
||||
} DSL_DEV_DeviceConfig_t;
|
||||
|
||||
/** error code definitions */
|
||||
typedef enum DSL_DEV_MeiError
|
||||
{
|
||||
DSL_DEV_MEI_ERR_SUCCESS = 0,
|
||||
DSL_DEV_MEI_ERR_FAILURE = -1,
|
||||
DSL_DEV_MEI_ERR_MAILBOX_FULL = -2,
|
||||
DSL_DEV_MEI_ERR_MAILBOX_EMPTY = -3,
|
||||
DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT = -4
|
||||
} DSL_DEV_MeiError_t; /* MEI_ERROR */
|
||||
|
||||
typedef enum {
|
||||
DSL_BSP_MEMORY_READ=0,
|
||||
DSL_BSP_MEMORY_WRITE,
|
||||
} DSL_BSP_MemoryAccessType_t; /* ifx_adsl_memory_access_type_t */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DSL_LED_LINK_ID=0,
|
||||
DSL_LED_DATA_ID
|
||||
} DSL_DEV_LedId_t; /* ifx_adsl_led_id_t */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DSL_LED_LINK_TYPE=0,
|
||||
DSL_LED_DATA_TYPE
|
||||
} DSL_DEV_LedType_t; /* ifx_adsl_led_type_t */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DSL_LED_HD_CPU=0,
|
||||
DSL_LED_HD_FW
|
||||
} DSL_DEV_LedHandler_t; /* ifx_adsl_led_handler_t */
|
||||
|
||||
typedef enum {
|
||||
DSL_LED_ON=0,
|
||||
DSL_LED_OFF,
|
||||
DSL_LED_FLASH,
|
||||
} DSL_DEV_LedMode_t; /* ifx_adsl_led_mode_t */
|
||||
|
||||
typedef enum {
|
||||
DSL_CPU_HALT=0,
|
||||
DSL_CPU_RUN,
|
||||
DSL_CPU_RESET,
|
||||
} DSL_DEV_CpuMode_t; /* ifx_adsl_cpu_mode_t */
|
||||
|
||||
#if 0
|
||||
typedef enum {
|
||||
DSL_BSP_EVENT_DYING_GASP = 0,
|
||||
DSL_BSP_EVENT_CEOC_IRQ,
|
||||
} DSL_BSP_Event_id_t; /* ifx_adsl_event_id_t */
|
||||
|
||||
typedef union DSL_BSP_CB_Param
|
||||
{
|
||||
DSL_uint32_t nIrqMessage;
|
||||
} DSL_BSP_CB_Param_t; /* ifx_adsl_cbparam_t */
|
||||
|
||||
typedef struct DSL_BSP_CB_Event
|
||||
{
|
||||
DSL_BSP_Event_id_t nID;
|
||||
DSL_DEV_Device_t *pDev;
|
||||
DSL_BSP_CB_Param_t *pParam;
|
||||
} DSL_BSP_CB_Event_t; /* ifx_adsl_cb_event_t */
|
||||
#endif
|
||||
|
||||
/* external functions (from the BSP Driver) */
|
||||
extern DSL_DEV_Device_t* DSL_BSP_DriverHandleGet(int, int);
|
||||
extern DSL_int_t DSL_BSP_DriverHandleDelete(DSL_DEV_Device_t *);
|
||||
extern DSL_DEV_MeiError_t DSL_BSP_FWDownload(DSL_DEV_Device_t *, const DSL_char_t *, DSL_uint32_t, DSL_int32_t *, DSL_int32_t *);
|
||||
extern int DSL_BSP_KernelIoctls(DSL_DEV_Device_t *, unsigned int, unsigned long);
|
||||
extern DSL_DEV_MeiError_t DSL_BSP_SendCMV(DSL_DEV_Device_t *, DSL_uint16_t *, DSL_int_t, DSL_uint16_t *);
|
||||
extern DSL_DEV_MeiError_t DSL_BSP_AdslLedInit(DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);
|
||||
extern DSL_DEV_MeiError_t DSL_BSP_Showtime(DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);
|
||||
extern int DSL_BSP_ATMLedCBRegister( int (*ifx_adsl_ledcallback)(void));
|
||||
extern DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess(DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t *, DSL_uint32_t);
|
||||
extern volatile DSL_DEV_Device_t *adsl_dev;
|
||||
|
||||
/**
|
||||
* Dummy structure by now to show mechanism of extended data that will be
|
||||
* provided within event callback itself.
|
||||
* */
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* Dummy value */
|
||||
DSL_uint32_t nDummy1;
|
||||
} DSL_BSP_CB_Event1DataDummy_t;
|
||||
|
||||
/**
|
||||
* Dummy structure by now to show mechanism of extended data that will be
|
||||
* provided within event callback itself.
|
||||
* */
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* Dummy value */
|
||||
DSL_uint32_t nDummy2;
|
||||
} DSL_BSP_CB_Event2DataDummy_t;
|
||||
|
||||
/**
|
||||
* encapsulate all data structures that are necessary for status event
|
||||
* callbacks.
|
||||
* */
|
||||
typedef union
|
||||
{
|
||||
DSL_BSP_CB_Event1DataDummy_t dataEvent1;
|
||||
DSL_BSP_CB_Event2DataDummy_t dataEvent2;
|
||||
} DSL_BSP_CB_DATA_Union_t;
|
||||
|
||||
|
||||
typedef enum
|
||||
{
|
||||
/**
|
||||
* Informs the upper layer driver (DSL CPE API) about a reboot request from the
|
||||
* firmware.
|
||||
* \note This event does NOT include any additional data.
|
||||
* More detailed information upon reboot reason has to be requested from
|
||||
* upper layer software via CMV (INFO 109) if necessary. */
|
||||
DSL_BSP_CB_FIRST = 0,
|
||||
DSL_BSP_CB_DYING_GASP,
|
||||
DSL_BSP_CB_CEOC_IRQ,
|
||||
DSL_BSP_CB_FIRMWARE_REBOOT,
|
||||
/**
|
||||
* Delimiter only */
|
||||
DSL_BSP_CB_LAST
|
||||
} DSL_BSP_CB_Type_t;
|
||||
|
||||
/**
|
||||
* Specifies the common event type that has to be used for registering and
|
||||
* signalling of interrupts/autonomous status events from MEI BSP Driver.
|
||||
*
|
||||
* \param pDev
|
||||
* Context pointer from MEI BSP Driver.
|
||||
*
|
||||
* \param IFX_ADSL_BSP_CallbackType_t
|
||||
* Specifies the event callback type (reason of callback). Regrading to the
|
||||
* setting of this value the data which is included in the following union
|
||||
* might have different meanings.
|
||||
* Please refer to the description of the union to get information about the
|
||||
* meaning of the included data.
|
||||
*
|
||||
* \param pData
|
||||
* Data according to \ref DSL_BSP_CB_DATA_Union_t.
|
||||
* If this pointer is NULL there is no additional data available.
|
||||
*
|
||||
* \return depending on event
|
||||
*/
|
||||
typedef int (*DSL_BSP_EventCallback_t)
|
||||
(
|
||||
DSL_DEV_Device_t *pDev,
|
||||
DSL_BSP_CB_Type_t nCallbackType,
|
||||
DSL_BSP_CB_DATA_Union_t *pData
|
||||
);
|
||||
|
||||
typedef struct {
|
||||
DSL_BSP_EventCallback_t function;
|
||||
DSL_BSP_CB_Type_t event;
|
||||
DSL_BSP_CB_DATA_Union_t *pData;
|
||||
} DSL_BSP_EventCallBack_t;
|
||||
|
||||
extern int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *);
|
||||
extern int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *);
|
||||
|
||||
/** Modem states */
|
||||
#define DSL_DEV_STAT_InitState 0x0000
|
||||
#define DSL_DEV_STAT_ReadyState 0x0001
|
||||
#define DSL_DEV_STAT_FailState 0x0002
|
||||
#define DSL_DEV_STAT_IdleState 0x0003
|
||||
#define DSL_DEV_STAT_QuietState 0x0004
|
||||
#define DSL_DEV_STAT_GhsState 0x0005
|
||||
#define DSL_DEV_STAT_FullInitState 0x0006
|
||||
#define DSL_DEV_STAT_ShowTimeState 0x0007
|
||||
#define DSL_DEV_STAT_FastRetrainState 0x0008
|
||||
#define DSL_DEV_STAT_LoopDiagMode 0x0009
|
||||
#define DSL_DEV_STAT_ShortInit 0x000A /* Bis short initialization */
|
||||
|
||||
#define DSL_DEV_STAT_CODESWAP_COMPLETE 0x0002
|
||||
|
||||
#endif //IFXMIPS_MEI_H
|
||||
Reference in New Issue
Block a user