| @@ -49,11 +49,11 @@ Signed-off-by: Andy Gross <andy.gross@linaro.org> | |||||||
| -	int idx, shift, w_size; | -	int idx, shift, w_size; | ||||||
| - | - | ||||||
| -	w_size = controller->w_size; | -	w_size = controller->w_size; | ||||||
|  | - | ||||||
|  | -	while (controller->rx_bytes < xfer->len) { | ||||||
| +	int i, shift, num_bytes; | +	int i, shift, num_bytes; | ||||||
| +	u32 word; | +	u32 word; | ||||||
|   |   | ||||||
| -	while (controller->rx_bytes < xfer->len) { |  | ||||||
| - |  | ||||||
| -		state = readl_relaxed(controller->base + QUP_OPERATIONAL); | -		state = readl_relaxed(controller->base + QUP_OPERATIONAL); | ||||||
| -		if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY)) | -		if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY)) | ||||||
| -			break; | -			break; | ||||||
| @@ -95,16 +95,20 @@ Signed-off-by: Andy Gross <andy.gross@linaro.org> | |||||||
| -	int idx, w_size; | -	int idx, w_size; | ||||||
| +	u32 remainder, words_per_block, num_words; | +	u32 remainder, words_per_block, num_words; | ||||||
| +	bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; | +	bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; | ||||||
| + |   | ||||||
|  | -	w_size = controller->w_size; | ||||||
| +	remainder = DIV_ROUND_UP(xfer->len - controller->rx_bytes, | +	remainder = DIV_ROUND_UP(xfer->len - controller->rx_bytes, | ||||||
| +				 controller->w_size); | +				 controller->w_size); | ||||||
| +	words_per_block = controller->in_blk_sz >> 2; | +	words_per_block = controller->in_blk_sz >> 2; | ||||||
| + |   | ||||||
|  | -	while (controller->tx_bytes < xfer->len) { | ||||||
| +	do { | +	do { | ||||||
| +		/* ACK by clearing service flag */ | +		/* ACK by clearing service flag */ | ||||||
| +		writel_relaxed(QUP_OP_IN_SERVICE_FLAG, | +		writel_relaxed(QUP_OP_IN_SERVICE_FLAG, | ||||||
| +			       controller->base + QUP_OPERATIONAL); | +			       controller->base + QUP_OPERATIONAL); | ||||||
| + |   | ||||||
|  | -		state = readl_relaxed(controller->base + QUP_OPERATIONAL); | ||||||
|  | -		if (state & QUP_OP_OUT_FIFO_FULL) | ||||||
| +		if (is_block_mode) { | +		if (is_block_mode) { | ||||||
| +			num_words = (remainder > words_per_block) ? | +			num_words = (remainder > words_per_block) ? | ||||||
| +					words_per_block : remainder; | +					words_per_block : remainder; | ||||||
| @@ -112,19 +116,15 @@ Signed-off-by: Andy Gross <andy.gross@linaro.org> | |||||||
| +			if (!spi_qup_is_flag_set(controller, | +			if (!spi_qup_is_flag_set(controller, | ||||||
| +						 QUP_OP_IN_FIFO_NOT_EMPTY)) | +						 QUP_OP_IN_FIFO_NOT_EMPTY)) | ||||||
| +				break; | +				break; | ||||||
|   | + | ||||||
| -	w_size = controller->w_size; |  | ||||||
| +			num_words = 1; | +			num_words = 1; | ||||||
| +		} | +		} | ||||||
| + | + | ||||||
| +		/* read up to the maximum transfer size available */ | +		/* read up to the maximum transfer size available */ | ||||||
| +		spi_qup_read_from_fifo(controller, xfer, num_words); | +		spi_qup_read_from_fifo(controller, xfer, num_words); | ||||||
|   | + | ||||||
| -	while (controller->tx_bytes < xfer->len) { |  | ||||||
| +		remainder -= num_words; | +		remainder -= num_words; | ||||||
|   | + | ||||||
| -		state = readl_relaxed(controller->base + QUP_OPERATIONAL); |  | ||||||
| -		if (state & QUP_OP_OUT_FIFO_FULL) |  | ||||||
| +		/* if block mode, check to see if next block is available */ | +		/* if block mode, check to see if next block is available */ | ||||||
| +		if (is_block_mode && !spi_qup_is_flag_set(controller, | +		if (is_block_mode && !spi_qup_is_flag_set(controller, | ||||||
| +					QUP_OP_IN_BLOCK_READ_REQ)) | +					QUP_OP_IN_BLOCK_READ_REQ)) | ||||||
|   | |||||||
| @@ -67,10 +67,14 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> | |||||||
| -		/* must be zero for BLOCK and BAM */ | -		/* must be zero for BLOCK and BAM */ | ||||||
| -		writel_relaxed(0, controller->base + QUP_MX_READ_CNT); | -		writel_relaxed(0, controller->base + QUP_MX_READ_CNT); | ||||||
| -		writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); | -		writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); | ||||||
| - | +	else | ||||||
|  | +		controller->mode = QUP_IO_M_MODE_BLOCK; | ||||||
|  |   | ||||||
| -		if (!controller->qup_v1) { | -		if (!controller->qup_v1) { | ||||||
| -			void __iomem *input_cnt; | -			void __iomem *input_cnt; | ||||||
| - | +	return 0; | ||||||
|  | +} | ||||||
|  |   | ||||||
| -			input_cnt = controller->base + QUP_MX_INPUT_CNT; | -			input_cnt = controller->base + QUP_MX_INPUT_CNT; | ||||||
| -			/* | -			/* | ||||||
| -			 * for DMA transfers, both QUP_MX_INPUT_CNT and | -			 * for DMA transfers, both QUP_MX_INPUT_CNT and | ||||||
| @@ -82,19 +86,13 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> | |||||||
| -				writel_relaxed(0, input_cnt); | -				writel_relaxed(0, input_cnt); | ||||||
| -			else | -			else | ||||||
| -				writel_relaxed(n_words, input_cnt); | -				writel_relaxed(n_words, input_cnt); | ||||||
| +	else |  | ||||||
| +		controller->mode = QUP_IO_M_MODE_BLOCK; |  | ||||||
| + |  | ||||||
| +	return 0; |  | ||||||
| +} |  | ||||||
|   |  | ||||||
| +/* prep qup for another spi transaction of specific type */ | +/* prep qup for another spi transaction of specific type */ | ||||||
| +static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) | +static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) | ||||||
| +{ | +{ | ||||||
| +	struct spi_qup *controller = spi_master_get_devdata(spi->master); | +	struct spi_qup *controller = spi_master_get_devdata(spi->master); | ||||||
| +	u32 config, iomode, control; | +	u32 config, iomode, control; | ||||||
| +	unsigned long flags; | +	unsigned long flags; | ||||||
| + |   | ||||||
| +	reinit_completion(&controller->done); | +	reinit_completion(&controller->done); | ||||||
| +	reinit_completion(&controller->dma_tx_done); | +	reinit_completion(&controller->dma_tx_done); | ||||||
| + | + | ||||||
|   | |||||||
| @@ -173,37 +173,37 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> | |||||||
| +			qup->n_words = SPI_MAX_XFER; | +			qup->n_words = SPI_MAX_XFER; | ||||||
| +		else | +		else | ||||||
| +			qup->n_words = n_words % SPI_MAX_XFER; | +			qup->n_words = n_words % SPI_MAX_XFER; | ||||||
| + |  | ||||||
| +		if (qup->tx_buf && offset) |  | ||||||
| +			qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER; |  | ||||||
| + |  | ||||||
| +		if (qup->rx_buf && offset) |  | ||||||
| +			qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER; |  | ||||||
| + |  | ||||||
| +		/* if the transaction is small enough, we need |  | ||||||
| +		 * to fallback to FIFO mode */ |  | ||||||
| +		if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32))) |  | ||||||
| +			qup->mode = QUP_IO_M_MODE_FIFO; |  | ||||||
|   |   | ||||||
| -	if (qup->mode == QUP_IO_M_MODE_FIFO) | -	if (qup->mode == QUP_IO_M_MODE_FIFO) | ||||||
| -		spi_qup_write(qup, xfer); | -		spi_qup_write(qup, xfer); | ||||||
| +		ret = spi_qup_io_config(spi, xfer); | +		if (qup->tx_buf && offset) | ||||||
| +		if (ret) | +			qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER; | ||||||
| +			return ret; |  | ||||||
|   |   | ||||||
| -	ret = spi_qup_set_state(qup, QUP_STATE_RUN); | -	ret = spi_qup_set_state(qup, QUP_STATE_RUN); | ||||||
| -	if (ret) { | -	if (ret) { | ||||||
| -		dev_warn(qup->dev, "cannot set RUN state\n"); | -		dev_warn(qup->dev, "cannot set RUN state\n"); | ||||||
| -		return ret; | -		return ret; | ||||||
| -	} | -	} | ||||||
|  | +		if (qup->rx_buf && offset) | ||||||
|  | +			qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER; | ||||||
|  |   | ||||||
|  | -	if (!wait_for_completion_timeout(&qup->done, timeout)) | ||||||
|  | -		return -ETIMEDOUT; | ||||||
|  | +		/* if the transaction is small enough, we need | ||||||
|  | +		 * to fallback to FIFO mode */ | ||||||
|  | +		if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32))) | ||||||
|  | +			qup->mode = QUP_IO_M_MODE_FIFO; | ||||||
|  | + | ||||||
|  | +		ret = spi_qup_io_config(spi, xfer); | ||||||
|  | +		if (ret) | ||||||
|  | +			return ret; | ||||||
|  | + | ||||||
| +		ret = spi_qup_set_state(qup, QUP_STATE_RUN); | +		ret = spi_qup_set_state(qup, QUP_STATE_RUN); | ||||||
| +		if (ret) { | +		if (ret) { | ||||||
| +			dev_warn(qup->dev, "cannot set RUN state\n"); | +			dev_warn(qup->dev, "cannot set RUN state\n"); | ||||||
| +			return ret; | +			return ret; | ||||||
| +		} | +		} | ||||||
|   | + | ||||||
| -	if (!wait_for_completion_timeout(&qup->done, timeout)) |  | ||||||
| -		return -ETIMEDOUT; |  | ||||||
| +		ret = spi_qup_set_state(qup, QUP_STATE_PAUSE); | +		ret = spi_qup_set_state(qup, QUP_STATE_PAUSE); | ||||||
| +		if (ret) { | +		if (ret) { | ||||||
| +			dev_warn(qup->dev, "cannot set PAUSE state\n"); | +			dev_warn(qup->dev, "cannot set PAUSE state\n"); | ||||||
|   | |||||||
| @@ -44,58 +44,54 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> | |||||||
| -	ret = spi_qup_io_config(spi, xfer); | -	ret = spi_qup_io_config(spi, xfer); | ||||||
| -	if (ret) | -	if (ret) | ||||||
| -		return ret; | -		return ret; | ||||||
| - | +	rx_sgl = xfer->rx_sg.sgl; | ||||||
|  | +	tx_sgl = xfer->tx_sg.sgl; | ||||||
|  |   | ||||||
| -	/* before issuing the descriptors, set the QUP to run */ | -	/* before issuing the descriptors, set the QUP to run */ | ||||||
| -	ret = spi_qup_set_state(qup, QUP_STATE_RUN); | -	ret = spi_qup_set_state(qup, QUP_STATE_RUN); | ||||||
| -	if (ret) { | -	if (ret) { | ||||||
| -		dev_warn(qup->dev, "cannot set RUN state\n"); | -		dev_warn(qup->dev, "cannot set RUN state\n"); | ||||||
| -		return ret; | -		return ret; | ||||||
| -	} | -	} | ||||||
| - | +	do { | ||||||
|  | +		int rx_nents = 0, tx_nents = 0; | ||||||
|  |   | ||||||
| -	if (!qup->qup_v1) { | -	if (!qup->qup_v1) { | ||||||
| -		if (xfer->rx_buf) | -		if (xfer->rx_buf) | ||||||
| -			rx_done = spi_qup_dma_done; | -			rx_done = spi_qup_dma_done; | ||||||
| - | +		if (rx_sgl) { | ||||||
|  | +			rx_nents = sg_nents_for_len(rx_sgl, SPI_MAX_XFER); | ||||||
|  | +			if (rx_nents < 0) | ||||||
|  | +				rx_nents = sg_nents(rx_sgl); | ||||||
|  |   | ||||||
| -		if (xfer->tx_buf) | -		if (xfer->tx_buf) | ||||||
| -			tx_done = spi_qup_dma_done; | -			tx_done = spi_qup_dma_done; | ||||||
| -	} | -	} | ||||||
| - | +			qup->n_words = spi_qup_sgl_get_size(rx_sgl, rx_nents) / | ||||||
|  | +						qup->w_size; | ||||||
|  | +		} | ||||||
|  |   | ||||||
| -	if (xfer->rx_buf) { | -	if (xfer->rx_buf) { | ||||||
| -		ret = spi_qup_prep_sg(master, xfer->rx_sg.sgl, | -		ret = spi_qup_prep_sg(master, xfer->rx_sg.sgl, | ||||||
| -				      xfer->rx_sg.nents, DMA_DEV_TO_MEM, | -				      xfer->rx_sg.nents, DMA_DEV_TO_MEM, | ||||||
| -				      rx_done, &qup->done); | -				      rx_done, &qup->done); | ||||||
| -		if (ret) | -		if (ret) | ||||||
| -			return ret; | -			return ret; | ||||||
| +	rx_sgl = xfer->rx_sg.sgl; | +		if (tx_sgl) { | ||||||
| +	tx_sgl = xfer->tx_sg.sgl; | +			tx_nents = sg_nents_for_len(tx_sgl, SPI_MAX_XFER); | ||||||
|  | +			if (tx_nents < 0) | ||||||
|  | +				tx_nents = sg_nents(tx_sgl); | ||||||
|   |   | ||||||
| -		dma_async_issue_pending(master->dma_rx); | -		dma_async_issue_pending(master->dma_rx); | ||||||
| -	} | -	} | ||||||
| +	do { | +			qup->n_words = spi_qup_sgl_get_size(tx_sgl, tx_nents) / | ||||||
| +		int rx_nents = 0, tx_nents = 0; | +						qup->w_size; | ||||||
|  | +		} | ||||||
|   |   | ||||||
| -	if (xfer->tx_buf) { | -	if (xfer->tx_buf) { | ||||||
| -		ret = spi_qup_prep_sg(master, xfer->tx_sg.sgl, | -		ret = spi_qup_prep_sg(master, xfer->tx_sg.sgl, | ||||||
| -				      xfer->tx_sg.nents, DMA_MEM_TO_DEV, | -				      xfer->tx_sg.nents, DMA_MEM_TO_DEV, | ||||||
| -				      tx_done, &qup->dma_tx_done); | -				      tx_done, &qup->dma_tx_done); | ||||||
| +		if (rx_sgl) { |  | ||||||
| +			rx_nents = sg_nents_for_len(rx_sgl, SPI_MAX_XFER); |  | ||||||
| +			if (rx_nents < 0) |  | ||||||
| +				rx_nents = sg_nents(rx_sgl); |  | ||||||
| + |  | ||||||
| +			qup->n_words = spi_qup_sgl_get_size(rx_sgl, rx_nents) / |  | ||||||
| +						qup->w_size; |  | ||||||
| +		} |  | ||||||
| + |  | ||||||
| +		if (tx_sgl) { |  | ||||||
| +			tx_nents = sg_nents_for_len(tx_sgl, SPI_MAX_XFER); |  | ||||||
| +			if (tx_nents < 0) |  | ||||||
| +				tx_nents = sg_nents(tx_sgl); |  | ||||||
| + |  | ||||||
| +			qup->n_words = spi_qup_sgl_get_size(tx_sgl, tx_nents) / |  | ||||||
| +						qup->w_size; |  | ||||||
| +		} |  | ||||||
| + |  | ||||||
| + | + | ||||||
| +		ret = spi_qup_io_config(spi, xfer); | +		ret = spi_qup_io_config(spi, xfer); | ||||||
|  		if (ret) |  		if (ret) | ||||||
| @@ -109,17 +105,22 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> | |||||||
| +			dev_warn(qup->dev, "cannot set RUN state\n"); | +			dev_warn(qup->dev, "cannot set RUN state\n"); | ||||||
| +			return ret; | +			return ret; | ||||||
| +		} | +		} | ||||||
| + |   | ||||||
|  | -	if (xfer->rx_buf && !wait_for_completion_timeout(&qup->done, timeout)) | ||||||
|  | -		return -ETIMEDOUT; | ||||||
| +		if (!qup->qup_v1) { | +		if (!qup->qup_v1) { | ||||||
| +			if (rx_sgl) { | +			if (rx_sgl) { | ||||||
| +				rx_done = spi_qup_dma_done; | +				rx_done = spi_qup_dma_done; | ||||||
| +			} | +			} | ||||||
| + |   | ||||||
|  | -	if (xfer->tx_buf && !wait_for_completion_timeout(&qup->dma_tx_done, timeout)) | ||||||
|  | -		ret = -ETIMEDOUT; | ||||||
| +			if (tx_sgl) { | +			if (tx_sgl) { | ||||||
| +				tx_done = spi_qup_dma_done; | +				tx_done = spi_qup_dma_done; | ||||||
| +			} | +			} | ||||||
| +		} | +		} | ||||||
| + |   | ||||||
|  | -	return ret; | ||||||
| +		if (rx_sgl) { | +		if (rx_sgl) { | ||||||
| +			ret = spi_qup_prep_sg(master, rx_sgl, rx_nents, | +			ret = spi_qup_prep_sg(master, rx_sgl, rx_nents, | ||||||
| +					      DMA_DEV_TO_MEM, rx_done, | +					      DMA_DEV_TO_MEM, rx_done, | ||||||
| @@ -149,17 +150,12 @@ Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> | |||||||
| +			pr_emerg(" tx timed out\n"); | +			pr_emerg(" tx timed out\n"); | ||||||
| +			return -ETIMEDOUT; | +			return -ETIMEDOUT; | ||||||
| +		} | +		} | ||||||
|   | + | ||||||
| -	if (xfer->rx_buf && !wait_for_completion_timeout(&qup->done, timeout)) |  | ||||||
| -		return -ETIMEDOUT; |  | ||||||
| +		for (; rx_sgl && rx_nents--; rx_sgl = sg_next(rx_sgl)); | +		for (; rx_sgl && rx_nents--; rx_sgl = sg_next(rx_sgl)); | ||||||
| +		for (; tx_sgl && tx_nents--; tx_sgl = sg_next(tx_sgl)); | +		for (; tx_sgl && tx_nents--; tx_sgl = sg_next(tx_sgl)); | ||||||
|   | + | ||||||
| -	if (xfer->tx_buf && !wait_for_completion_timeout(&qup->dma_tx_done, timeout)) |  | ||||||
| -		ret = -ETIMEDOUT; |  | ||||||
| +	} while (rx_sgl || tx_sgl); | +	} while (rx_sgl || tx_sgl); | ||||||
|   | + | ||||||
| -	return ret; |  | ||||||
| +	return 0; | +	return 0; | ||||||
|  } |  } | ||||||
|   |   | ||||||
|   | |||||||
| @@ -85,7 +85,7 @@ More majordomo info at  http://vger.kernel.org/majordomo-info.html | |||||||
| +	}; | +	}; | ||||||
| --- a/drivers/clk/qcom/Kconfig | --- a/drivers/clk/qcom/Kconfig | ||||||
| +++ b/drivers/clk/qcom/Kconfig | +++ b/drivers/clk/qcom/Kconfig | ||||||
| @@ -2,6 +2,9 @@ | @@ -2,6 +2,9 @@ config QCOM_GDSC | ||||||
|  	bool |  	bool | ||||||
|  	select PM_GENERIC_DOMAINS if PM |  	select PM_GENERIC_DOMAINS if PM | ||||||
|   |   | ||||||
| @@ -95,7 +95,7 @@ More majordomo info at  http://vger.kernel.org/majordomo-info.html | |||||||
|  config COMMON_CLK_QCOM |  config COMMON_CLK_QCOM | ||||||
|  	tristate "Support for Qualcomm's clock controllers" |  	tristate "Support for Qualcomm's clock controllers" | ||||||
|  	depends on OF |  	depends on OF | ||||||
| @@ -9,6 +12,19 @@ | @@ -9,6 +12,19 @@ config COMMON_CLK_QCOM | ||||||
|  	select REGMAP_MMIO |  	select REGMAP_MMIO | ||||||
|  	select RESET_CONTROLLER |  	select RESET_CONTROLLER | ||||||
|   |   | ||||||
| @@ -117,7 +117,7 @@ More majordomo info at  http://vger.kernel.org/majordomo-info.html | |||||||
|  	select QCOM_GDSC |  	select QCOM_GDSC | ||||||
| --- a/drivers/clk/qcom/Makefile | --- a/drivers/clk/qcom/Makefile | ||||||
| +++ b/drivers/clk/qcom/Makefile | +++ b/drivers/clk/qcom/Makefile | ||||||
| @@ -29,3 +29,4 @@ | @@ -29,3 +29,4 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm896 | ||||||
|  obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o |  obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o | ||||||
|  obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o |  obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o | ||||||
|  obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o |  obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o | ||||||
|   | |||||||
| @@ -54,9 +54,9 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> | |||||||
|  	depends on COMMON_CLK_QCOM && QCOM_SMD_RPM |  	depends on COMMON_CLK_QCOM && QCOM_SMD_RPM | ||||||
| --- a/drivers/clk/qcom/Makefile | --- a/drivers/clk/qcom/Makefile | ||||||
| +++ b/drivers/clk/qcom/Makefile | +++ b/drivers/clk/qcom/Makefile | ||||||
| @@ -23,3 +23,4 @@ obj-$(CONFIG_MSM_GCC_8974) += gcc-msm897 | @@ -30,3 +30,4 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8 | ||||||
|  obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o |  | ||||||
|  obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o |  obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o | ||||||
|  |  obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o | ||||||
|  obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o |  obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o | ||||||
| +obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o | +obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o | ||||||
| --- /dev/null | --- /dev/null | ||||||
|   | |||||||
| @@ -1,6 +1,6 @@ | |||||||
| --- a/arch/arm/boot/dts/Makefile | --- a/arch/arm/boot/dts/Makefile | ||||||
| +++ b/arch/arm/boot/dts/Makefile | +++ b/arch/arm/boot/dts/Makefile | ||||||
| @@ -573,92 +573,61 @@ | @@ -573,92 +573,61 @@ dtb-$(CONFIG_ARCH_OMAP4) += \ | ||||||
|  	omap4-var-stk-om44.dtb |  	omap4-var-stk-om44.dtb | ||||||
|  dtb-$(CONFIG_SOC_AM43XX) += \ |  dtb-$(CONFIG_SOC_AM43XX) += \ | ||||||
|  	am43x-epos-evm.dtb \ |  	am43x-epos-evm.dtb \ | ||||||
| @@ -281,7 +281,10 @@ | |||||||
| +					0x00094 0x4e        /* PORT6_STATUS */ | +					0x00094 0x4e        /* PORT6_STATUS */ | ||||||
| +					>; | +					>; | ||||||
| +			}; | +			}; | ||||||
| + |   | ||||||
|  | -				nand-ecc-strength = <4>; | ||||||
|  | -				nand-ecc-step-size = <512>; | ||||||
|  | -				nand-bus-width = <8>; | ||||||
| +			phy4: ethernet-phy@4 { | +			phy4: ethernet-phy@4 { | ||||||
| +				device_type = "ethernet-phy"; | +				device_type = "ethernet-phy"; | ||||||
| +				reg = <4>; | +				reg = <4>; | ||||||
| @@ -306,10 +309,7 @@ | |||||||
| +			status = "ok"; | +			status = "ok"; | ||||||
| +			phy-mode = "sgmii"; | +			phy-mode = "sgmii"; | ||||||
| +			qcom,id = <2>; | +			qcom,id = <2>; | ||||||
|   | + | ||||||
| -				nand-ecc-strength = <4>; |  | ||||||
| -				nand-ecc-step-size = <512>; |  | ||||||
| -				nand-bus-width = <8>; |  | ||||||
| +			fixed-link { | +			fixed-link { | ||||||
| +				speed = <1000>; | +				speed = <1000>; | ||||||
| +				full-duplex; | +				full-duplex; | ||||||
|   | |||||||
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	 Felix Fietkau
					Felix Fietkau