generic: ar8216: allow to specify SGMII config via platform data
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 36798
This commit is contained in:
		@@ -1099,13 +1099,32 @@ ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
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		priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
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							priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
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		priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
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							priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
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		priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
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							priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
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							if (new_pos != pos)
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								new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
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	}
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						}
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	if (new_pos != pos) {
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						if (pdata->sgmii_cfg) {
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		new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
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							t = pdata->sgmii_cfg->sgmii_ctrl;
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		priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
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							if (priv->chip_rev == 1)
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								t |= AR8327_SGMII_CTRL_EN_PLL |
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								     AR8327_SGMII_CTRL_EN_RX |
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								     AR8327_SGMII_CTRL_EN_TX;
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							else
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								t &= ~(AR8327_SGMII_CTRL_EN_PLL |
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								       AR8327_SGMII_CTRL_EN_RX |
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								       AR8327_SGMII_CTRL_EN_TX);
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							priv->write(priv, AR8327_REG_SGMII_CTRL, t);
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							if (pdata->sgmii_cfg->serdes_aen)
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								new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
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							else
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								new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
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	}
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						}
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						priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
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	return 0;
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						return 0;
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}
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					}
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@@ -327,6 +327,7 @@
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#define AR8327_REG_POWER_ON_STRIP		0x010
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					#define AR8327_REG_POWER_ON_STRIP		0x010
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#define   AR8327_POWER_ON_STRIP_POWER_ON_SEL	BIT(31)
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					#define   AR8327_POWER_ON_STRIP_POWER_ON_SEL	BIT(31)
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#define   AR8327_POWER_ON_STRIP_LED_OPEN_EN	BIT(24)
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					#define   AR8327_POWER_ON_STRIP_LED_OPEN_EN	BIT(24)
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					#define   AR8327_POWER_ON_STRIP_SERDES_AEN	BIT(7)
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#define AR8327_REG_INT_STATUS0			0x020
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					#define AR8327_REG_INT_STATUS0			0x020
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#define   AR8327_INT0_VT_DONE			BIT(20)
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					#define   AR8327_INT0_VT_DONE			BIT(20)
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@@ -357,6 +358,11 @@
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#define AR8327_REG_HEADER_CTRL			0x098
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					#define AR8327_REG_HEADER_CTRL			0x098
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#define AR8327_REG_PORT_HEADER(_i)		(0x09c + (_i) * 4)
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					#define AR8327_REG_PORT_HEADER(_i)		(0x09c + (_i) * 4)
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					#define AR8327_REG_SGMII_CTRL			0x0e0
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					#define   AR8327_SGMII_CTRL_EN_PLL		BIT(1)
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					#define   AR8327_SGMII_CTRL_EN_RX		BIT(2)
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					#define   AR8327_SGMII_CTRL_EN_TX		BIT(3)
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#define AR8327_REG_PORT_VLAN0(_i)		(0x420 + (_i) * 0x8)
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					#define AR8327_REG_PORT_VLAN0(_i)		(0x420 + (_i) * 0x8)
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#define   AR8327_PORT_VLAN0_DEF_SVID		BITS(0, 12)
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					#define   AR8327_PORT_VLAN0_DEF_SVID		BITS(0, 12)
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#define   AR8327_PORT_VLAN0_DEF_SVID_S		0
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					#define   AR8327_PORT_VLAN0_DEF_SVID_S		0
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@@ -63,6 +63,11 @@ struct ar8327_port_cfg {
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	int duplex:1;
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						int duplex:1;
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};
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					};
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					struct ar8327_sgmii_cfg {
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						u32 sgmii_ctrl;
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						bool serdes_aen;
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					};
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struct ar8327_led_cfg {
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					struct ar8327_led_cfg {
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	u32 led_ctrl0;
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						u32 led_ctrl0;
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	u32 led_ctrl1;
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						u32 led_ctrl1;
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@@ -75,6 +80,7 @@ struct ar8327_platform_data {
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	struct ar8327_pad_cfg *pad0_cfg;
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						struct ar8327_pad_cfg *pad0_cfg;
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	struct ar8327_pad_cfg *pad5_cfg;
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						struct ar8327_pad_cfg *pad5_cfg;
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	struct ar8327_pad_cfg *pad6_cfg;
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						struct ar8327_pad_cfg *pad6_cfg;
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						struct ar8327_sgmii_cfg *sgmii_cfg;
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	struct ar8327_port_cfg port0_cfg;
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						struct ar8327_port_cfg port0_cfg;
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	struct ar8327_port_cfg port6_cfg;
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						struct ar8327_port_cfg port6_cfg;
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	struct ar8327_led_cfg *led_cfg;
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						struct ar8327_led_cfg *led_cfg;
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